KR19980043929A - Method of forming isolation film for semiconductor device - Google Patents

Abstract

The present invention is to provide a method for forming a device isolation film suitable for a highly integrated device. A method of forming an isolation layer of a semiconductor device for this purpose includes forming a first insulating layer on a substrate, a second insulating layer on the first insulating layer, and forming a first polycrystalline silicon layer on the second insulating layer. Patterning the polysilicon layer, the second insulating layer, and the first insulating layer to form a first isolation region and a second isolation region to which the substrate is exposed; and a substrate and a polysilicon layer of the first and second isolation regions Growing the first thermal oxide film on the substrate; removing the first thermal oxide film by the thickness grown in the second isolation region; and etching the substrate in the second isolation region from which the first thermal oxide film has been removed. Forming a second polycrystalline silicon layer on the entire surface of the substrate such that the second thermal oxide film is grown on the inner surface of the trench and the trench is sufficiently filled; and the trench and the second isolation region define the second isolation region. 1st insulation layer and 2nd Removing the second polysilicon layer so as to remain as sidewalls on the side of the insulating layer; growing a thermal oxide film on the second polycrystalline silicon layer remaining in the trenches and the second polycrystalline silicon layer remaining as the sidewalls and removing unnecessary second insulating layers; It is made, including the process.

Description

Method of forming isolation film for semiconductor device

The present invention relates to a method for manufacturing a semiconductor device of the present invention, and more particularly, to a method for forming an isolation film of a semiconductor device suitable for preventing a loading effect during etching and improving the uniformity of a process in the entire wafer area.

In general, as the degree of integration of semiconductor devices increases, technology developments for reducing field areas occupying a considerable area of semiconductor devices have been actively conducted.

This is to minimize the field area to improve the integration of the semiconductor device.

The LOCOS method has been mainly used as an isolation method for semiconductor CMOS devices.

However, due to the limitations of the LOCOS technology, devices with an integration density of 256M DRAM or higher can no longer be used as an isolation method.

LOCOS technology inserts a thin film pad oxide film between the nitride film and the silicon substrate to solve the stress caused by different thermal characteristics between the nitride film and the silicon substrate as oxide masks. Oxides (Oxidant: O ₂ ) are diffused and penetrated in the transverse direction through the relaxation pad oxide film as a passage, so that the field oxide film is grown under the pattern edge of the oxidation resistant nitride film.

Therefore, a phenomenon in which the field oxide film erodes the active region and the actual active region is reduced.

The phenomenon in which the field oxide film encroaches on the active region is called bird's beak because its shape is the same as that of a bird's beak, and the length of the buzz beak is 1/2 of the thickness of the field oxide film.

In order to reduce the loss of the active area, the length of the Buzzbeek should be minimized.

The method of reducing the thickness of the field oxide film was introduced as a method to reduce the Burj Beek, but the IC characteristics were increased due to the increase of the capacitance between the wiring and the substrate formed on the surface of the device generated by reducing the thickness of the field oxide film at 16M DRAM or higher. The problem of lowering, that is, lowering of the signal transmission speed (t = RC) occurs.

Where t is the delay time, R is the resistance, and C is the capacitance between the wiring and the substrate.

In addition, the threshold voltage of the parasitic transistor whose gate is the field region between the device and the device is reduced, and the isolation characteristic between the device and the device is greatly reduced.

Therefore, a new method for reducing buzz bequee has emerged, and its representative techniques are PBLOCOS (Poly Si Buffered LOCOS) technology in which the thickness of the stress relieving pad oxide film is reduced and polysilicon is interposed between the nitride film and the substrate. Sealed interface LOCOS (SiLO) technology that protects the sidewall of the pad oxide film with a silicon nitride film, and recess LOCOS technology that recesses the substrate.

The above-mentioned problems and securing the flatness of the surface of the newly separated region have a great effect on the phantom resolution during the pattern formation of the post process, especially the wiring process. ) And tight design specifications (buzzbee, i.e., loss of active area should be almost zero in 256M DRAM), making it unsuitable for next-generation devices.

Therefore, BOX (buried oxide) trench isolation technology has come into the spotlight as an isolation technology that can overcome the problems of existing LOCOS type device isolation technology.

The BOX type device isolation technology has a structure in which a trench is formed on a silicon substrate and a CVD oxide film is embedded, so that it can be configured at any interval between devices, and there is no buzz beating the active region found in the LOCOS structure.

Therefore, there is no loss of the active region and there is an advantage that the CVD oxide film can be buried and completely planarized.

Hereinafter, a method of forming a BOX type device isolation layer according to the related art will be described with reference to the accompanying drawings.

1A to 1F are process cross-sectional views illustrating a method of forming a separator of a conventional semiconductor device.

First, as shown in FIG. 1A, a thermal oxide film 12 is grown on a silicon substrate 11, and a CVD nitride film 13 is stacked on the thermal oxide film 12.

Subsequently, as shown in FIG. 1B, a photoresist (not shown) is applied onto the CVD nitride film 13, and then the photoresist is patterned through an exposure and development process.

Subsequently, the CVD nitride film 13 and the thermal oxide film 12 below are selectively removed using the patterned photoresist as a mask.

As shown in FIG. 1C, trenches having different widths are removed by etching the silicon substrate 11 to a predetermined depth by using the patterned CVD nitride film 13 and thermal oxide film 12 as a mask. To form (14, 14a).

As shown in FIG. 1D, a CVD oxide film 15 is deposited on the entire surface including the transistors 14 and 14a.

Subsequently, as illustrated in FIG. 1E, the surface of the substrate 11 is planarized by coating a photoresist 16 or a spin on glass (SOG) on the CVD oxide film 15.

At this time, the trench 14 having a relatively wide width among the trenches 14 and 14a is recessed by the depth of the trench 14 because the CVD oxide film 15 is equally buried.

Subsequently, as shown in FIG. 1F, the photoresist 16 is etched back at the same etching rate as the CVD oxide film 15 by chemical mechanical mirror polishing (CMP) or reactive ion etching (RIE).

Therefore, the CVD oxide film 15 on the active region is completely removed.

The process is the same as the general semiconductor device manufacturing process.

However, the method of forming a device isolation film of the conventional semiconductor device has the following problems.

First, since the thickness of the photoresist applied for the surface planarization is unevenly applied according to the density of the pattern, a critical photoresist etchback process is required because the photoresist is thinly applied in the highly integrated region.

That is, since the thickness of the CVD oxide film and the photoresist is non-uniform, the surface of the active region is severely damaged during etching, even after the etch back process.

Second, since the wide field region and the relatively narrow field region are etched differently from each other, there is a dishing problem in which the amount of locally etched back varies due to the nonuniformity or loading effect of the CVD oxide film over the entire wafer surface. Is generated.

Therefore, although the conventional technology is suitable as a method for isolating high integration devices, there are many technical problems in applying it to actual products.

That is, it is very difficult to apply the prior art to a highly integrated semiconductor device without solving the loading effect or dishing problem.

An object of the present invention is to provide a method for forming an isolation layer of a semiconductor device suitable for a highly integrated semiconductor device by eliminating the loading effect or dishing problem to solve the above problems.

1A to 1F are process diagrams showing a method of forming a separator of a conventional semiconductor device.

2A to 2K are process drawings showing a method of forming a separator of a semiconductor device of the present invention.

* Description of the symbols for the main parts of the drawings *

21 silicon substrate 22 first thermal oxide film

23: first insulating layer 24: first polycrystalline silicon layer

25: first isolation region 25a: second isolation region

26: second thermal oxide film 27: trench

28: third thermal oxide film 29: second polycrystalline silicon layer

29a: side wall 30: fourth thermal oxide film

In order to achieve the above object, an isolation film forming method of a semiconductor device of the present invention comprises the steps of forming a first insulating layer on a substrate, a second insulating layer on the first insulating layer, and a first on the second insulating layer. Forming a first isolation region and a second isolation region to which the substrate is exposed by patterning the polysilicon layer, the second insulation layer, and the first insulation layer after the polysilicon layer is formed; Growing a first thermal oxide film on the substrate and the polysilicon layer in the isolation region, removing the first thermal oxide film by the thickness grown in the second isolation region, and separating the second thermal oxide film from the second isolation region. Etching a substrate in the region to form a trench; growing a second thermal oxide film on the inner surface of the trench and forming a second polysilicon layer on the front surface of the substrate so that the trench is sufficiently buried; 2 Set the isolation area Removing the second polysilicon layer so that the sidewalls of the first insulating layer and the second insulating layer remain as sidewalls; and a thermal oxide film on the second polycrystalline silicon layer remaining in the trenches and the second polysilicon layer remaining as the sidewalls. Growing and removing unnecessary second insulating layers.

Hereinafter, a method of forming an isolation layer of a semiconductor device of the present invention will be described with reference to the accompanying drawings.

First, the isolation film forming method of the semiconductor device of the present invention eliminates the loading effect in which the wide field region and the relatively narrow field region are etched differently according to the pattern density by the trench formation, and the CVD oxide film is unevenly distributed over the entire surface of the wafer. This is to solve the dishing problem in which the amount of local etch back is different due to the loading effect.

In addition, in order to prevent the threshold voltage of the active transistor caused by the contact between the edge portion of the sharp trench and the gate line, the structure of the trench formed in a narrow space must be improved.

For this purpose, the trench is made of polysilicon and the surface of the trench is oxidized so that the LOCOS oxide film is mounted on the surface so that the gate line passing through the trench region is formed in the same structure as the existing LOCOS oxide film.

2A to 2J are cross-sectional views illustrating a method of forming an isolation film of a semiconductor device of the present invention.

As shown in FIG. 2A, a first thermal oxide film 22 is grown on the silicon substrate 21, and a first insulating layer 23 is formed on the first thermal oxide film 22.

In this case, the material of the first insulating layer 23 is silicon nitride, the thickness thereof is in the range of 1000 to 1500 kPa, and the thickness of the first thermal oxide film 22 is 200 kPa.

Next, as shown in FIG. 2B, a first polysilicon layer 24 is formed on the first insulating layer 23.

At this time, the thickness of the first polysilicon layer 24 is in the range of 1000 to 1500 kPa, most preferably 1500 kPa.

Here, the thickness of the first polycrystalline silicon 24 determines the thickness of the thermal oxide film grown on the first polycrystalline silicon 24 in a later step.

Next, as shown in FIG. 2C, the photoresist 25 is coated on the first polysilicon layer 24 and patterned through an exposure and development process to relatively narrow the first isolation region 25 having a wide width. A second isolation region 25a having a width is defined.

The silicon substrate 21 is selectively removed by using the patterned photoresist 25 as a mask to selectively remove the first polycrystalline silicon layer 24, the first insulating layer 23, and the first thermal oxide layer 22. Expose

As shown in FIG. 2D, the photoresist 25 is removed, and a second thermal oxide layer 26 having a thickness of 2000 μs is formed on the exposed silicon substrate 21 and the first polycrystalline silicon layer 24. To grow.

At this time, the second thermal oxide film 26 grown on the surface of the patterned polysilicon layer 24 is overgrown toward the isolation regions on both sides thereof.

In addition, the second thermal oxide film 26 on the left and right sides are brought into contact with each other around the second isolation region 25a having a relatively narrow width, thereby exposing the silicon substrate 21 exposed at a narrow width from the oxidizing component O ₂ . Block.

Therefore, the thickness of the second thermal oxide film 26 grown on the silicon substrate 21 in the narrow second isolation region 25a is adjusted thinly.

Here, since the second thermal oxide film 26 grown on the silicon substrate 21 of the wide first isolation region 25 is exposed to the oxidizing component as it is, the thickness of the second isolation region 25a of the narrow width is narrow. Thicker than the thickness of the second thermal oxide film 26 grown on the silicon substrate 21.

Subsequently, as shown in FIG. 2E, the silicon substrate 21 is immersed in HF aqueous solution to remove the thickness of the second thermal oxide film 26 grown on the silicon substrate 21 of the second isolation region 25a having the narrow width. do.

Accordingly, the second thermal oxide layer 26 grown on the silicon substrate 21 of the first isolation region 25 is not removed, and the second column grown on the silicon substrate 21 of the second isolation region 25a is not removed. Only the thickness of the oxide film 26 is removed.

Next, as illustrated in FIG. 2F, the trench 27 is formed by dry etching the exposed silicon substrate 21 of the second isolation region 25a.

At this time, the length of the trench 27 is in the range of 3500 ~ 4000Å and most preferably set to 4000Å.

As shown in FIG. 2G, when the silicon substrate 21 is thermally oxidized in an oxidative atmosphere, a third thermal oxide layer 28 is grown on the exposed silicon substrate 21 in the trench 27.

At this time, the thickness of the third thermal oxide film 28 is grown in the range of 100 ~ 150Å.

Subsequently, as shown in FIG. 2H, a second polycrystalline silicon layer 19 is formed on the silicon substrate 21 including the second thermal oxide film 26 to form a second polycrystalline silicon layer 29 in the trench 27. ) Landfill completely.

As shown in FIG. 2I, the second polysilicon layer 29 is etched back, leaving the second polysilicon layer 29 embedded in the trench 27 as it is and removing the rest.

At this time, sidewalls 29a are formed on side surfaces of the first thermal oxide film 22 and the first insulating layer 23 defining the first isolation region 25.

Subsequently, as illustrated in FIG. 2J, when the silicon substrate 21 is thermally oxidized in an oxidative atmosphere, a fourth thermal oxide layer 30 is grown on the second polycrystalline silicon layer 29 embedded in the trench 27.

The sidewall 29a formed of the second polysilicon layer 29 is oxidized to be connected to the second thermal oxide film 26 grown on the silicon substrate 21 of the first isolation region 25.

At this time, the thickness of the fourth thermal oxide film 30 grown on the second polysilicon layer 29 embedded in the trench 27 is in the range of about 1000 to 1500 kW and most preferably adjusted to 1500 kW.

Subsequently, as shown in FIG. 2K, the process of forming the semiconductor device isolation film of the present invention is performed by removing the first insulating layer 23 on the active region and the first thermal oxide film 22 formed on the silicon substrate 21 of the active region. To complete. The process is the same as the general semiconductor device manufacturing process.

As described above, the isolation film forming method of the semiconductor device of the present invention has the following effects.

First, there is no loading effect that is etched differently in narrow and wide isolation regions.

Second, since the backing is etched in a uniform amount over the entire surface of the wafer, the dishing problem does not occur, thereby maintaining the uniformity of the process.

Third, since the shape of the field oxide film can be arbitrarily adjusted, the process margin of the pattern alignment in the later process is improved.

Fourth, the lowering of the threshold voltage of the active transistor is prevented.

Claims (7)

Forming a first insulating layer on the substrate, and then forming a second insulating layer on the first insulating layer; Forming a first isolation region and a second isolation region to expose the substrate by forming a first polycrystalline silicon layer on the second insulating layer and then patterning a polysilicon layer, a second insulating layer, and a first insulating layer; , Growing a first thermal oxide film on the substrate and the polysilicon layer in the first and second isolation regions; Removing the first thermal oxide film by a thickness grown in the second isolation region; Etching the substrate in the second isolation region from which the first thermal oxide film has been removed to form a trench; Growing a second thermal oxide film on the inner surface of the trench and forming a second polysilicon layer on the front surface of the substrate to sufficiently fill the trench; Removing a second polycrystalline silicon layer such that the trench and the second insulating region define sidewalls on side surfaces of the first insulating layer and the second insulating layer; And growing a thermal oxide film on the second polysilicon layer remaining in the trench and the second polysilicon layer remaining on the sidewalls and removing the unnecessary second insulating layer. The method of claim 1, wherein the first isolation region has a relatively wider width than the second isolation region. The method of claim 1, wherein the first thermal oxide film has a thickness of 2000 microns. The method of claim 1, wherein the trench has a depth in the range of 3500 to 4000 μs. The method of claim 1, wherein the thickness of the second thermal oxide film is in a range of 100 to 150 kPa. The method of claim 1, wherein the thickness of the first polycrystalline silicon layer is in the range of 1000 to 1500 kHz. The method of claim 1, wherein an amorphous silicon layer is applied instead of the second polycrystalline silicon layer.