KR19980043656A - High speed MPEG decoder and its run length error processing method - Google Patents

Abstract

The present invention relates to a fast MPEG decoding apparatus and a run length error processing method thereof, which enable proper processing of a corresponding slice when a run length error occurs when decoding into a plurality of paths. The present invention includes a header decoder which determines the skipped macroblock flag signal by comparing the vertical position information of the slice and the macroblock order information detected from the header information with the row counter value and the macroblock counter value at that time. When the variable length decoding apparatus detects a run length error and sends related information, the header decoder enables the skipped macroblock flag signal and decodes the block pattern signal to 0 and outputs it. The plurality of run / level decoders output 64 zero values as run / level decoded data for all blocks while the block pattern and the block read signal are zero. Therefore, there is an effect that can reduce the burden on the system clock and prevent the harmful effects on the system.

Description

High speed MPEG decoder and its run length error processing method

The present invention relates to an MPEG decoding device that requires a high processing speed. In particular, when a run-length error occurs during decoding by dividing into multiple paths, the present invention is suitable for a corresponding slice. A high speed MPEG decoder and its run length error processing method are provided.

Recently, in systems such as high-definition television (HD-TV), digital VTR and camcorder, multimedia, video telephone, etc., video and audio are encoded into digital signals, transmitted or stored on a recording medium, and decoded and played back. The method is mainly used. In such an encoding and decoding system, a technique for compressing a transmission data amount more effectively is required to maximize data transmission efficiency. In general, a MPEG (Moving Picture Experts Group) decoding apparatus receives a bit stream that is compressed and encoded, interprets header information added to the bit stream, and converts the input bit stream into an original process through an inverse process of encoding. Restore to the signal of. At this time, decoding of the header information and decoding of the encoded coefficient are performed through a single path.

In performing decoding as described above, a general system clock is used in a medium belonging to a main level (ML) that needs to process a bit string having a small encoding amount. However, in the case of a medium belonging to a high level (HL) such as high-definition television (HD-TV), since a large amount of data must be processed, the decoding operation must be performed at a high speed. A system clock of at least 100 MHz is required for high speed operation. Hardware capable of operating using such a system clock is difficult to implement, and even if the hardware is implemented, there is a problem of excessively increasing manufacturing costs.

Conventionally, to solve this problem, an apparatus for decoding four luminance signal blocks, two color difference signal blocks, and a DC (direct current component) coefficient in a macroblock through a plurality of paths has been developed. This decoding apparatus has the advantage of reducing the burden on the system clock because it can process the input bit stream at a high speed without increasing the system clock speed in a medium requiring a high processing speed. In addition, there is no need to implement the hardware to generate a high-frequency system clock has the advantage of reducing the manufacturing cost.

As described above, a general decoding apparatus for decoding in a single path includes a circuit for appropriately processing a slice in which an error occurs when a run length error occurs in a variable length decoder (VLD). However, a device that decodes a plurality of paths in consideration of a high processing speed has a problem in that encoded data cannot be properly restored because there is no circuit that can cope with a run length error in a variable length decoder.

It is an object of the present invention to reduce the burden on a plurality of decoders and system clocks by decoding encoded data into a plurality of paths without increasing the system clock speed in a medium requiring a high processing speed. An apparatus and its run length error handling method are provided.

Another object of the present invention is to check the transmitted error-related information when a run length error occurs in the process of decoding a plurality of paths, and to check the slice from the slice currently being decoded until the next start code is detected. The present invention provides a high speed MPEG decoder and its run length error processing method.

1 is a block diagram showing a schematic configuration of a fast MPEG decoding apparatus to which the present invention is applied.

2 is a timing relationship diagram for explaining a processing method for a slice in which a run length error occurs when decoding an encoded input bit string.

※ Explanation of code for main part of drawing

1,7,15 Demultiplexers 2 to 4 FIFO memory

5,13: run / level decoder 6,14: scan converter

10,18: multiplexer 11,19: inverse quantizer

12,20: reverse DCT 22: header decoder

The high speed MPEG decoding apparatus of the present invention for achieving the above object is provided with a variable length decoding apparatus for detecting a run length error from the input bit string and sending the variable length decoded data and the error-related information to a plurality of paths . The plurality of FIFO memories store data and header information separated into a plurality of paths through a variable length decoding apparatus. The header decoder connected to one FIFO memory determines the skipped macroblock flag signal by comparing the vertical position information of the slice and the macroblock order information detected from the header information with the row counter value and the macroblock counter value at that time. If the signal is enabled, the block pattern signal is decoded to zero. A plurality of run / level decoders respectively connected to the remaining FIFO memories determine the block read signal according to the block pattern signal and run / level decode the data according to the block read signal. At this time, 64 zero values are output as run / level decoded data for all blocks while the block pattern and the block read signal are zero.

In addition, the run length error processing method of the high-speed MPEG decoding apparatus of the present invention detects the vertical position information of the slice and the order information of the macroblock from the decoded header information and latches them in the register, and the vertical position of the latched slice. A second step of enabling or disabling the skipped macroblock flag signal by comparing the information and the sequence information of the macroblock with the row counter value and the macroblock counter value at that time; and the macroblock normally according to the skipped macroblock flag signal. A third process may be performed to perform run / level decoding or to output the run / level decoding output as 0 for a predetermined period.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2 as follows.

1 is a block diagram showing a schematic configuration of a fast MPEG decoding apparatus to which the present invention is applied. The apparatus of the present invention receives data indicating that a variable length decoded data and a run length error have occurred from a variable length decoding apparatus (VLD) (not shown). Reference numeral 1 is a first demultiplexer. The input demultiplexer divides the input bit string and outputs header information and data divided into two paths A and B, respectively, through the corresponding path. Three FIFOs (First In First Out) memories 2 to 4 are connected to an output terminal of the first demultiplexer 1. These FIFO memories (2 to 4) store data in the order in which they are input, and then output the data first inputted when there is an output request.

The first FIFO memory 2 stores data corresponding to two luminance signal blocks 1 and 3 and one color difference signal block U positioned above one macro block. Similarly, the second FIFO memory 3 stores data corresponding to two luminance signal blocks 2 and 4 and one chrominance signal block V positioned lower in one macro block. The third FIFO memory 4 receives the header information from the first demultiplexer 1, temporarily stores the header information, and outputs the data in order. Two identical devices are connected to the output terminals of the first and second FIFO memories 2 and 3 so as to perform parallel processing in the path A and the path B in the same manner.

The first run / level decoder 5 connected to the output of the first FIFO memory 2 decodes the input data through the reverse process of run / level encoding to extend the compressed data. A first scan converter 6 composed of two memories, a demultiplexer, and a multiplexer is connected to an output terminal of the first run / level decoder 5. In the first scan converter 6, the second demultiplexer 7 divides the data output from the first run / level decoder 5 and inputs the data to the first memory 8 and the second memory 9, respectively. Let's do it. The first multiplexer 10 reads the data stored in the two memories 8 and 9 and multiplexes the data in a manner different from that before the data is input to the first scan converter 6. The data that has passed through the first scan converter 6 is then converted into a video signal of another scan method which has undergone the reverse process of the scan performed by the encoding apparatus.

The first inverse quantizer 11 connected to the output terminal of the first scan converter 6 performs inverse quantization on the input video data corresponding to the quantization of the encoding apparatus. A first inverse DCT (Discrete Cosine Transform) unit 12 is connected to an output terminal of the first inverse quantizer 11, and the first inverse DCT unit 12 inverse-DCT transforms the inverse quantized data and the DC coefficient. It reconstructs the moving picture data before encoding. On the other hand, the same devices as in the aforementioned path A are connected to the output terminal of the second FIFO memory 3 to form the path B. That is, the second FIFO memory 3, the second run / level decoder 13, the third demultiplexer 15, and the third and fourth memories 16, 17, and the second multiplexer 18 are formed. The second scan converter 14, the second inverse quantizer 19, and the second DCT unit 20 are connected in order to perform the same operation as in the path A.

A DC decoder 21 is also connected to the output terminals of the first and second FIFO memories 2 and 3. The DC decoder 21 reads the DC coefficient of the Intra macroblock from the data input from the two FIFO memories 2 and 3 and dequantizes it. The dequantized DC coefficients are input to the first and second inverse DCT units 12 and 20, respectively. A header decoder 22 and a quantization matrix decoder 23 are connected to an output terminal of the third FIFO memory 4. The header decoder 22 receives header information separated from the third FIFO memory 4 and generates various parameters necessary for decoding coefficient data. In addition, the quantization matrix decoder 23 receives separated header information and generates a quantization matrix necessary for dequantizing coefficient data.

The operation of the high speed MPEG decoding apparatus configured as described above and the run length error processing method of the present invention will be described with reference to the timing diagram of FIG.

In general, variable-length coding is a pair of runs (number of consecutive zeros) and levels (any nonzero value) paired together to form a single sign. When video data is encoded in this manner, the sum of the runs in any block is less than or equal to 64 in a steady state. The run length error to be processed in the present invention occurs when the sum of runs corresponding to any one block is 64 or more, and is usually found in a variable length decoding apparatus. The variable length decoding apparatus calculates the sum of runs corresponding to any one block and determines that the run length error is 64 or more, and sends information about the error to the first demultiplexer 1. In addition, as soon as an error is found, the next start code is found, and all data until the start code is found is not output. Here, the method of calculating the sum of the runs is described in MPEG data ISO / IEC 13818-2 variable length decoding.

FIG. 2 is a timing relationship diagram for describing a processing method for a slice in which a run length error occurs when decoding an input bit string encoded by the apparatus of FIG. 1. In FIG. 1, as described above, the first demultiplexer 1 has data corresponding to 1, 3, and U blocks in one macroblock as path A, and data corresponding to 2, 4, and V blocks as path B, respectively. Send it. At this time, information about the error is sent to both path A and path B as soon as they are found. The first to third FIFO memories 2 to 4 storing the data sent from the first demultiplexer 1 do not store the data after the error occurs until the start code of the next slice is found.

When run / level decoding the data read out from the first and second FIFO memories 2 and 3, the decoding of the path A and the path B starts synchronously in block units, and also in macroblock units (Fig. 2). c, d waveform). The third FIFO memory 4, which stores the header information sent from the first demultiplexer 1, reads the header information in units of macroblocks every time the header read signal shown in FIG. b waveform). At this time, the header information of any macroblock is read from the third FIFO memory 4 before the run / level decoding of the macroblock data and then decoded. That is, when decoding the m + 1th macroblock [MB (m + 1)] in the first and second run / level decoders 5 and 13 (see c and d waveforms in FIG. 2), the third FIFO memory. In (4), header information of the first macroblock of the next slice is output (see b waveform in FIG. 2).

When the header decoder 22 detects the vertical position information of the slice (slice_vertical_position (see e-waveform in FIG. 2)) and the order information of the macroblock (mb_column (see g-waveform in FIG. 2)) from the input header information, the header decoder 22 registers them. Latch on the At this time, the vertical position information (slice _vertical_position) of the latched slice and the order information (mb_column) of the macroblock are the values of the slices after the error occurrence is completed regardless of whether the error occurs over one or several slices. For example, if an error occurs in the m + 1th macroblock MB (m + 1) of path A as shown in the timing diagram of FIG. 2, the vertical position (slice _vertical_position) of the latched slice is (n + α). ) And the macroblock order (mb_column) is β. In the information [slice_vertical_position (n + α)] of the next slice shown in FIG. 2E, α may be 0 or 1 or more. If one row is divided into multiple slices, an errored slice is included in the current decoding row, and the next slice is included in the current decoding row, α becomes zero. However, if the next slice is on a different row than the failed slice, α is one or more.

Meanwhile, the above-described header readout signal (see waveform a in FIG. 2) is enabled when the first and second run / level decoders 5 and 13 start decoding the second block, and then the macro is enabled. It is disabled at the last header data position of the block. In this case, the skipped macroblock flag must be in a zero state as shown in FIG. The skipped macroblock flag signal that enables the header readout signal in macroblock units may be configured to convert the vertical position information (slice_vertical_position) of the latched slice and the sequence information (mb_column) of the macroblock to the row counter at that time. Enable or disable by comparing with the Row Counter) value and the macroblock counter value.

The condition for enabling the skipped macroblock flag signal is when the slice_vertical_position and the row counter value of the slice are not the same or the order value (mb_column) and the macroblock counter value of the macroblock are not the same. This is a case where an error occurs, in which the vertical position value (see e-waveform in FIG. 2) of the slice latched in FIG. 2 is (n + α) but the row counter value (see f-waveform in FIG. 2) is n. In addition, the ordered value of the latched macroblock (see g waveform in FIG. 2) is β, but the macroblock counter value (see h waveform in FIG. 2) is m + 2, m + 3,... If

The time when the skipped macroblock flag signal is disabled is when the first and second run / level decoders 5 and 13 start decoding the second block, such as the timing for enabling the header read signal. In an error-free situation, the macroblock counter value is equal to or larger than the macroblock order value (mb_column). Therefore, when the skipped macroblock flag signal is in the 0 state, the slice_vertical_position and the row counter value of the slice are equal to (n + α), and the order value (mb_column) and macroblock counter value of the macroblock are β. do.

Here, β is the first macroblock of the next slice, and the point at which the header read signal for reading the header of the β + 1st macroblock [MB (β + 1)] is enabled is the β-th macroblock [MB (β)]. It is time to start run / level decoding the second block of. By doing so, even when an error occurs, the timing of reading the header of the macroblock and the run / level decoding of the paths A and B are properly adjusted. The above-described row counter and macroblock counter are changed in units of rows and macroblocks when decoding is performed by the first and second run / level decoders 5 and 13, respectively. That is, the row counter changes when the macro block counter starts the run / level decoding of the next macro block with the macro block width (mb_width, refer to MPEG data), and the macro block counter starts decoding the first block in units of macro blocks. It is changing.

The header decoder 22 reads the header of any macro block from the third FIFO memory 4 in accordance with the header read signal. At this time, the header reading completion time should be the decoding completion time of the macroblock currently being decoded by the first and second run / level decoders 5 and 13 as shown in FIG. In particular, the header decoder 22 checks the state of the skipped macroblock flag before ending the run / level decoding of the macroblock. If the skipped macroblock flag signal is 1, the coded block pattern signal coded_block_pattern is decoded to 0 and sent to the first and second run / level decoders 5 and 13. The first and second run / level decoders 5 and 13 determine the block read signal block_read of each block by checking the coded block pattern signal coded_block_pattern before starting decoding of every block. This block read signal (block_read) is zero only for all macroblocks from the macroblock after the error-producing macroblock to the next slice. The first and second run / level decoders 5 and 13 output 64 zero values for all blocks while the block read signal block_read is zero.

When the run length error occurs, the first and second run / level decoders 5 and 13 operate individually to perform appropriate processing. For example, if an error occurs in the m + 1th macroblock MB (m + 1) of path A (see also the timing in FIG. 2), the first run / level decoder 5 detects that the error information is found. The decoding output from the time point until the first macroblock of the next slice is set to 0 and output. As described above, a method of generating and processing a skipped macroblock flag when a run length error occurs is the same as a method of generating a skipped macroblock flag to process a skipped macroblock defined in MPEG.

As described above, the present invention reduces the burden on a plurality of decoders and system clocks by decoding the encoded data into multiple paths without increasing the system clock speed in a medium requiring a high processing speed. There is. In addition, if a run-length error occurs, the decoding output from the time the error is detected to the first macroblock of the next slice is replaced with 0, which prevents a fatal effect on the system and prevents the user from feeling that an error has occurred. have.

Claims (11)

An apparatus for decoding a coded bit string divided into a plurality of paths, Variable length decoding apparatus that detects a run length error from an input bit string and sends the variable length decoded data and the error related information through a plurality of paths and outputs no data until the start code of the next slice is detected after the error is detected. Wow; A plurality of FIFO memories for storing data and header information separated into a plurality of paths through a variable length decoding apparatus and outputting the first input data whenever an output request is made; The sliced macroblock flag signal is determined by comparing the vertical position information of the slice and the macroblock order information detected from the header information with the row counter value and the macroblock counter value at that time, and if the signal is enabled, the block pattern signal A header decoder that decodes 0 into 0; The block read signal of each block is determined according to the block pattern signal, and 64 blocks of all blocks while the block pattern and the block read signal are zero are run / level decoded or the block pattern and the block read signal are 0 according to the block read signal. And a plurality of run / level decoders for outputting zero values as run / level decoded data. The high-speed MPEG decoding apparatus of claim 1, wherein the variable length decoding apparatus calculates a sum of runs corresponding to any one block of the input bit strings and determines that a run length error has occurred when 64 or more. The FIFO memory of claim 1, further comprising: a first FIFO memory for storing upper two luminance signal blocks (1,3) and one color difference signal block (U) data in a macro block; A second FIFO memory for storing the lower two luminance signal blocks 2 and 4 and one color difference signal block V data; And a third FIFO memory configured to read and output header information in units of macroblocks each time a header read signal is enabled. 4. The header read signal of claim 3, wherein the header read signal is enabled when the run / level decoder starts decoding the second block when the skipped macroblock flag signal is in a disabled state, and then the last header data position of the macroblock. A high speed MPEG decoding apparatus, characterized in that disabled in the. 2. The high speed MPEG decoding apparatus of claim 1, wherein the header decoder is configured to decode header information of an arbitrary macroblock by one macroblock before run / level decoding of the macroblock data. In the method of decoding a coded bit string divided into a plurality of paths, A first step of detecting vertical position information of the slice and order information of the macroblock from the decoded header information and latching them in a register; A second step of enabling or disabling the skipped macroblock flag signal by comparing the vertical position information of the latched slice and the sequence information of the macroblock with the row counter value and the macroblock counter value at that time; Run length in a high speed MPEG decoding apparatus comprising a third process of normally performing run / level decoding of a macroblock according to a skipped macroblock flag signal or outputting the run / level decoding output to 0 for a predetermined period of time Error handling method. 7. The run length error process of claim 6, wherein the vertical position information of the slice latched in the first process and the sequence information of the macro block are set to the value of the slice after the occurrence of an error. Way. 7. The method of claim 6, wherein the condition for enabling the skipped macroblock flag signal in the second step is that an error occurs and the vertical position value and the row counter value of the slice are not the same, or the order value and the macroblock counter value of the macroblock are different. A run length error processing method in a high speed MPEG decoding apparatus, characterized in that the case is not equal. 7. The method of claim 6, wherein the condition for disabling the macroblock flag signal skipped in the second process is equal to the vertical position value of the slice and the row counter value, or the macroblock counter value is equal to or equal to the order value of the macroblock. In a large case, the run length error processing method of the high speed MPEG decoding apparatus, characterized in that it is disabled when the second block of the macro block starts to run / level decoding. 7. The method of claim 6, wherein in the second process, the row counter value is changed in units of rows when the macro block counter value is the macro block width and the start / level decoding of the next macro block is started, and the macro block counter value is the first in the macro block unit. A run length error processing method in a high speed MPEG decoding apparatus characterized by changing at the start of decoding a block. 7. The method of claim 6, wherein the third step comprises: examining the skipped macroblock flag signal and decoding the encoded block pattern signal to 0 when the enabled macroblock flag signal is enabled; Examining a block pattern signal and determining a block read signal of each block as 0 before starting decoding of every block; And outputting 64 zero values for all blocks while the block read signal is zero as run / level decoded data.