KR19980043612A - Device isolation film formation method of semiconductor device - Google Patents

Device isolation film formation method of semiconductor device Download PDF

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KR19980043612A
KR19980043612A KR1019960061542A KR19960061542A KR19980043612A KR 19980043612 A KR19980043612 A KR 19980043612A KR 1019960061542 A KR1019960061542 A KR 1019960061542A KR 19960061542 A KR19960061542 A KR 19960061542A KR 19980043612 A KR19980043612 A KR 19980043612A
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South Korea
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film
device isolation
forming
semiconductor device
nitride film
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KR1019960061542A
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Korean (ko)
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KR100418300B1 (en
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유석빈
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Abstract

본 발명은 반도체 소자의 소자분리막 형성 방법에 관한 것으로, 버즈빅의 생성을 방지하기 위하여 소자분리 영역 양측부의 실리콘 기판에 미세한 크기의 트렌치를 형성하므로써 버즈빅의 생성을 억제하며 표면의 평탄도를 향상시킬 수 있도록 한 반도체 소자의 소자분리막 형성 방법에 관한 것이다.The present invention relates to a method for forming a device isolation film of a semiconductor device, in order to prevent the formation of a buzz big, by forming a small trench in the silicon substrate on both sides of the device isolation region to suppress the formation of the buzz big and improve the flatness of the surface The present invention relates to a device isolation film forming method of a semiconductor device.

Description

반도체 소자의 소자분리막 형성 방법Device isolation film formation method of semiconductor device

본 발명은 반도체 소자의 소자분리막 형성 방법에 관한 것으로, 특히 버즈빅(Bird's Beak)의 생성을 억제하며 표면의 평탄도를 향상시킬 수 있도록 한 반도체 소자의 소자분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device, and more particularly, to a method of forming a device isolation film of a semiconductor device to suppress the generation of Bird's Beak and improve surface flatness.

일반적으로 반도체 소자의 제조 공정에서 소자와 소자 또는 주변 지역과 메모리 셀 지역을 전기적으로 분리시키기 위하여 소자분리 영역에 소자분리막을 형성한다. 이러한 소자분리막은 LOCOS(Local Oxidation of Silicon) 공정 또는 트렌치(Trench)를 이용한 방법 등과 같이 여러 가지의 방법에 의해 형성될 수 있는데, 그러면 LOCOS 공정을 이용한 종래 반도체 소자의 소자분리막 형성 방법을 도 1A 및 도 1B를 통해 설명하면 다음과 같다.In general, in the fabrication process of a semiconductor device, an isolation layer is formed in an isolation region to electrically isolate an element and a device, or a peripheral region and a memory cell region. The device isolation film may be formed by various methods such as a local oxide of silicon (LOCOS) process or a trench (Trench) method, and then the method of forming a device isolation film of a conventional semiconductor device using the LOCOS process is shown in Figure 1A and Referring to Figure 1B as follows.

종래에는 도 1A에 도시된 바와 같이 실리콘 기판(1)상에 패드 산화막(2) 및 질화막(3)을 순차적으로 형성한 후 소자 분리 영역의 상기 실리콘 기판(1)이 노출되도록 상기 질화막(3) 및 패드 산화막(2)을 순차적으로 패터닝한다. 그리고 패터닝된 상기 질화막(3)을 산화 방지층으로 이용한 산화 공정으로 노출된 부분의 상기 실리콘 기판(1)을 산화시켜 도 1B에 도시된 바와 같이 소자분리막(4)을 형성한다. 그런데 상기 LOCOS 공정을 이용하는 경우 산화 공정시 산화제의 측면확산에 의해 상기 소자 분리막(4) 양측부에 버즈빅(A 부분)이 생성되기 때문에 활성 영역의 크기가 감소되고, 이로 인해 소자의 고집적화가 어려운 단점이 있다. 또한 상기 표면의 평탄도가 불량해져 후속 공정의 진행에 어려움이 따른다.Conventionally, as illustrated in FIG. 1A, the pad oxide film 2 and the nitride film 3 are sequentially formed on the silicon substrate 1, and the nitride film 3 is exposed so that the silicon substrate 1 in the device isolation region is exposed. And the pad oxide film 2 is sequentially patterned. Then, the silicon substrate 1 in the exposed portion is oxidized by the oxidation process using the patterned nitride film 3 as an oxidation prevention layer to form the device isolation film 4 as shown in FIG. 1B. However, when the LOCOS process is used, the size of the active region is reduced because the Buzzvik (A part) is formed at both sides of the device isolation layer 4 by side diffusion of the oxidant during the oxidation process, which makes it difficult to achieve high integration of the device. There are disadvantages. In addition, the flatness of the surface is poor, it is difficult to proceed with the subsequent process.

따라서 본 발명은 소자 분리 영역 양측부의 실리콘 기판에 미세한 크기의 트렌치를 형성하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 소자분리막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of forming a device isolation film of a semiconductor device capable of solving the above-mentioned disadvantages by forming a trench of a fine size on both sides of a device isolation region.

상기한 목적을 달성하기 위한 본 발명은 실리콘 기판 상에 패드산화막, 질화막 및 감광막을 순차적으로 형성한 후 소자분리 영역의 상기 질화막이 노출되도록 상기 감광막을 패터닝하는 제1단계와, 상기 제1단계로부터 노출된 부분의 상기 질화막 및 패드 산화막이 순차적으로 제거되는 동시에 상기 소자분리 영역 양측부의 상기 실리콘 기판에 트렌치가 형성되도록 식각 공정을 실시하는 제2단계와, 상기 제2단계로부터 상기 감광막을 제거하고 상기 질화막의 패터닝된 측벽에 질화막 스페이서를 형성한 후 산화 공정을 실시하여 상기 소자 분리 영역에 소자분리막을 형성하는 제3단계와, 상기 제3단계로부터 잔류된 상기 질화막, 질화막 스페이서 및 패드 산화막을 제거하는 제4단계로 이루어지는 것을 특징으로 하며, 상기 감광막은 측벽이 70 내지 85° 경사지게 패터닝되고, 상기 제2단계의 식각 공정후 격자 결함을 제거하기 위한 산화 및 열처리 공정을 순차적으로 실시하는 단계를 더 포함하는 것을 특징으로 한다.The present invention for achieving the above object is a first step of sequentially forming a pad oxide film, a nitride film and a photoresist film on a silicon substrate and patterning the photoresist film so that the nitride film of the device isolation region is exposed, and from the first step A second step of performing an etching process such that the exposed portions of the nitride film and the pad oxide film are sequentially removed and a trench is formed in the silicon substrate on both sides of the device isolation region, and the photoresist film is removed from the second step. Forming a nitride spacer on the patterned sidewall of the nitride film and performing an oxidation process to form an isolation layer in the device isolation region; and removing the nitride film, the nitride spacer, and the pad oxide film remaining from the third step. It characterized in that the fourth step, the photosensitive film has a side wall of 70 to 85 ° And patterned it is used, characterized by further comprising the step of conducting oxidation and heat treatment processes for the removal of lattice defects after the etch process of the second step in order.

도 1A 및 도 1B는 종래 반도체 소자의 소자분리막 형성 방법을 설명하기 위한 소자의 단면도.1A and 1B are cross-sectional views of a device for explaining a method of forming a device isolation film of a conventional semiconductor device.

도 2A 내지 도 2F는 본 발명에 따른 반도체 소자의 소자분리막 형성 방법을 설명하기 위한 소자의 단면도.2A to 2F are cross-sectional views of devices for explaining a device isolation film forming method of a semiconductor device according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

1 및 11:실리콘 기판2 및 12:패드산화막1 and 11: silicon substrates 2 and 12: pad oxide film

3:질화막4 및 17:소자분리막3: nitride film 4 and 17: device isolation film

13:제1질화막14:감광막13: First nitride film 14: Photosensitive film

15:트렌치16:제2질화막15: trench 16: second nitride film

16A:제2질화막 스페이서16A: Second nitride film spacer

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2A 내지 도 2F는 본 발명에 따른 반도체 소자의 소자분리막 형성 방법을 설명하기 위한 소자의 단면도로서, 도 2A는 실리콘 기판(11)상에 패드산화막(12), 제1질화막(13) 및 감광막(14)을 순차적으로 형성한 후 소자 분리 영역의 상기 제1질화막(13)이 노출되도록 상기 감광막(14)을 패터닝한 상태의 단면도로서, 이때 상기 감광막(14)의 패터닝된 측벽이 70 내지 85°정도의 경사각을 갖도록 노광 공정시 노광 에너지를 조절한다. 여기서 상기 패드 산화막(12)은 50 내지 300Å의 두께로 형성하며 상기 질화막(13)은 500 내지 3000Å의 두께로 형성한다.2A to 2F are cross-sectional views of a device for explaining a method of forming a device isolation film of a semiconductor device according to the present invention, and FIG. 2A is a pad oxide film 12, a first nitride film 13, and a photoresist film on a silicon substrate 11. A cross-sectional view of the photoresist layer 14 being patterned such that the first nitride layer 13 of the device isolation region is exposed after sequentially forming (14), wherein the patterned sidewalls of the photoresist layer 14 are 70-85. The exposure energy is adjusted during the exposure process to have an inclination angle of about degrees. Here, the pad oxide film 12 is formed to a thickness of 50 to 300 kPa and the nitride film 13 is formed to a thickness of 500 to 3000 kPa.

도 2B는 패터닝된 상기 감광막(14)을 마스크로 이용한 건식 식각 공정으로 상기 제1질화막(13) 및 패드 산화막(12)을 순차적으로 식각한 후 상기 감광막(14)을 제거한 상태의 단면도로서, 이때 낮은 기압과 높은 전계 조건에서 상기 건식 식각 공정을 진행하면 식각 이온이 상기 감광막(14)의 패터닝된 측벽을 따라 이동하기 때문에 상기 소자 분리 영역 양측부의 상기 실리콘 기판(11)에 미세한 크기의 트렌치(15)가 형성된다. 또한 상기 건식 식각시 이후 형성될 소자분리막의 돌출이 최소화되도록 상기 소자분리 영역의 상기 실리콘 기판(11)을 소정 깊이 식각할 수 있다.FIG. 2B is a cross-sectional view of the first nitride layer 13 and the pad oxide layer 12 being sequentially etched and subsequently removing the photosensitive layer 14 by a dry etching process using the patterned photosensitive layer 14 as a mask. When the dry etching process is performed at a low atmospheric pressure and a high electric field condition, since the etch ions move along the patterned sidewall of the photosensitive film 14, the trench 15 having a minute size in the silicon substrate 11 at both sides of the device isolation region is formed. ) Is formed. In addition, the silicon substrate 11 of the device isolation region may be etched to a predetermined depth so that the protrusion of the device isolation layer to be formed after the dry etching is minimized.

도 2C는 상기 건식 식각 공정시 발생된 격자 결함을 제거시키며 상기 제1질화막(13)이 산화 방지막(Barrier Film) 역할을 할 수 있도록 900 내지 1100℃의 온도에서 1차 산화 공정을 실시한 후 열처리를 실시하고 전체 상부면에 제2질화막(16)을 300 내지 1000Å의 두께로 형성한 상태의 단면도로서, 상기 1차 산화 공정시 상기 트렌치(15)하부에도 산화막이 성장된다.FIG. 2C is a heat treatment after performing a first oxidation process at a temperature of 900 to 1100 ° C. to remove lattice defects generated during the dry etching process and to act as a barrier film of the first nitride layer 13. A cross-sectional view of the second nitride film 16 having a thickness of 300 to 1000 GPa on the entire upper surface thereof, wherein an oxide film is grown under the trench 15 during the first oxidation process.

도 2D는 상기 제2질화막(16)을 블렌켓 식각(Blanket Etch)하여 상기 제1질화막(13)의 패터닝된 측벽에 제2질화막 스페이서(16A)를 형성한 상태의 단면도이다.FIG. 2D is a cross-sectional view of a second nitride film spacer 16A formed by blanket etching the second nitride film 16 to form a patterned sidewall of the first nitride film 13.

도 2E는 800 내지 1100℃의 온도에서 습식 산화 공정을 실시함으로써 상기 소자분리 영역에 소자분리막(17)이 형성된 상태의 단면도로서, 상기 트렌치(15)에 의해 상기 소자분리막(17) 양측부에 버즈빅이 생성되지 않았다.FIG. 2E is a cross-sectional view of the device isolation film 17 formed in the device isolation region by performing a wet oxidation process at a temperature of 800 to 1100 ° C., wherein the trench 15 buzzes both sides of the device isolation film 17. Big was not created.

도 2F는 잔류된 상기 제1질화막(13), 제2질화막 스페이서(16A) 및 패드 산화막(12)을 제거한 상태의 단면도이다.FIG. 2F is a cross-sectional view of the first nitride film 13, the second nitride film spacer 16A, and the pad oxide film 12 removed.

상술한 바와 같이 본 발명에 의하면 소자 분리 영역 양측부의 실리콘 기판에 미세한 크기의 트렌치를 형성하고 질화막의 패터닝된 측벽에 질화막 스페이서를 형성하므로써 버즈빅의 생성이 완전히 억제되어 충분한 활성영역의 확보가 가능하다. 또한 질화막을 패터닝하는 과정에서 소자 분리 영역의 실리콘 기판이 소정 깊이 식각되도록 함으로써 실리콘 기판 상부로 돌출되는 부분이 감소되어 표면의 평탄도가 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, by forming a trench having a small size in the silicon substrate on both sides of the device isolation region and forming a nitride spacer on the patterned sidewall of the nitride layer, the generation of the buzz be completely suppressed, thereby ensuring a sufficient active region. . In addition, in the process of patterning the nitride film, the silicon substrate of the device isolation region is etched to a predetermined depth, thereby reducing the portion protruding to the upper portion of the silicon substrate, thereby improving surface flatness.

Claims (8)

반도체 소자의 소자분리막 형성 방법에 있어서,In the device isolation film forming method of a semiconductor device, 실리콘 기판상에 패드 산화막, 질화막 및 감광막을 순차적으로 형성한 후 소자 분리 영역의 상기 질화막이 노출되도록 상기 감광막을 패터닝하는 제1단계와,A first step of sequentially forming a pad oxide film, a nitride film, and a photosensitive film on a silicon substrate, and then patterning the photosensitive film to expose the nitride film in an isolation region; 상기 제1단계로부터 노출된 부분의 상기 질화막 및 패드 산화막이 순차적으로 제거되는 동시에 상기 소자분리 영역 양측부의 상기 실리콘 기판에 트렌치가 형성되도록 식각 공정을 실시하는 제2단계와,A second step of performing an etching process so that the nitride film and the pad oxide film of the portion exposed from the first step are sequentially removed and a trench is formed in the silicon substrate on both sides of the device isolation region; 상기 제2단계로부터 상기 감광막을 제거하고 상기 질화막의 패터닝된 측벽에 질화막 스페이서를 형성한 후 산화 공정을 실시하여 상기 소자 분리 영역에 소자분리막을 형성하는 제3단계와,Removing the photoresist film from the second step, forming a nitride spacer on the patterned sidewall of the nitride film, and performing an oxidation process to form an isolation layer in the device isolation region; 상기 제3단계로부터 잔류된 상기 질화막, 질화막 스페이서 및 패드 산화막을 제거하는 제4단계로 이루어지는 것을 특징으로 하는 반도체 소자의 소자분리막 형성 방법.And a fourth step of removing the nitride film, the nitride film spacer, and the pad oxide film remaining from the third step. 제1항에 있어서,The method of claim 1, 상기 패드 산화막은 50 내지 300Å의 두께로 형성되며 상기 질화막은 500 내지 3000Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성 방법.Wherein the pad oxide film is formed to a thickness of 50 to 300 Å and the nitride film is formed to a thickness of 500 to 3,000 Å. 제1항에 있어서,The method of claim 1, 상기 감광막은 측벽이 70 내지 85° 경사지게 패터닝되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성 방법.The photosensitive film is a method of forming a device isolation film of a semiconductor device, characterized in that the sidewall is patterned inclined 70 to 85 °. 제1항에 있어서,The method of claim 1, 상기 제2단계의 식각 공정은 건식으로 실시되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성 방법.The etching process of the second step is a method of forming a device isolation film of a semiconductor device, characterized in that carried out dry. 제1항에 있어서,The method of claim 1, 상기 제3단계의 산화 공정은 습식으로 실시되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성 방법.The method of forming a device isolation film of a semiconductor device according to claim 3, wherein the oxidation process of the third step is performed in a wet manner. 제1 또는 제5항에 있어서,The method according to claim 1 or 5, 상기 산화 공정은 8000 내지 1100℃의 온도에서 실시되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성 방법.The oxidation process is a device isolation film forming method of the semiconductor device, characterized in that carried out at a temperature of 8000 to 1100 ℃. 제1항에 있어서,The method of claim 1, 상기 제2단계의 식각 공정후 격자 결함을 제거하기 위한 산화 및 열처리 공정을 순차적으로 실시하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 소자분리막 형성 방법.And sequentially performing an oxidation and heat treatment process for removing lattice defects after the etching process of the second step. 제7항에 있어서,The method of claim 7, wherein 상기 산화 공정은 900 내지 1100℃의 온도에서 실시되는 것을 특징으로 하는 반도체 소자의 소자분리막 형성 방법.The oxidation process is a device isolation film forming method of a semiconductor device, characterized in that carried out at a temperature of 900 to 1100 ℃.
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