KR19980036199A - A texture cache memory using tile map - Google Patents

Abstract

The present invention relates to a texture cache memory of a graphics controller capable of high-speed texture mapping using a tile map in texture mapping, A plurality of tags 65 each representing information on the texture addresses U and V of the plurality of cache blocks 62 and a plurality of tags 65 indicating texture addresses U and V ) To a plurality of And a tile map address converting unit (50) for converting the physical address into a physical address of a local memory (20) of a graphics controller to which an address is assigned in the form of a square tile map and providing the same to the memory controller (40) The texture image data of the local memory 20 is stored in the form of a tile map so that data can be loaded into the texture cache without a page miss.

Description

A texture cache memory using a tile map (A TEXTURE CACHE MEMORY USING TILE MAP)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a texture cache memory of a graphics controller. More specifically, the present invention relates to a texture cache memory capable of high-speed texture mapping using a tile map in texture mapping, .

Currently, graphics controllers are capable of very fast graphics processing, with two-dimensional and three-dimensional graphics processing and a graphic acceleration function. Texture mapping, which is one of the most important functions of a graphic controller with 3D graphics acceleration, requires more memory performance than other functions. This is because texture mapping, which functions to apply an image to a three-dimensional object, must read the image to be loaded from memory each time. Moreover, this is more likely because the data to be read is not stored sequentially in the memory.

Generally, in the case of a memory configured with a DRAM (Dynamic Random Access Memory), the probability of occurrence of a page miss increases due to its characteristics. Also, in the case of a synchronous DRAM, it is difficult to utilize a burst operation function for transferring data at high speed in block units. In this case, a cache memory is provided in the graphics controller for the purpose of improving performance.

1 is a view for explaining an example of using a conventional texture cache memory.

Referring to FIG. 1, when texture mapping is performed, corresponding data in a main memory 10 in which graphic data is stored is loaded into a local memory 20 of the graphics controller. The graphics controller pre-loads the data into the texture cache memory 30 and uses the data. The amount of data to be read at a time in the local memory 20 is referred to as a line size or a block size in the context of the texture cache memory 30 and can be read once in the local memory 20, You can read it once.

A recent graphics controller employs a 64-bit data bus. In 64 bits, there are four 16-bit data and eight 8-bit data. This is a small number considering the efficiency of texture mapping and cache efficiency. Therefore, this type of 64-bit access must be done 4 or more times. In order to increase the performance of the DRAM, the consecutive access operation must be the page that is currently accessed. However, when a page miss occurs, the RAS signal (Row Address Strobe signal) must be re-applied to the DRAM, so that the access speed becomes slower.

However, texture mapping does not read only consecutive data. If the texture image is stored in sequential space and the data is read in the horizontal direction when texture mapping is performed, a large amount of data already loaded in the cache can be utilized as it is, which can greatly improve performance. However, if you try to use the data in the vertical direction, you will not be able to read it, no matter how much data it reads. Therefore, in texture mapping, it is desirable to store each part of the texture image in the form of a square in one block of the cache.

The problem with this case, however, is that the first and second rows of data are likely to be on different DRAM pages. This results in slower DRAM access speeds and lower performance. To solve this problem, a tile map can be formed by changing the address area of the DRAM. However, if the entire local memory is constituted by a tile map, the performance of the graphics controller due to the 3D texture mapping may increase, but the performance of the graphics controller may deteriorate in the case of screen refresh or the like in which sequential access is performed Problems may arise.

It is an object of the present invention to provide a texture cache memory capable of performing high-speed texture mapping using a tile map structure only in texture mapping.

FIG. 1 is a view for explaining an example of using a conventional texture cache memory,

FIG. 2 is a view showing a texture cache memory and a peripheral circuit using a tile map according to an embodiment of the present invention;

FIG. 3 is a view showing the internal structure of the texture cache memory shown in FIG. 2;

4 is a view for explaining a texture address,

5A and 5B are diagrams for explaining a memory configuration method of an address storage method using a tile map and an address storage method using no tile map.

Description of the Related Art [0002]

10: main memory 20: local memory

30, 60: texture cache memory 40: memory controller

50: tile map address conversion unit 62: cache block

65: Tag

(Configuration)

According to an aspect of the present invention for achieving the above object, a texture cache memory of a graphics controller includes: A square cache block; A plurality of tags indicating respective pieces of information on texture addresses of the plurality of cache blocks; Wherein when the texture is mapped, And a tile map address converting unit for converting the physical address into a physical address of a local memory of the graphics controller to which the address is assigned in the form of a square tile map and providing the physical address to the memory controller.

In this embodiment, the cache block has m bits of data First to fourth cache blocks; The plurality of tags include first to fourth tags in which information on each texture address corresponding to the first to fourth texture cache blocks is stored.

In this embodiment, each of the first through fourth cache blocks has 16-bit data .

(Action)

According to the present invention, when performing texture mapping, texture image data of a local memory is stored in the form of a tile map, and data can be loaded into a texture cache without a page miss.

(Example)

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a view showing a texture cache memory and a peripheral circuit using a tile map according to an embodiment of the present invention, and FIG. 3 is a view showing the internal structure of the texture cache memory shown in FIG.

Referring to FIG. 2, a texture cache memory 60 and a tile map address converting unit 50 are provided in the graphics controller. In the embodiment of the present invention, a texture cache having a relatively small size is used in consideration of the area of the graphics controller.

Referring to FIG. 3, since each block 62 of the cache is made up of 4 × 4 pieces of 16-bit data, the size of the block 62 is 32 bytes, and a four- set associative method, the size of the entire cache is 128 bytes since four blocks (62a to 62d) are required. Each block has a tag 65 consisting of U and V addresses which are texture addresses. The tag 65 is used to compare whether the address of data to be read ahead is stored in the cache or not.

If the bus size of the local memory 20 configured as DRAM is 64 bits (8 bytes), DRAM access is required 4 times to fill one block. And here, all 4 DRAM accesses should not cause page misses. Therefore, the texture image should be divided into 4 × 4 blocks from the beginning and stored in the DRAM in the form of a tile map. One block of the texture image stored in the DRAM in the form of a tile map is allocated to the contiguous address in the DRAM. Therefore, when a cache miss occurs and the corresponding data is fetched from the local memory 20 to the texture cache memory 30, one block can be fetched from the contiguous space, thereby improving the speed.

More specifically, if the data has already been placed in the cache, one of the four tags 65a to 65d and the current U and V addresses match. In this case, you can retrieve the data from the hit block and send the data to the internal rendering engine that requested the data. However, if the same U and V addresses in four tags are not found, the cache does not have the desired data, so the data must be read from the DRAM. At this time, the U and V addresses are converted into the physical address of the DRAM through the tile map conversion unit 50 and provided to the memory controller 40.

At this time, since the data storage format of the local memory 20 is composed of the tile map, the 4x4 data to be filled in the block exists in the same page of the DRAM. So you can read all the data in a fairly quick time. In particular, when the local memory 20 is configured as a synchronous DRAM capable of performing a burst operation, a burst read operation can be performed to perform the burst operation more quickly.

FIG. 4 is a diagram for explaining a texture address. FIGS. 5A and 5B are diagrams for explaining a memory configuration method of an address storage method using a tile map and an address storage method using no tile map.

Figure 4 and Figure 5A, with reference to 5B, U, the data on the texture image 100 having a V address a case in represented as a _UV, the first four data _{a 0, a 1, a 2} , a 3 are tiled In the case of not a map 110 and the case of a tile map 120, both are stored as consecutive addresses. However, if the next a ₀₄ data is not a tile map, it will come immediately after a ₃ , but in the case of a tile map, it will not be shown in the figure but will be stored after a ₃₃ . On the other hand, if the a ₁₀ data is not a tile map, it will be stored after all the first columns are stored, and if it is a tile map, it will be immediately after a ₃ . That is, in the case of the tile map 120, each data string a, b, c, ... is sequentially stored.

As described above, when the graphics controller performs texture mapping, the structure of the local memory 20 stores data in the form of a tile map. When data is loaded from the local memory 20 to the texture cache 60, the corresponding texture image is loaded into each cache block 62 of the texture cache 60, so that high-speed texture mapping can be performed.

According to the present invention, since the structure of the local memory has a general memory structure in the operation such as the screen refresh which has a lot of sequential accesses and the structure of the tile map is used in the texture mapping, High-speed texture mapping can be performed.

Claims (3)

A texture cache memory of a graphics controller comprising: Plural A square cache block 62; A plurality of tags (65) indicating respective information on the texture addresses (U, V) of the plurality of cache blocks (62); When texture mapping, the texture addresses (U, V) And a tile map address converting unit (50) for converting the physical address into a physical address of the local memory (20) of the graphics controller to which the address is assigned in the form of a square tile map and providing the physical address to the memory controller (40) Texture cache memory. The method according to claim 1, The cache block 65 stores the m- First to fourth cache blocks 62a to 62d; The plurality of tags 65 includes first to fourth tags 65a to 65d for storing information on texture addresses U and V corresponding to the first to fourth texture cache blocks 62a to 62d, The texture cache memory of claim 1, 3. The method of claim 2, Each of the first to fourth cache blocks 62a to 62d has 16-bit data And a texture cache memory for storing the texture cache memory.