KR19980034653A - High voltage semiconductor device and manufacturing method - Google Patents
High voltage semiconductor device and manufacturing method Download PDFInfo
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- KR19980034653A KR19980034653A KR1019960052787A KR19960052787A KR19980034653A KR 19980034653 A KR19980034653 A KR 19980034653A KR 1019960052787 A KR1019960052787 A KR 1019960052787A KR 19960052787 A KR19960052787 A KR 19960052787A KR 19980034653 A KR19980034653 A KR 19980034653A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 239000000758 substrate Substances 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 항복전압의 값을 높이고, 그 소자의 크기를 최소화한 고전압 반도체소자 및 그 제조방법에 관한 것이며, 종래의 고전압 반도체소자는 항복전압의 증가를 위해 채널의 길이를 길게함으로써, 소자의 크기가 증대되는 문제점이 있었다. 이와같은 문제점을 감안한 본 발명에 의한 고전압 반도체소자는 고농도 소스/드레인과 게이트 사이에 형성되는 저농도 소스/드레인의 구조를 트랜치구조로 형성하여 그 저농도 소스/드레인이 인가되는 고전압에 대해 저항역할을 하게하여 소자가 파괴되는 것을 방지하고, 소자의 크기를 최소화하여 집적화에 용이한 효과가 있다.The present invention relates to a high-voltage semiconductor device and a method of manufacturing the same, increasing the value of the breakdown voltage and minimizing the size of the device, and the conventional high-voltage semiconductor device by increasing the length of the channel to increase the breakdown voltage, the size of the device There was a problem that is increased. In consideration of such a problem, the high voltage semiconductor device according to the present invention forms a structure of a low concentration source / drain formed between a high concentration source / drain and a gate as a trench structure to serve as a resistance to a high voltage to which the low concentration source / drain is applied. This prevents the device from being destroyed and minimizes the size of the device, thereby facilitating integration.
Description
본 발명은 고전압 반도체소자 및 그 제조방법에 관한 것으로, 특히 저농도 소스/드레인을 트랜치구조로 형성함으로써 소자의 크기를 최소화한 고전압 반도체소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage semiconductor device and a method of manufacturing the same, and more particularly, to a high voltage semiconductor device and a method of manufacturing the same, which minimize the size of a device by forming a low concentration source / drain in a trench structure.
종래 고전압 피모스의 제조공정 수순에 따른 단면도를 도시한 도 1에 의거하여 종래의 반도체소자 및 그 제조방법을 상세히 설명하면 다음과 같다.A semiconductor device and a method of manufacturing the same will be described in detail with reference to FIG. 1, which shows a cross-sectional view of a conventional high voltage PMOS manufacturing process.
먼저, 도 1a에 도시한 바와 같이 기판(1)위에 산화막(2)을 증착하고, 상기 산화막(2)위에 포토레지스트(3)를 도포 및 패터닝한 후에, 고전압 피모스의 항복전압을 높이기 위해, 기판(1)에 저농도의 P형 불순물 원자를 이온주입하여 저농도의 소스(4)를 형성한다.First, as shown in FIG. 1A, an oxide film 2 is deposited on a substrate 1, a photoresist 3 is applied and patterned on the oxide film 2, and then, in order to increase the breakdown voltage of the high voltage PMOS, A low concentration source 4 is formed by ion implantation of a low concentration of P-type impurity atoms into the substrate 1.
그 다음, 도 1b에 도시한 바와 같이 상기 포토레지스트(3) 및 산화막(2)을 제거하고, 다시 그 하부에 저농도의 P형 불순물 원자가 도핑된 기판(1)위에 산화막(5)을 증착하고, 상기 증착된 산화막(5)위에 포토레지스트(5)를 도포 및 패터닝한 후에, 고농도의 P형 불순물원자를 이온주입하여 고농도 소스/드레인(7)을 형성한다.Next, as shown in FIG. 1B, the photoresist 3 and the oxide film 2 are removed, and an oxide film 5 is deposited on the substrate 1 doped with a low concentration of P-type impurity atoms at the bottom thereof. After coating and patterning the photoresist 5 on the deposited oxide film 5, a high concentration source / drain 7 is formed by ion implantation of a high concentration of P-type impurity atoms.
그 다음, 도 1c에 도시한 바와 같이 상기 포토레지스트(6) 및 산화막(5)을 제거한 후, 로코스(LOCOS)공정을 통해 고농도 소스(7)의 일부 및 저농도 소스(4)의 상부에 필드산화막(8a)을 형성하여 저농도 소스(4)의 길이를 증가시켜 고전압 인가시에 저항역할을 하게 한다.Next, after removing the photoresist 6 and the oxide film 5, as shown in FIG. 1C, a part of the high concentration source 7 and the upper portion of the low concentration source 4 are processed through a LOCOS process. The oxide film 8a is formed to increase the length of the low concentration source 4 to serve as a resistance when high voltage is applied.
그 다음, 도 1d에 도시한 바와 같이 상기한 제조공정으로 저농도 소스(4)와 고농도 소스/드레인(7)과, 필드산화막(8a)이 형성된 기판(1)위에 게이트 산화막(8)을 증착하고, 상기 증착된 산화막(8)위에 다결정실리콘(9)을 증착한 다음, 상기 다결정실리콘(9) 위에 포토레지스트(10)를 도포 및 패터닝하여 게이트(11)를 형성한다.Then, as shown in FIG. 1D, the gate oxide film 8 is deposited on the substrate 1 on which the low concentration source 4, the high concentration source / drain 7, and the field oxide film 8a are formed. After depositing the polysilicon 9 on the deposited oxide film 8, the photoresist 10 is coated and patterned on the polysilicon 9 to form the gate 11.
그 다음, 도 1e에 도시한 바와 같이 상기 포토레지스트(10)를 제거한 후, 저농도 소스(4)와 고농도 소스/드레인(7)과, 필드산화막(8a) 및 게이트(11)가 형성된 기판(1)위에 소자의 보호를 위한 산화막(12)을 증착한다.Subsequently, as shown in FIG. 1E, after removing the photoresist 10, the substrate 1 having the low concentration source 4, the high concentration source / drain 7, the field oxide film 8a and the gate 11 formed thereon. An oxide film 12 is deposited to protect the device.
그 다음, 도 1f에 도시한 바와 같이 고농도 소스/고농도 드레인(7)의 상부에 증착된 산화막(12)을 식각한후, 알루미늄을 증착하여 소스/드레인전극(13)을 형성함으로써, 고전압 피모스의 제조를 완료하게 된다.Next, as shown in FIG. 1F, the oxide film 12 deposited on the high concentration source / high concentration drain 7 is etched, and then aluminum is deposited to form the source / drain electrode 13 to form a high voltage PMOS. The manufacture of is completed.
상기와 같은 제조공정순서에 따라 제조된 종래의 고전압 피모스는 도 1f에 도시한 바와 같이 기판(1)과; 항복전압을 높이기 위해 상기 기판(1)에 형성된 저농도 소스(4)와; 상기 기판(1)에 형성된 고농도 소스/드레인(7)과; 저농도 소스(4)의 저항을 증가시키기 위해 저농도 소스(4)의 상부에 형성된 필드산화막(8a)과, 상기 필드산화막(8a)의 일부와 게이트 산화막(8)의 상부에 다결정실리콘(9)을 증착하여 형성한 게이트(11)와; 소자의 보호를 위해 상기 고농도 소스/드레인(7), 저농도 소스(4)가 형성된 기판(1)과 상기 기판(1)위에 형성된 게이트(11)의 상부전면에 증착한 산화막(12)과; 상기 고농도 소스/고농도 드레인(7)에 접속되어 그 고농도 소스/드레인(7)에 전원전압을 인가하는 소스/드레인전극(13)으로 구성된다. 이와같이 구성된 종래의 고전압 피모스는 그 저농도 소스(4)가 저항역할을 하고, 일반적인 피모스에 비하여 채널의 길이를 길게함으로써, 인가되는 고전압에 소자가 파괴되지 않도록 큰 항복전압을 갖는 장점이 있다.The conventional high voltage PMOS manufactured according to the above manufacturing process sequence includes a substrate 1 as shown in FIG. 1F; A low concentration source (4) formed in the substrate (1) to increase the breakdown voltage; A highly concentrated source / drain (7) formed in the substrate (1); In order to increase the resistance of the low concentration source 4, a polycrystalline silicon 9 is formed on the field oxide film 8a formed on the low concentration source 4, a part of the field oxide film 8a and on the gate oxide film 8. A gate 11 formed by evaporation; An oxide film 12 deposited on the upper surface of the substrate 1 on which the high concentration source / drain 7 and the low concentration source 4 are formed and the gate 11 formed on the substrate 1 for protecting the device; And a source / drain electrode 13 connected to the high concentration source / high concentration drain 7 and applying a power supply voltage to the high concentration source / drain 7. The conventional high voltage PMOS configured as described above has an advantage of having a large breakdown voltage so that the low concentration source 4 acts as a resistance and lengthens the channel length as compared with the general PMOS, so that the device is not destroyed at the applied high voltage.
그러나, 상기한 종래의 고전압 피모스는 항복전압의 증가를 위해 채널의 길이를 길게하고, 저농도 소스를 형성함으로써, 소자의 크기가 증대되는 문제점이 있었다.However, the conventional high voltage PMOS has a problem in that the size of the device is increased by lengthening the channel length and forming a low concentration source for increasing the breakdown voltage.
상기와 같은 문제점을 감안한 본 발명은 큰 항복전압을 갖으며, 그 크기를 최소화한 고전압 반도체소자를 제공함에 그 목적이 있다.In view of the above problems, the present invention has a large breakdown voltage, and an object thereof is to provide a high voltage semiconductor device with a minimum size.
도 1은 종래의 고전압 피모스를 제조공정 수순에 따라 도시한 단면도.1 is a cross-sectional view showing a conventional high voltage PMOS according to a manufacturing process procedure.
도 2는 본 발명에 의한 고전압 피모스를 제조공정 수순에 따라 도시한 단면도.2 is a cross-sectional view showing the high voltage PMOS according to the present invention according to the manufacturing process procedure.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1:기판 2,5,8,8a,12:산화막1: substrate 2,5,8,8a, 12: oxide film
3,6,10:포토레지스트 4:저농도 소스/드레인3,6,10: Photoresist 4: Low Concentration Source / Drain
7:고농도 소스/드레인 9:다결정실리콘7: High concentration source / drain 9: Polycrystalline silicon
11:게이트 13:소스/드레인전극11: gate 13: source / drain electrodes
상기와 같은 목적은 저농도 소스/드레인를 트랜치구조로 형성함으로써 달성되는 것으로, 기판위에 두개의 트랜치구조를 형성하는 단계와; 상기 형성된 트랜치구조에 저농도의 불순물 이온을 주입하여 저농도의 소스/드레인을 형성하는 단계와; 상기 형성된 좌측 트랜치구조의 좌측과 우측 트랜치구조의 우측 기판에 고농도의 소스/드레인을 형성하는 단계와; 상기 두 트랜치구조 사이에 게이트를 형성하는 단계와; 소자의 보호를 위해 소스/드레인전극을 제외한 소자의 표면 전반에 산화막을 형성하는 단계와; 상기 고농도 소스/드레인에 전압을 인가하기 위해 소스/드레인전극을 형성하는 단계로 구성됨을 특징으로 하는 본 발명에 의한 고전압 반도체소자 제조방법을 도 2에 도시한 고전압 피모스의 제조공정 수순에 따른 단면도를 참조하여 상세히 설명하면 다음과 같다.The above object is achieved by forming a low concentration source / drain into a trench structure, comprising: forming two trench structures on a substrate; Implanting a low concentration of impurity ions into the formed trench structure to form a low concentration of source / drain; Forming a high concentration source / drain on the left and right substrates of the formed left trench structure; Forming a gate between the two trench structures; Forming an oxide film over the surface of the device except for the source / drain electrodes to protect the device; A cross-sectional view of a method of manufacturing a high voltage semiconductor device according to the present invention, characterized in that it comprises a step of forming a source / drain electrode for applying a voltage to the high concentration source / drain. When described in detail with reference to as follows.
먼저, 도 2a에 도시한 바와 같이 기판(1)위에 산화막(2)을 증착한 후, 상기 산화막(2)위에 포토레지스트(3)를 도포 및 패터닝하여 게이트가 형성될 영역과 소스/드레인이 형성될 영역사이의 기판(1)을 식각하여 트랜치구조를 형성한다.First, as shown in FIG. 2A, an oxide film 2 is deposited on the substrate 1, and then a photoresist 3 is applied and patterned on the oxide film 2 to form a region and a source / drain where a gate is to be formed. The substrate 1 between the regions to be etched is etched to form a trench structure.
그 다음, 도 2b에 도시한 바와 같이 상기 포토레지스트(3)를 제거한 후, 저농도의 P형불순물 원자를 이온주입하여, 상기 형성된 트랜치구조 전반에 저농도의 소스/드레인(4)을 형성한다.Then, as shown in FIG. 2B, the photoresist 3 is removed, followed by ion implantation of low concentration P-type impurity atoms to form a low concentration source / drain 4 throughout the formed trench structure.
그 다음, 도 2c에 도시한 바와 같이 상기 산화막(2)을 제거한 후에, 다시 저농도의 P형 불순물 원자로 도핑된 트랜치구조를 포함하는 기판(1)에 산화막(5)을 증착하고, 상기 산화막(5) 위에 포토레지스트(6)를 도포 및 패터닝한 후에, 고농도의 P형불순물 원자를 이온주입하여 좌측 트랜치구조의 좌측과 우측 트랜치구조의 우측에 고농도의 소스/드레인(7)을 형성한다.Then, after removing the oxide film 2 as shown in FIG. 2C, an oxide film 5 is deposited on the substrate 1 including the trench structure doped with a low concentration of P-type impurity atoms, and the oxide film 5 After the photoresist 6 is applied and patterned on the photoresist, a high concentration of P-type impurity atoms are ion implanted to form a high concentration source / drain 7 on the left side of the left trench structure and the right side of the right trench structure.
그 다음, 도 2d에 도시한 바와 같이, 상기 산화막(5)을 제거하고 다시 게이트 산화막(8)을 트랜치구조의 저농도 소스/드레인(4)과 고농도의 소스/드레인(7)을 포함하는 기판(1)위에 증착한 후, 상기 게이트 산화막(8)위에 다결정실리콘(9)을 증착하고, 상기 다결정실리콘(9)위에 포토레지스트(10)를 도포 및 패터닝하여 두 트랜치구조의 사이에 게이트(11)를 형성한다.Then, as shown in FIG. 2D, the oxide film 5 is removed and the gate oxide film 8 is again formed of a substrate including a trench source low concentration source / drain 4 and high concentration source / drain 7 ( 1) After deposition on the gate oxide film 8, polycrystalline silicon 9 is deposited, and the photoresist 10 is applied and patterned on the polysilicon 9 to form a gate 11 between the two trench structures. To form.
그 다음, 도 2e에 도시한 바와 같이, 상기 트랜치구조의 저농도 소스/드레인(4)과 고농도 소스/드레인(7)을 포함하는 기판(1)과, 상기 기판위에 형성된 게이트(11)의 위에 소자의 보호를 위한 산화막(12)을 증착한다.Next, as shown in FIG. 2E, a substrate 1 including a low concentration source / drain 4 and a high concentration source / drain 7 of the trench structure, and an element on the gate 11 formed on the substrate. An oxide film 12 is deposited for protection.
그 다음, 도 2f에 도시한 바와 같이 상기 증착으로 형성된 산화막(12)위에 포토레지스트(도면생략)를 도포 및 패터닝함으로써, 고농도 소스/드레인(7)을 노출시킨다. 이어서, 알루미늄을 증착하여 소스/드레인전극(13)을 형성함으로써, 고전압 피모스의 제조공정을 완료하게 된다.Then, as shown in FIG. 2F, the high concentration source / drain 7 is exposed by applying and patterning a photoresist (not shown) on the oxide film 12 formed by the deposition. Subsequently, aluminum is deposited to form the source / drain electrodes 13, thereby completing the manufacturing process of the high voltage PMOS.
상기와 같은 제조공정단계에 따라 제조된 고전압 피모스는 도 2f에 도시한 바와 같이 기판(1)에 형성된 트랜치구조의 저농도 소스/드레인(4)과, 상기 트랜치구조의 저농도 소스/드레인(4)이 형성된 왼쪽/오른쪽에 각각 형성된 고농도 소스/드레인(7)과; 다결정실리콘(9) 및 산화막(8)을 포함하여 상기 트랜치구조의 저농도 소스와 드레인(4) 사이의 기판(1)위에 형성된 게이트(11)와;상기 고농도 소스/드레인(7)에 전압을 인가하기 위해 일측이 그 고농도 소스/드레인(7)에 접속되고 다른 일측이 소자의 외부로 노출되도록 형성한 소스/드레인전극(13)과; 소자의 보호를 위해 소스/드레인전극(13)을 제외한 소자의 상부전면에 형성한 산화막(12)으로 구성된다.The high voltage PMOS fabricated according to the above manufacturing process steps includes a low concentration source / drain 4 of a trench structure formed in the substrate 1 and a low concentration source / drain 4 of the trench structure as shown in FIG. 2F. A high concentration source / drain 7 formed on each of the left and right sides thereof; A gate 11 formed on the substrate 1 between the low concentration source and the drain 4 of the trench structure, including the polysilicon 9 and the oxide film 8; and applying a voltage to the high concentration source / drain 7 A source / drain electrode 13 having one side connected to the high concentration source / drain 7 and the other side exposed to the outside of the device; It is composed of an oxide film 12 formed on the upper surface of the device except for the source / drain electrodes 13 to protect the device.
상기한 바와 같이 본 발명에 의한 고전압 피모스는 피엔접합(PN junction)의 농도가 낮아질수록 항복저항이 증가하는 점과 저항은 그 단면적이 일정할때 길이가 증가에 비례하는 점에 착안하여 고농도의 소스/드레인과 게이트 사이에 저농도 소스/드레인을 트랜치구조로 형성함으로써, 피모스의 항복전압을 증가시키고 그 피모스의 크기를 최소화하는 효과가 있다.As described above, in the high voltage PMOS according to the present invention, as the concentration of the PN junction decreases, the yield resistance increases and the resistance increases in proportion to the increase in length when the cross-sectional area is constant. By forming a low concentration source / drain in the trench structure between the source / drain and the gate, there is an effect of increasing the breakdown voltage of the PMOS and minimizing the size of the PMOS.
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| KR1019960052787A KR100206957B1 (en) | 1996-11-08 | 1996-11-08 | High-voltage semiconductor device and method of fabricating the same |
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| KR1019960052787A KR100206957B1 (en) | 1996-11-08 | 1996-11-08 | High-voltage semiconductor device and method of fabricating the same |
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| KR100396703B1 (en) * | 2001-04-28 | 2003-09-02 | 주식회사 하이닉스반도체 | High Voltage Device and Method for the Same |
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| KR100525615B1 (en) | 2003-09-23 | 2005-11-02 | 삼성전자주식회사 | Field Effect Transistor with high breakdown voltage and Method of forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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