KR19980034553A - Memory Arrays in Semiconductor Memory Devices - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory chip array of a semiconductor memory device. In particular, the memory chip array blocks having different capacities (number of memory chips) and sizes are mixed to reduce the overall chip size and to prevent deterioration thereof. The present invention relates to a memory array of semiconductor memory devices. SUMMARY OF THE INVENTION In accordance with an aspect of the present invention, a memory array of a semiconductor memory device including sub-memory arrays in which memory chips are repeatedly arranged at regular intervals in a row and column direction, includes at least one first memory chip array blocks, and The number of memory cells arranged to the left and right of the first memory array array blocks and arranged in the column direction has at least one second memory array array block different from the first memory array array blocks.

Description

Memory Arrays in Semiconductor Memory Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device. In particular, in determining the number of memory chips connected to a bit line of a semiconductor memory device, characteristics and areas are inseparable, and memory chip array blocks having different capacities and sizes are mixed. Therefore, the present invention relates to a memory array of a semiconductor memory device capable of minimizing degradation while reducing chip size.

In general, one method of minimizing the size of a memory cell array is to reduce the number of blocks constituting the memory cell array. By reducing the number of blocks, the chip size can be reduced by reducing the number of sense amplifiers. On the other hand, when the block is made larger, the loading and power noise on the bit line increases, and the operation current increases and the bit line sensing speed becomes slower than when the block size is small. There is a problem. FIG. 1 is a layout view showing an overall structure of a 4M memory array in 8 512K blocks according to an embodiment of the prior art. Referring to FIG. 1, eight memory chip array blocks 10 including a plurality of sub memory cell arrays 10-1 to 10-4 and a sense amplifier provided in each memory cell array blocks are provided. 7, a column decoder 5 connected to a column line, and a row decoder 3 connected to a row line. Here, the memory array array blocks 10 have a capacity of 512K and the total memory capacity is 4 mega. In addition, sense amplifier S / A 7 is shared for each memory array array block 10. Meanwhile, there is a problem in that block redendancy cannot be performed due to sharing of sense amplifiers in order to operate 1K in a 4 megabyte memory array. In addition, as described above, there is a problem in that loading and power noise applied to the bit line are increased, and the operating current increases and the bit line sensing speed is slower than when the block size is smaller than 512K. FIG. 2 is a layout view illustrating an overall structure of a 4M memory array in 16 256K blocks according to an embodiment of the prior art. Referring to FIG. 2, sixteen memory array array blocks 20 each including a plurality of sub-memory arrays 20-1 to 20-4, a sense amplifier 7 included in each memory array array block, and column lines It consists of a column decoder 5 connected and a row decoder 3 connected to the row line. Here, the memory array array blocks 20 have a capacity of 256K and the total memory capacity is 4 mega. In addition, sense amplifier S / A 7 is shared for each memory array array block 20. Compared to FIG. 1, the capacity is the same as 4 megabytes, but the operating current is reduced in half. However, there is a disadvantage in that the overall size of the memory array is larger than the structure of FIG.

An object of the present invention is to provide a memory chip array of a semiconductor memory device which can reduce chip size by mixing a small memory chip array and a large memory chip array into one chip.

Another object of the present invention is to mix a small memory chip array with a small size and a large memory chip array in a single chip to reduce chip size while preventing degradation of overall capacity and characteristics. A memory array of semiconductor memory devices is provided.

1 is a layout diagram showing the overall structure of a 4M memory array in 8 prior art as one embodiment of the 512K block.

FIG. 2 is a layout view showing an overall structure of a 4M memory array having 16 256K blocks according to one embodiment of the prior art. FIG.

3 is a layout view illustrating a memory array array structure according to an embodiment of the present invention.

According to the technical spirit of the present invention for achieving the above objects, in the memory array of the semiconductor memory device consisting of a sub-memory array array of memory arrays are arranged repeatedly at regular intervals in the row and column direction, at least one or more A first memory array block and at least one second memory array positioned at left and right sides of the first memory array blocks and arranged in the column direction; and at least one second memory array different from the first memory array blocks; And array blocks.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings.

3 is a layout diagram illustrating a memory array array structure according to an embodiment of the present invention. Referring to FIG. 3, two sub-memory arrays 10-1 through 10-4 are arranged in left and right sides of each of the two-memory array arrays 10 and a plurality of sub-memory arrays 20-1 through. 8 memory array arrays 20 arranged in the center and 20-4, sense amplifier 7 provided in each memory array array block, column decoder 5 connected to a column line, and a row line It consists of 3 low decoders. Here, the memory array array blocks 10 have a capacity of 512K and the memory array array blocks 20 have a capacity of 256K. And the total memory capacity is 4 mega. Meanwhile, in FIG. 1, block redundancy cannot be performed due to the sharing of sense amplifiers. In FIG. 3, two memory beam array blocks among the left and right memory bank array blocks and two memory block arrays among the central memory bank blocks are shown in FIG. 3. Block redundancy can be implemented by selecting and using as a redundancy block. In the structure of FIG. 1, when the operating consumption charge is assumed to be 100, the operation consumption charge is 50, which is half of that in the structure of FIG. 2, and the operating consumption charge is 75, which is the middle of both. Therefore, the structure of FIG. 3 is smaller in noise than the structure of FIG. In addition, since the bit line loading at a farther point from the power supply point can be reduced by bringing the block on the weak side of the power weaker portion, there is an advantage of reducing the speed limit due to power than the structure of FIG.

According to the present invention described above, the memory chip array blocks having memory capacities and sizes having different capacities and sizes reduce chip size compared to a single memory chip array composed of memory chip array blocks having large and small single capacities and sizes. At the same time there is an effect that can prevent the deterioration accordingly.

Claims (2)

A memory array of a semiconductor memory device, comprising memory arrays in which memory chips are repeatedly arranged at regular intervals in a row and column direction. At least one first memory array array blocks, And at least one second memory chip array blocks that are positioned to the left and right of the first memory chip array blocks and are arranged in the column direction different from the first memory chip array blocks. Memory array of semiconductor memory devices. 2. The memory array of claim 1, wherein a memory array array block of the first and second memory array arrays having a smaller number of memory arrays is configured adjacent to a column decoder.