KR19980030794A - Semiconductor memory device with increased cell node capacitance - Google Patents

Abstract

A cell of a semiconductor memory device, which is designed to simplify the configuration of a memory cell and to reduce the area of a chip while increasing the node capacitance, forms a capacitor in a node region of a cell, but the potential of the capacitor is caused by the voltage of one cell node. It has a structure in which the electrode of the upper capacitor is electrically connected to one cell node so as to be determined.

Description

Semiconductor memory device with increased cell node capacitance

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of increasing cell node capacitance of an SRAM.

Semiconductor manufacturers have recently used thin-film transistors as cell load elements to manufacture SRAM cells in response to the trend of increasingly high integration and low power. However, in the case of forming a cell by using a thin film transistor as a load element, a decrease in node capacitance occurs due to a decrease in cell size. Since the reduction of node junction capacitance affects the stability of the cell and increases the soft error rate, a countermeasure for increasing the cell node capacitance when using such a thin film transistor is required.

In order to provide a thorough understanding of the present invention, the thin film transistor has been used for a function of the memory cell of the SRAM and what arrangement and connection relationship with other components in the cell will be described first. 11 shows an equivalent circuit diagram of a typical SRAM cell. As is known, a representative structure of a memory cell array of an SRAM semiconductor memory device has a matrix form in which unit memory cells formed as in the circuit configuration of FIG. 11 are arranged between a plurality of rows and a plurality of columns, respectively. It is coming true. In FIG. 11, the N-type transistors N1 and N2 having gates connected to the word lines WL in the row direction respectively transfer potentials on the nodes 10 and 20 to the bit line pairs BL and BLB, respectively, or provide them from the bit line pairs BL and BLB. A pass transistor that transfers the potential to the nodes 10 and 20. The pass transistor is also called an access transistor because of its connection with the word line. The N-type MOS transistors N3 and N4 each having a channel connected between the nodes 10 and 20 and the ground VSS are pull-down transistors, which are also referred to as driving transistors. The morphed transistors P1 and P2 having channels connected between the power supply voltage VCC and the node are load transistors. The gate of the load transistor P1 and the pull-down transistor N3 are commonly connected to the node 20, and the gate of the load transistor P2 and the pull-down transistor N4 are commonly connected to the node 10 to form a flip-flop structure. In the memory cell configured as described above, a load for operating the cell is provided through the morph transistors P1 and P2, and the load transistor is manufactured as the thin film transistor (TFT). When a load is provided to the nodes 10 and 20 and a word line selection signal is applied, data transfer is performed between the bit line pairs BL, BLB and memory cells. In the cell structure of FIG. 11, it can be seen that the cell node becomes the node that the thin film transistors P1 and P2 provide loads, that is, the nodes 10 and 20. In order to solve the soft error problem caused by the reduction of the junction capacitance of the cell node due to the decrease of the cell size, conventionally, a buried layer doped with a low concentration of the ion type in the bulk silicon layer is formed to charge by the effect of narrow passage. A method of reducing the collection mechanism has been proposed. However, this method has to be accompanied by additional high-energy ion process, which causes manufacturing difficulties and increased cost. As another solution, in the case of the upper gate type thin film transistor, there is a method of forming a plate poly layer in the region of the cell node to receive a power supply voltage, but this is also undesirable because it weakens the current characteristics of the thin film transistor.

Recently, a process cross-sectional structure of an SRAM cell employing a lower gate type thin film transistor is shown in FIG. 10 to further reduce the size of the chip and further improve the problem of reducing the junction capacitance of the cell node. FIG. 10 is a vertical cross-sectional structure diagram of a recent SRAM memory cell, and has a bottom gate type structure while employing a thin film transistor for a load. Referring to Fig. 10, one of the cell nodes 10 and 20 becomes a portion where the gate of the TFT and the substrate layer come into contact with each other. However, this structure also has a problem in that the two nodes are electrically connected, so that the cell node capacitance is not preferably increased.

Accordingly, it is an object of the present invention to provide a cell of a semiconductor memory that can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a semiconductor memory device capable of increasing cell node capacitance of an SRAM without degrading current characteristics.

1A and 1B are vertical cross-sectional structural views of a memory cell in accordance with an embodiment of the present invention.

2 to 9 are layout plan views showing a sequence of steps for making the structures of FIGS. 1A and 1B.

10 is a vertical cross-sectional structure diagram of a conventional general memory cell.

11 is an equivalent circuit diagram of a typical SRAM cell.

According to the present invention for achieving the above object, a capacitor is formed in the node region of the cell, but the electrode of the upper capacitor is electrically connected to one cell node so that the potential of the capacitor is determined by the voltage of one cell node. It features.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In addition, in the following description, there are many specific details such as components of a specific circuit, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It will be self-evident to those who have knowledge.

In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Meanwhile, in the detailed description of the present invention, specific embodiments of the SRAM memory will be described, but various modifications can be made without departing from the scope of the present invention. Therefore, in order to emphasize the improvement of the transistor gate structure used in the load for convenience of description and illustration, the cell node will be described in cross section and plan view.

1A and 1B show vertical cross-sectional structure diagrams of a memory cell according to an embodiment of the present invention. 2 to 9 are layout plan views sequentially showing the sequence of steps for making the structure of FIGS. 1A and B.

Referring to FIGS. 1A and 1B, a cross-sectional view is shown in which a capacitor is formed in a node region of a cell, but an electrode of an upper capacitor is electrically connected to one cell node so that the potential of the capacitor is determined by the voltage of one cell node. . Here, the upper electrode of the capacitor is separated from the channel region and the drain offset region.

Referring to FIG. 2, the layout planar structure after forming the active pattern of the cell can be seen. 3 shows a planar structure after the gate poly is formed, reference numeral 120 denotes a portion of the pull-down transistor, and 121 denotes a gate poly-forming portion of the pass transistor. 4 is a plan view after formation of a second polysilicon layer to be used as a ground line and a word line in the cell. 5 is a plan view after formation of a third polysilicon layer to be used as the gate poly of the TFT. 6 is a plan view after formation of the fourth polysilicon layer to be used as the channel body of the TFT. The channel poly reoxidation process is performed as a subsequent process. 7 is a plan view showing only the TFT. Subsequently, a silicon nitride film to be used as the dielectric material of the capacitor is laminated. The thickness of the silicon nitride film is preferably about 100 angstroms. Fig. 8 is a plan view after formation of a contact hole for electrically connecting the drain and the gate of the channel of the TFT and at the same time connecting the node poly of the capacitance poly and the SRAM cell. In the subsequent step, the capacitor polysilicon is depoted. 9 is a plan view after patterning a poly layer for capacitors. In this manner, the steps shown in FIGS. 2 to 9 are sequentially performed to obtain the cross-sectional structures of FIGS. 1A and 1B.

Therefore, when the capacitor is formed in the node region of the cell, it has a structure in which the electrode of the upper capacitor is electrically connected to one cell node, thereby coping with the soft error rate by increasing the node capacitance without affecting the characteristics of the load transistor. .

According to the present invention as described above, when the capacitor is formed in the node region of the cell has a structure in which the electrode of the upper capacitor is electrically connected to one cell node so that the potential of the capacitor is determined by the voltage of one cell node, The chip area can be reduced while increasing node capacitance.

Although the present invention described above has been limited to the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (3)

In a semiconductor memory device: And forming a capacitor in a node region of the cell, wherein the electrode of the upper capacitor is electrically connected to one cell node so that the potential of the capacitor is determined by the voltage of one cell node. The semiconductor memory device of claim 1, wherein the upper electrode of the capacitor is separated from the channel region and the drain offset region. 2. The semiconductor memory device according to claim 1, wherein the interlayer insulating film of said capacitor is made of a silicon nitride film.