KR19980030441A - High voltage semiconductor device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage semiconductor device having a novel structure capable of improving the characteristics of a device according to high voltage driving, and a method of manufacturing the same, wherein a gate having a hollow shape, such as a gate oxide film and a gate oxide film formed in a predetermined area, is A first concentration type substrate having the lowest conductivity type, a first high concentration source / drain region and a second high concentration source / drain region of the second conductivity type formed on the surface of the semiconductor substrate with respect to the gate, respectively, and the first and second The first conductive second and second low concentration drain regions formed under the high concentration drain region and the first and second low concentration drain regions while being in contact with a predetermined portion under the gate oxide film, and surrounding the first and second high concentration source regions. First and second low concentration well regions of the first conductivity type to be partially bonded to the first and second high concentration source regions, A first conductive type first and second high concentration well region bonded to and formed on the surface of the first and second low concentration well regions, the second surrounding the first and second high concentration well regions and the first and second high concentration source regions. The source electrode and the first and the first electrode of the conductivity type, and the first and second well-concentrated source regions are joined to each other, and the second and second well-concentrated source regions are in contact with each other. And a drain electrode formed on each of the second high concentration drain region, wherein the doping levels of the high concentration, the low concentration, and the lowest concentration are in the order of high concentration> low concentration> lowest concentration.

Description

High voltage semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a high voltage semiconductor device having a novel structure capable of improving the characteristics of the device according to high voltage driving, and a manufacturing method thereof.

In general, when an external system using high voltage is controlled by an integrated circuit, the integrated circuit needs an element for high voltage control therein, and such an element needs a structure having a high breakdown voltage. .

That is, in order to enable an external system to operate smoothly in a drain of a transistor to which a high voltage is directly applied, a punch through voltage between the drain and the substrate and a breakdown voltage between the drain and the well are It must be greater than the high voltage.

FIG. 1 is a process sectional view showing a conventional high voltage transistor having a structure having a low concentration layer of the same conductivity type as a drain under the drain region in order to obtain a high breakdown voltage as described above.

As shown in FIG. 1, a conventional high voltage transistor includes a semiconductor substrate 1 having a first conductivity type well, a gate oxide film 3 formed in a predetermined region on the semiconductor substrate 1, and a gate oxide film 4. The gate 4 formed on the upper portion, the high concentration source region 5 of the second conductivity type formed in a predetermined portion of the semiconductor substrate 1, the common high concentration drain region 6, and the source and drain regions 5 and 6; Source and drain electrodes 7 and 8 formed on the upper portion, a low concentration semiconductor region 2 of the second conductivity type formed under the drain region 6, and a channel region between the drain and source regions 5 and 6 ( 9).

In the high voltage transistor, the gate oxide layer is formed to have a thickness of 800 kV to 1,000 kV for high voltage driving. As the driving voltage increases, the gate oxide layer needs to have a thicker thickness and an appropriate threshold voltage value. In order to have the doping level of the well region must be reduced.

However, if the doping level of the well is lowered, a punch-through phenomenon occurs between the source and the drain, so that the leakage current flows, and the latch-up is caused, thereby degrading the characteristics of the device due to the high voltage driving.

Accordingly, the present invention has been made in view of the above-described problems, and prevents latch-up and punch-through due to the thickness of a gate oxide film, thereby improving the characteristics of the device according to the high voltage driving and its fabrication. The purpose is to provide a method.

1 is a cross-sectional view showing a conventional high voltage transistor.

2A through 2J are cross-sectional views sequentially illustrating a method of manufacturing a high voltage N-channel MOS transistor according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a high voltage P-channel MOS transistor according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11: p ^- semiconductor region 12: n ^- source region

13a, 13b: p ^- well region 14a. 14b: n ^- drain region

15 pad oxide film 16 nitride film

17: preliminary oxide film 18: field oxide film

18-1: Oxide Film 19: Gate Oxide Film

20: Gate

21a, 21b: n ⁺ source region

22a, 22b: n ⁺ drain region

23a, 23b: p ⁺ well region

24: insulating film

25 source electrode

26: drain electrode

The high voltage semiconductor device according to the present invention for achieving the above object is a low-concentration substrate of the first conductivity type formed with a gate oxide film formed in a recessed shape in a predetermined region of the upper portion and a gate having a recessed shape like the gate oxide film, and the gate A first high concentration source / drain region and a second high concentration source / drain region of a second conductivity type formed on the surface of the semiconductor substrate, respectively, and a second conductivity type first portion formed under the first and second high concentration drain regions; And a first conductivity type in contact with a second low concentration drain region and a predetermined portion of the lower portion of the gate oxide film, surrounding the first and second low concentration drain regions, and partially contacting the first and second high concentration source regions. First and second low concentration well regions of and the first and second high concentration source regions, the first and second low concentration regions Lowest concentration of the first conductivity type first and second high concentration well regions formed on the surface of the concentration well region and the second conductivity type surrounding the first and second high concentration well regions and the first and second high concentration source regions. A source electrode in contact with a source region, a portion where the first high concentration well region and a first high concentration source region are joined, and a portion where the second high concentration well region and the second high concentration source region are joined, and the first and second portions, respectively. It characterized in that it comprises a drain electrode formed on each of the high concentration drain region.

In addition, a method of manufacturing a high voltage semiconductor device according to the present invention for achieving the above object is provided by providing a substrate of the lowest concentration layer of the first conductivity type, a second concentration source region of the second conductivity type of a predetermined depth on the substrate; Forming a first and second low concentration well region of a first conductivity type of a predetermined depth in the lowest concentration source region, and forming a second conductivity type of a second depth of predetermined depth in the first and second low concentration well regions Forming a first and a second low concentration drain region, and forming a predetermined recessed region on the surface of the substrate in the center of the lowest concentration region so as to contact the first and second low concentration well regions and the first and second low concentration drain regions. Forming a field oxide film for isolation between devices on the substrate, and forming the gate oxide film and the gate oxide on the substrate in the recessed region. Forming a first high concentration source / drain region and a second high concentration source of a second conductivity type in a predetermined portion of a surface of each of the lowest concentration region and the first and second low concentration drain regions on both sides of the recessed gate; / Forming a drain region, and forming first and second high concentration well regions to be joined to the first and second high concentration source regions at predetermined portions of exposed first and second low concentration well region surfaces on both sides of the gate. And source electrodes in contact with the portion where the first high concentration well region and the first high concentration source region are joined, and the portion where the second high concentration well region and the second high concentration source region are joined, respectively, and the first and second high concentration. And forming a drain electrode in contact with the drain region, respectively.

In addition, the high concentration, the low concentration and the lowest concentration doping level is characterized in that the order of high concentration> low concentration> lowest concentration.

According to the present invention having the above configuration, in order to increase the breakdown voltage, the drain region is formed in a low concentration layer as in the prior art, and the source region of the lowest concentration layer is formed so as to cover the entire transistor, so that the hot carrier ( By capturing holes caused by hot carriers, the problem of latch-up and punch-through can be avoided.

On the other hand, the amount of current increases as the channel region under the gate oxide film is shortened by the formation of the hollow gate.

EXAMPLE

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

2J is a cross-sectional view illustrating a high voltage N MOS transistor according to an embodiment of the present invention, wherein p ⁻ substrate 11, a gate oxide film 19 formed in a recessed shape in a predetermined region on the substrate 11, and a gate oxide film (19) First n ⁺ source / drain regions formed on the surface of the substrate 11 and formed on the surface of the substrate 11 centered on the gate electrode 20 and formed in the same shape as the gate oxide film 19, respectively. (21a, 22a) and the 2 n ⁺ source / drain regions (21b, 22b) and, the first and the 2 n ⁺ drain region (22a, 22b) on the lower respectively formed first and the 2 n ^- drain region (14a , 14b and the first and second n ^- drain regions 14a and 14b, respectively, in contact with a predetermined portion of the lower portion of the gate oxide film 19, and respectively, and the first and second n ⁺ source regions 21a and 21b. ) And the first and second p ⁻ well regions 13a and 13b which are partially bonded to each other, and the first and second n ⁺ source regions 21a and 21b, respectively, And a 2 p ^- well region (13a, 13b) on the surface formed of the first and the 2 p ⁺ well region (23a, 23b) and a first and a 2 p ^- well region (13a, 13b) and the first and N ^- source region 12 surrounding the entirety of the second n ⁺ source regions 21a and 21b, a portion where the first p ⁺ well region 23a and the first n ⁺ source region 21a are joined, and The source electrode 25 is in contact with the portion where the 2 p ⁺ well region 23b and the second n ⁺ source region 21b are joined to each other, and the first and second n ⁺ drain regions 22a and 22b are in contact with each other. Each drain electrode 26 is comprised.

In this case, the first conductivity type refers to trivalent ions such as boron (B), gallium (Ga), or indium (In), that is, P type, and the second conductivity type is phosphorus (P), arsenic (As), or the like. Means a pentavalent ion, that is, N-type.

In addition, the high concentration doping level sequence> low concentration> as a sequence of lowest level, for example the doping level of the order p> p of the first conductivity type of the impurity ^-> p ^-, and the second doping level of the order of conductivity type is n> n ^-> n ^- a.

Next, a method of manufacturing a high voltage N MOS transistor having the above configuration will be described.

2A through 2J are cross-sectional views sequentially illustrating a method of manufacturing a high voltage N MOS transistor according to an embodiment of the present invention.

First, as shown in FIG. 2A, an oxide film (not shown) is grown on a p ⁻ substrate 11 by a conventional thermal oxidation process, and a nitride film (not shown) is formed on the top thereof by a known method. Thereafter, a photoresist pattern (not shown) is formed on the nitride layer by photolithography. The nitride layer below is etched using the photoresist pattern and the photoresist pattern is removed to form a nitride ion implantation mask.

By selectively implanting n ^- onto the substrate 11 through an ion implantation process using the nitride film mask, annealing is performed to form the n ^- source region 12 having a predetermined depth, and then a known method. The nitride film mask is removed.

As shown in FIG. 2B, p ^{− having a} higher doping level than p ⁻ is selectively implanted into an n ⁻ source region 12 by a mask process and an ion implantation process as described above, followed by annealing. First and second p ^- well regions 13a and 13b having a predetermined depth are formed side by side.

As shown in Figure 2c, the first and the 2 p ^- to inject, and ^anneal-well region (13a, 13b) to the n mask process and an ion implantation process at a predetermined portion of the ^- higher than the doping level n The first and second n ^- drain regions 14a and 14b having a predetermined depth are formed, respectively.

As shown in FIG. 2D, a predetermined pad oxide film 15 and a nitride film 16 are sequentially deposited on the semiconductor substrate 11, and a photoresist pattern (not shown) is formed on the nitride film 16 by photolithography. Form. Subsequently, the nitride film 16 at the gate formation site is etched using the photosensitive film, and the photosensitive film is removed by a known method.

As shown in FIG. 2E, an oxide film of a portion where the nitride film 16 is removed through a high temperature thermal process is grown to be recessed into the substrate 11, for example, to form a preliminary oxide film 17 in the form of a predetermined field oxide film. Form.

As shown in FIG. 2F, the nitride film 16 is removed in a conventional manner, and the pad oxide film 15 and the preliminary oxide film 17 are removed to form a recessed shape of the gate forming portion on the substrate 11.

As shown in Fig. 2G, a field oxide film 18 for inter-element separation is formed on the substrate 11 in a known manner. In addition, although the first and second p ^- well regions 13a and 13b and the first and second n ^- drain regions 14a and 14b are not shown at the junction when the field oxide film 18 is formed, the upper portion is not shown. In order to insulate the wiring, a predetermined oxide film 18-1 is additionally formed.

As shown in FIG. 2H, the gate oxide film 19 and the gate 20 are formed in a recessed shape on the recessed substrate 11 by a known method.

As shown in FIG. 2I, the exposed n ^- source region 12 surface and exposed first and second n ^- drain regions 14a and 14b on both sides of the gate 20 through a mask process and an ion implantation process. N ⁺ is injected to a predetermined portion of the surface and annealed to form first n ⁺ source / drain regions 21a and 22a and second source / drain regions 21b and 22b.

Subsequently, through the mask process and the ion implantation process, the first and second n ⁺ source regions may be formed on predetermined portions of the exposed surfaces of the first and second p ⁻ well regions 13a and 13b on both sides of the gate 20. 21a, the p ⁺ implanted to junction 21b), respectively, to form a first and a 2 p ⁺ well region (23a, 23b of the p ^+).

As illustrated in FIG. 2J, an insulating film 24 is formed over the entire structure, and the first and second n ⁺ drain regions 22a and 22b are bonded to each other through the photolithography and etching processes. Contact holes (not shown) for electrical coupling are formed with the 2 n ⁺ source regions 21a and 21b and the first and second p ⁺ well regions 23a and 23b.

Then, a metal is deposited on the contact hole and the insulating layer 21 and then patterned to form a drain electrode 26 and each source electrode 25 in which the well region and the source region are bonded to each other.

On the other hand, it can be easily understood by those skilled in the art that the P MOS transistor can be manufactured as shown in FIG.

In the high voltage N-MOS transistor according to the above embodiment, when a voltage is applied to a recessed gate, a source region is formed under the gate oxide layer, and channels are formed in both well regions around the gate.

Then, the drain regions as in the prior art to increase the breakdown voltage ^n-by a hot carrier (hot carrier) in the channel region as a source region formed in the layer so as to surround the entire ^transistor formed in a layer and, n By capturing the generated holes, problems with latch-up and punch-through can be avoided.

On the other hand, the amount of current increases as the channel region under the gate oxide film is shortened by the formation of the hollow gate.

In addition, this invention is not limited to the said embodiment, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

As described above, according to the present invention, it is possible to realize a high voltage semiconductor device having a new structure and a manufacturing method thereof, which can improve the characteristics of the device according to the high voltage driving.

Claims (12)

The first conductivity type lowest concentration substrate having a gate oxide film formed in a recessed shape on a predetermined region and a gate formed in a recessed shape like the gate oxide film, and a second conductivity type formed on the surface of the semiconductor substrate with respect to the gate A first high concentration source / drain region and a second high concentration source / drain region, a second conductivity type first and second low concentration drain region formed under the first and second high concentration drain regions, and a predetermined portion under the gate oxide film. First and second low concentration well regions of a first conductivity type surrounding the first and second low concentration drain regions and partially contacting the first and second high concentration source regions in contact with a portion; And first conductivity type first and second high concentration well regions that are bonded to a second high concentration source region and formed on surfaces of the first and second low concentration well regions. And a second conductivity type lowest concentration source region surrounding the first and second high concentration source regions and the entire first and second high concentration source regions, and the first high concentration well region and the first high concentration source region are joined to each other. And a source electrode in contact with the portion where the second portion and the second high concentration well region and the second high concentration source region are respectively joined, and a drain electrode formed on the first and second high concentration drain regions, respectively. Semiconductor device. 2. The high voltage semiconductor device of claim 1, wherein the doping levels of the high concentration, the low concentration, and the lowest concentration are in the order of high concentration> low concentration> lowest concentration. 2. The high voltage semiconductor device of claim 1, wherein the first conductivity type is P type and the second conductivity type is N type. The high voltage semiconductor device of claim 1, wherein the first conductivity type is N type and the second conductivity type is P type. The method according to any one of claims 1 to 4, wherein the high concentration> a low concentration> If the concentration level of the order of lowest concentration of the first type or the second conductivity type is the P ⁺ p> p ^-> p ^-, and High-voltage semiconductor device, characterized in that ^- either the first or the second type when the conductivity type is N ⁺ n> n ^-> n. Providing a substrate of a first conductivity type lowest concentration layer, forming a second conductivity type lowest concentration source region of a predetermined depth on the substrate, and forming a first conductivity type of a first depth of a predetermined depth in the lowest concentration source region Forming first and second low concentration well regions, forming first and second low concentration drain regions of a second conductivity type of a predetermined depth in the first and second low concentration well regions, and the first and second low concentration well regions Forming a predetermined recessed region on the surface of the substrate at the center of the lowest concentration source region so as to contact a well region and the first and second low concentration drain regions, and forming a field oxide layer on the substrate for separation between devices. Forming a gate oxide film and a gate on the substrate in the recessed region, the lowest concentration source region on both sides of the recessed gate, and Forming a first high concentration source / drain region and a second high concentration source / drain region of a second conductivity type in a predetermined portion of a surface of each of the first and second low concentration drain regions, the exposed first and second sides of the gate; 2 forming a first and a second high concentration well region on a predetermined portion of the surface of the low concentration well region so as to be bonded to the first and second high concentration source region; and a portion where the first high concentration well region and the first high concentration source region are joined. And forming a source electrode in contact with a portion where the second high concentration well region and the second high concentration source region are respectively joined, and a drain electrode in contact with the first and second high concentration drain regions, respectively. Method of manufacturing a high voltage semiconductor device. The method of manufacturing a high voltage semiconductor device according to claim 6, wherein the doping levels of the high concentration, the low concentration, and the lowest concentration are in the order of high concentration> low concentration> lowest concentration. The method of manufacturing a high voltage semiconductor device according to claim 6, wherein the first conductivity type is P type and the second conductivity type is N type. The method of manufacturing a high voltage semiconductor device according to claim 6, wherein the first conductivity type is N type and the second conductivity type is P type. The method according to any one of claim 6 through claim 9, wherein the high concentration> a low concentration> If the concentration level of the order of lowest concentration of the first type or the second conductivity type is the P ⁺ p> p ^-> p ^-, and method for manufacturing a high voltage semiconductor device, characterized in that ^- the first or second conductivity type in this case is an N ⁺ n> n ^-> n. The method of claim 6, wherein the forming of the recessed region comprises sequentially forming a pad oxide film and a nitride film on the semiconductor substrate, etching the nitride film, and forming the oxide film on a portion where the nitride film is etched. Growing a phase, removing the nitride film and the pad oxide film, and removing the grown oxide film. 7. The high voltage semiconductor device of claim 6, wherein a predetermined insulating film is additionally formed at a portion where the first and second well regions and the first and second drain regions are joined to each other in the forming of the field oxide film. Manufacturing method.