KR19980029428A - Registers Supporting Bypass Paths in Pipeline Processors - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Register file that supports the bypass path in the pipeline processor.

2. The technical problem to be solved by the invention

Instead of using an external index comparator and MUX circuit to provide a bypass path in the pipeline processor, it has a feedback path in a specially designed register cell to provide a bypass path directly.

3. Summary of Solution to Invention

In the register file structure supporting the bypass path of the pipeline processor, the structure of the register file providing the bypass path includes the decoding circuits of the write index and the read index, the register cells extended according to the number of bits of data, and the read data. Providing a register file structure comprising a circuit for selecting.

4. Important uses of the invention

The present invention provides a register file structure for supporting a bypass path on a cell-by-cell basis in a register file structure of a pipeline processor having an internal feedback path without additional circuitry, thereby creating a standby state caused by data dependency. Used as a circuit to reduce

Description

Register File Supporting Bypass Paths in Pipeline Processors

The present invention relates to a register file for supporting a bypass path in a pipeline processor. In particular, the present invention provides a feedback path in a specially designed register cell without using an external index comparator and a mux circuit to provide a bypass path. It is directly related to a circuit that provides a bypass path.

In general, in a register file structure that stores data of a floating point unit having a pipelined arithmetic processor, the pipelined processors have one or more processing latencies. That is, a few cycles after the actual operation starts, the result of the operation can be obtained. Thus, subsequent operations using the result of that operation can be started only after the previous operation is finished. Until then, the next operation waits in a waiting state.

1A is an embodiment of a pipeline stage according to the prior art. First, when the first operation 11 adds to the operand 15 corresponding to the top of the stack and the operand 16 below it, the E stage 21 in the pipeline stage stage. ) Reads data from the register file, then actually adds in the x1 (22) and x2 (23) stages, and writes the result to the stack top 15 of the register file in the WF stage 24. Indicates. The next operation 12 then multiplies the written operand 15 of the top by the operand 17 below the top of the tower and writes it back to the stack top 15, where the result of the addition must be the WF stage 24 for multiplication. You have to wait until then. At this time, latency of addition is called 3. In addition, the E stages 26, 27, 28, and 29 of the multiplication must read data from the register file. However, since the data written to the register file cannot be read until the WF stage 24 of the actual addition passes, three cycles (26, 27, After waiting 28), data can be read and multiplied. In this way, having a stack structure with a register file creates a lot of data dependency on the top of the stack, which degrades overall performance. The prior art for solving this problem is a pipeline structure having a bypass path. 1B relates to one embodiment of a pipeline stage having such a bypass path.

Referring to the drawings, a bypass path in which the WF stage 24 in which the result of the previous addition is written in the register file is simultaneously the operand read stage 28 of the next instruction. The register structure is shown. In this case, the cycle in the standby state becomes two cycles 26 and 27, and a gain of one cycle can be obtained than in the case of FIG. 1A. In total, this happens many times and you can benefit greatly.

In the prior art for providing such a bypass path, the bypass path is not provided by the cell itself, but an additional circuit is disposed outside. That is, a cell of a register file is normally used as a latch type cell, and the index of an externally read register is compared with the currently written index, and in this case, the data to be written is sent to the read port. In this case, a circuit for comparing the indices of reads and writes and a circuit for MUXing data are required. In addition, multiple read and write ports require as many comparators and data muxes as possible.

As such, when the bypass path is provided to a circuit added to the outside of the register file, the area of the chip increases.

An object of the present invention is to provide a register cell having a feedback path without using an index comparator and a mux circuit externally to provide a bypass path in a register file, so that data of a cell that is presently present is regenerated. It is to provide a bypass path by feeding back to the register input stage and selecting new data. Alternatively, the register file structure allows new data to be written to the register.

1A is an embodiment of a pipeline stage according to the prior art.

1B is an embodiment of a pipeline stage with a bypass path.

2 is an overall register file structure diagram in accordance with the present invention;

3 is a structural diagram of a register cell having a feedback path in accordance with the present invention;

In the present invention for achieving the above object, in the register file supporting the bypass path in the pipeline processor, the structure of the register file providing the bypass path is the decoding circuit of the write index and read index, and the number of bits of data According to the present invention, there is provided a register file comprising an extended register cell and a circuit for selecting read data.

In the decoding circuit, the decoder of the write port receives an index indicating the number of an entry of a register to be written and an enable signal indicating that a write operation is performed, and supplies a write enable signal of a corresponding register entry.

In the decoding circuit, a decoder of a read port receives an index indicating a number of a register entry to be read and supplies a read enable signal.

The decoder of the write port and the read port has a decoder corresponding to the number of write and read ports.

The register cell includes NMOS transistors for selecting and passing data to be written, an AND gate for ORing all write enable signals, a MUX for selecting old and new data, and a flip for storing actual data. It consists of a tri-state buffer that controls the sending of data to the flop cell and read port.

The MUX selecting the old data and the new data selects one of the two data as the output signal of the logical sum, and uses the result as an input of the tree-stay buffer.

Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.

2 is a structural diagram of an entire register file according to the present invention. The register file 40 assumed in the present invention is a register having two write ports 33 and 34 and two read ports 37 and 38, with each entry floating in extended double precision. It consists of 80 bits that can store floating point data. You can write to two different locations at the same time and read the same entry from two read ports simultaneously. Just writing data from different light ports to the same thing prevents the external logic from checking for dependencies.

Referring to the drawings, the two write ports 33 and 34 are wr_data1 (41) and wr_data2 (42), which are 80 bits of data to be written, and the index wr_index1 (43) and wr_index2 of the register entry where the bits are to be written, each having three bits. (45)) and two write enable signals, wr_enable1 (44) and wr_enable2 (46), and the two read ports (37, 38) are rd_index1 (47) and rd_index2 (48), which are indexes of entries to read. ) And rd_enable1 (54) and rd_enable2 (56) which are read enable signals.

Two write decoders 61, 62 of the write ports 37, 38 are used to make write enable of each of the register entries, and two read decoders 63, 64 of the read ports 37, 38 are read ports. It is used to put the data of (37, 38) from the register file 40 into the corresponding entry. The last MUXs 65, 66 of the read ports 37, 38 are for writing data to the read port latch only when the actual read operation is enabled.

Each 80-bit entry of the register file consists of two write enable signals wr_enable1 (44) and wr_enable2 (46), respective data, and two read enable signals (rd_enable1 (54) and rd_enable2 (56)).

3 shows the structure of a register cell with a feedback path.

In order to support the bypass path, a circuit for comparing the index of the currently written entry with the index of the read entry is used to export the currently written data to the outside only in the same case. However, the present invention naturally supports the bypass path by adding a feedback path without comparing the indexes to be read so that always written data goes out. That is, unless new data is written in a cycle, old data may be maintained. In the present invention, data is written to the read port immediately by updating the data every cycle. .

Referring to the drawings, first, data 41 and 42 written to the write port pass through one NMOS transistor 71 and 72, which can open only one of the two ports to send data, and none of them are written. Node 91 is plotted. The next 2x1 MUX 77 selects the outputs of the NMOS transistors 71 and 72 if data is being written to the current cycle, or data currently stored in the D-flip-flop 78 if not written. Select again. Therefore, there is no problem even if node 1 is floated when writing is not performed. Node 2, thus selected, is always latched back to D-flip-flop 78 at the end of every cycle to properly perform the write operation. In general, the read port of the register performs a read operation with the data of the node 93, but in the present invention, since the currently written data must be bypassed immediately, the node 92 is output to the outside. do. That is, when there is no write operation, node 3 is transferred to node 2 again through 2x1 MUX 77, and when the write operation is performed, the node 93 enters through NMOS transistors 71 and 72. Write data will go out. In this case, you can bypass regardless of which of the two light ports you are coming from.

In general, when reading data from a register file, this structure cannot be used if the data being read is used directly in the cycle. This is because valid data when bypassed comes after the middle of the cycle, or in a structure that uses a feedback path, the read access time is inevitably larger than when read directly. However, in the overall pipeline design, step E (21 in Fig. 1A) is defined as reading data from a register file, so there is no problem in increasing access time until the end of the cycle. In other words, in the pipeline structure supporting the bypass path, it is preferable to define the E level in this way. The structure of the cell supporting the bypass path with the feedback path proposed in the present invention can be simply designed as shown in FIG. 3, and a large gain can be obtained in terms of the overall area. In addition, by supporting the bypass path in the structure of the cell itself, there is an advantage that no additional circuitry needs to be added to the outside.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, according to the present invention, by providing a register cell that supports a bypass path of a pipeline processor, an external index comparator used in the past is not required, and an external data MUX circuit used in the past is internal to a cell. Since it is a standardized structure, the total area can be reduced. In addition, in the case where there are several ports for read and write, the index and data MUX circuit, which is increased in proportion to the conventional one, may provide a constant circuit regardless of the number of read and write ports in the present invention.

Claims (6)

A register file structure supporting a bypass path in a pipeline processor, the register file structure comprising: a decoding circuit for write and read indices, an extended register cell according to the number of bits of data, and a circuit for selecting read data Register file. The decoder of claim 1, wherein the decoder of the write port of the decoding circuit receives an index indicating a number of an entry of a register to be written and an enable signal indicating that a write operation is performed, and supplies a write enable signal of a corresponding register entry. Register file, characterized in that. The register file of claim 1, wherein the decoder of the read port of the decoding circuit receives an index indicating a number of a register entry to be read and supplies a read enable signal. The register file of claim 1, wherein the decoders of the write port and the read port of the decoding circuit have decoders corresponding to the number of write and read ports. 2. The register cell of claim 1, wherein the register cell includes transistors for selecting and passing data to be written, a gate for ORing all of the write enable signals, a MUX for selecting old data and new data, and a flip for storing actual data. A register file comprising a tri-state buffer that controls sending data to the flop cell, read port. The register of claim 5, wherein the MUX selecting the old data and the new data selects one of two data as the output signal of the logical sum, and uses the result as an input of the tree-stay buffer. file.