KR19980029048A - Structure of Integrated Multimedia Data Processor and Its Driving Method - Google Patents

Abstract

In the conventional multimedia data processing hardware, audio, video, and graphics are independently configured, media data is processed separately, thereby increasing system frequency by increasing frequency of use of the system bus due to frequent data transfer. To solve this problem, the present invention proposes a structure of a multimedia data processor incorporating audio and video functions, supports a local bus for efficient transmission of audio and video data, and provides high-speed data between video and audio data and a host memory. By adopting the DMA for mobile and the bus master function of the local bus, it is very suitable for high quality three-way video conferencing, and it is possible for multi-way video conferencing. This is disclosed.

Description

Structure of Integrated Multimedia Data Processor and Its Driving Method

The present invention relates to a multimedia system, and more particularly, to a structure of an integrated multimedia data processor supporting video conferencing and a driving method thereof.

In the conventional multimedia data processing hardware, audio, video, and graphics are separated and configured independently, media data is processed separately, or various types of media processing boards are used in applications such as video conferencing, thereby frequently transferring data between boards. This increases the frequency of use of the system bus, adding to the burden on system performance. In addition, in the case of video, only a part of the compression / restoration function is provided or the restoration processor is limited to one, so only video communication between the two could be expected. In addition, audio I / O is limited to applications because only one-way processing is possible at one time, and bi-directional listening and talking are not allowed, and the video frame rate or video overlay screen processed per second due to the bottleneck of media data processing due to the low speed system bus There is a deterioration in size and the like. As a result, large-scale media data, such as video conferencing, could only meet limited needs when moving between multimedia platforms to perform functions.

As described above, in the prior art, audio and video are separately configured, and in the case of video, the restoration function is only one module to support video conferencing between two parties, and in the case of audio, bidirectional is not supported, so There are many limitations to supporting multimedia applications.

Therefore, in the present invention, the system bus bottleneck generated by accommodating the media processing standard of the standard method widely used in multimedia applications, maximizing the utilization and expandability of media processing hardware resources, and individually configuring functions such as audio and video Integrated multimedia data that supports 3 or more computer video conferencing by adopting the concept of local memory and direct memory access (DMA) for efficient data transfer and system bus access by reducing the phenomenon. It is an object to provide a structure of a processor and a driving method thereof.

The structure of the integrated multimedia data processor according to the present invention for achieving the above object is to input / receive analog video signals of still or moving images in real time to compress / restore and export the result to an output device or host memory for other applications. It supports high speed data transfer to host memory, video stage to transmit to the network, audio stage to support voice compression / restoration and recording / playback function according to media type, local bus controller which is responsible for efficient data movement between various function blurs And a PCI bus interface stage performing a bus master / slave function.

In addition, a method of driving an integrated multimedia data processor according to the present invention for achieving the above object is to convert an analog video signal into a digital signal at the input video stage, and then to convert again to an analog signal, mixed with graphics data and output to the monitor And converting the analog signal into a digital signal at the input video stage, compressing the analog signal, and storing the compressed signal in a host memory, restoring the compressed video data stored in the host memory, converting the digital signal into a digital signal, and mixing with graphics data. Outputting to the monitor through the output to the monitor, restoring the MPEG compressed data of the host memory and performing analog conversion and amplification, and compressing the digital audio data at the audio stage where the analog audio signal is input to the host memory. Storing, Restoring the compressed data at an audio stage receiving the compressed audio data stored in the host memory, converting the amplified data into an analog signal, amplifying and outputting the compressed audio data to a speaker, and generating digital sound data from the audio codec inputted with the analog voice signal. And converting the digital sound data stored in the host memory into an analog signal in the received audio codec, amplifying the analog signal, and outputting the analog sound signal to the speaker.

1 is a structural diagram of an integrated multimedia data processor according to the present invention;

2A to 2C are operational flowcharts illustrating a compression / restore process of video data according to the present invention.

3 is an operation flowchart illustrating an MPEG audio decompression process according to the present invention.

4A and 4B are flowcharts of processing audio data using a standard speech compression / reconstruction algorithm according to the present invention.

5A and 5B are flowcharts illustrating the recording / playback process of the audio codec unit according to the present invention;

＊ Explanation of symbols on main parts of drawing

1: video stage, 2: audio stage, 3: local bus controller, 4: DMA controller, 5: PCI bus interface, 6: PCI bus, 7: host memory, 8: video signal input, 9: video processor, 10 : Frame buffer, 11: video signal output, 12: feature connector, 13: video compression / restore processor, 14: video / audio restoration processor, 15: first SRAM, 16: boot ROM, 17: first DRAM, 18 : 2nd SRAM, 19: Boot ROM, 20: 2nd DRAM, 21: Audio Compression / Restore Processor, 22: Audio Codec, 23: Audio Input / Output Processor, 24: 3rd SRAM, 25: EPROM, 26: PCI Bus Interface, 27: first data buffer, 28: second data buffer, 29: latch.

The present invention can process audio and video data in one integrated structure, reducing the number of system buses used when audio and video are separated, as well as DMA requests for audio and video and bus arbitration of local bus controllers. Feature enables high-speed data transfer with the host. In addition, video conferencing of about two characters can be performed with a conventional video board. However, since two types of video data streams can be restored at the same time with this structure and driving method, three-way video conferencing can be performed. The audio may process a moving picture expert group (MPEG) in addition to pulse code modulation (PCM) and adaptive differential pulse code modulation (ADPCM). Joint Photographics Expert Group (JPEG) for processing still images, MPEG for processing video, and H.261 algorithms for video conferencing. There is also a feature connector for connecting to graphics.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a structural diagram of an integrated multimedia data processor according to the present invention. As shown, the video stage 1, the audio stage 2, the local bus controller 3, the DMA controller 4 and the Peripheral Component Interconnect (PCI) bus interface stage 5 are shown. It consists of. The video stage 1 inputs an analog video signal of a still image or a moving image and compresses / restores it in real time, and outputs the result to an output device or to a host memory for other applications. The audio stage 2 reproduces the voice recording and reproducing and the sound by the sound source according to the media type. The local bus controller 3, the DMA controller 4, and the PCI bus interface stage 5 support efficient data transfer between the audio / video stage and the host system.

The PCI bus interface stage 5 follows the PCI standard and performs a bus master / slave function. Key features include PCI bus master / slave functionality and two independent DMA channels. It has four bidirectional first-in, first-out buffers (FIFOs) for the master, slave, and two DMA channels, and supports PCI clocks and asynchronous local clocks. As a component, the PCI bus interface 26 serves as a data relay between the video stage 1 and the PCI bus 6. The first data buffer 27 relays (buffers) data transfer between the data bus system input and output to the PCI bus interface 26 and the local bus where video is controlled. 32 bits of local bus data are used between the first data buffer 27 and the PCI bus interface 26. The second data buffer 28 relays (buffers) data transfer between the local bus data bus system and the audio unit 2 and exchanges 8-bit analog signals with the audio codec 22. The latch 29 temporarily stores the address output from the DMA controller 4 so that the address output from the DMA controller 4 changes until the PCI bus interface 26 and the local bus controller 3 read the corresponding data. It maintains the old address. The latch 29 uses PCI bus interface 26 and 2 to 23 bits of address bus bits, and the local bus controller 3 uses 8 to 11 bits of address bits.

The DMA controller 4 is a controller for directly accessing the host system memory through the PCI bus. The demands for DMA are for audio playback requests, audio capture requests, video encoder requests, and video decode requests for two video codecs. Upon request as described above, the DMA controller 4 drives the local bus usage request signal from the local bus controller 3 to start the transfer to the latch 29 when the local bus usage right is acquired.

The local bus controller 3 is a block for controlling the local bus generated inside the board through the PCI bus interface. The local bus controller 3 arbitrates the request for using the local bus, controls the local bus when the host system accesses local resources, and controls the DMA controller. It controls this when accessing the PCI bus, and interrupt control that delivers the interrupt of internal board resources to the host system through the PCI bus. It also controls the video processor 9, the video compression / restore processor 13, the video / audio reconstruction processor 14, the first data buffer 27 and the second data buffer 28, and the latch 29.

The video stage 1 inputs an analog video signal of a still image or a moving image, compresses or decompresses it in real time, and transmits the result to the monitor or the host memory 7. The configuration is as follows.

The video signal input unit 8 converts an analog composite video signal input from an external source into a digital signal through an analog-to-digital converter (ADC) and converts the analog composite video signal into digital data that can be processed by a computer. A luminance and chrominance (hereinafter referred to as YUV) video signal and a synchronization signal that pass through the decoder to represent the brightness / color of an analog signal (hereinafter referred to as YUV) are generated to generate a video processor 9 and a video compression / restore processor ( 13) to transmit.

The video processor 9 receives two input data from the video signal input unit 8 and the video compression / restore processor 13 or the video / audio reconstruction processor 14 to perform data processing such as format conversion and screen size scaling. The 32-bit processed frame buffer data is transmitted and received to the frame buffer 10.

The frame buffer 10 transmits and receives 32-bit frame buffer data to and from the video processor 9 and transmits the 32-bit frame buffer data to the video signal output unit 11 in the form of 32-bit video signal data.

The video signal output unit 11 overlays the video signal data received from the frame buffer 10 and the graphic data received through the feature connector 12 and outputs the graphics as color information sent to the color monitor. Digital to Analog Converter (DAC) is included. 244 between feature connector 12 and video output 11 allows TTL 74F244 to move data in only one direction. That is, data is moved from the feature connector 12 only to the video signal output unit 11, and the movement in the opposite direction is prevented.

The video compression / restore processor 13 receives the YUV 4: 2: 2 format video data output from the video signal input unit 8, performs a compression / reconstruction algorithm, and transmits the video data to the video processor 9. The video compression / restore processor 13 stores a first boot ROM 16 which stores a compression algorithm at initialization, and a first DRAM which stores data and video data necessary for performing the algorithm of the video compression / restore processor 13 (hereinafter, referred to as a first boot ROM 16). And a video compression unit for performing a video compression process together with a first SRAM (hereinafter referred to as SRAM) 15 storing a compression algorithm received from a host. The video compression process is a process of compressing video data of YUV 4: 2: 2 format output from the video signal input unit 8 and handing it over to a host, which is controlled by the local bus controller 3.

Compressed remote video data sent from the remote controller or compressed data stored in the hard disk, etc., received from the computer network through the PCI bus (6) and restored by the video compression / restoration processor (13) or video / audio restoration processor (14). The video restoration process is then performed to the video processor 9. The video reconstruction unit 14 includes a video / audio reconstruction processor 14, a second boot ROM 19 for storing a compression algorithm upon initialization, a second DRAM 20 for storing data and video data necessary for executing an algorithm, and compression received from a host. It is composed of a second SRAM 18 storing an algorithm and has the same configuration as the data compression unit. As shown, video reconstruction can simultaneously restore two types of video data streams in the video compression / restore processor 13 and video / audio reconstruction processor 14 to support three-way conferencing. Is controlled by

The audio stage 2 consists of two functional blocks. One is an audio compression / restoration processor 21 which provides MPEG audio restoration and voice compression / restoration function conforming to the ITU-T standard, and the other is an audio codec 22 which provides playback / recording of system audio data. It consists of.

The audio reconstruction function of the audio compression / restore processor 21 receives the MPEG audio data stream from the video / audio reconstruction processor 14, restores the MPEG audio data stream to the audio input / output processor 23, and restores the audio signal to the audio input / output processor 23. It receives the MPEG data stream and outputs it to the speaker. In addition, the voice compression function receives the audio data input from the microphone from the audio input / output processor 23 and transfers the compressed data to the video / audio reconstruction processor 14 by applying a standard voice compression algorithm. The compressed audio data is received from the video / audio restoration processor 14 and restored. A third SRAM 24 storing various data necessary to perform compression / restore and start-up, an EPROM which stores a part for performing a voice compression and decompression algorithm and a startup program for the entire audio compression / restore processor 21. Numeral 25 drives the audio compression / restore processor 21.

The audio codec 22 is a function block for processing the basic sound of the system so that recording and playback can be performed simultaneously by using two channels of DMA during playback and recording. The 8-bit analog data is exchanged with the second data buffer 28 and is controlled by the local bus controller 3.

2A to 2C are flowcharts illustrating a compression / restore process of video data according to the present invention. 2A is a flowchart illustrating a process of outputting input video data without undergoing a compression / restore process. An analog video signal is input (201), and the video signal input unit is converted into a digital YUV signal (202). Data to be converted into a digital YUV signal is input at the video processor (203). The video processor that inputs the digital YUV signal stores it in the frame buffer in the form of 32-bit frame buffer data (204). The stored data is transmitted to the video signal output unit in the form of 32-bit video signal data (205). The video signal output unit performs media DAC conversion on the video signal data (206). The DAC converted data is mixed (207) with graphics data input through the feature connector and output to the monitor (208).

2B is a flowchart illustrating a compression process of input video data. An analog video signal is input (209) and converted into a digital YUV signal by the video signal input (210). The digitalized YUV data is input by the video compression / restore processor and compressed (211), and then transmitted (212) to the first data buffer through a video data bus of the local bus in a DMA transfer scheme. The compressed data transmitted to the first data buffer is stored in the host memory through the PCI bus interface and the PCI bus (213).

2C is a flowchart illustrating a reconstruction process of input video data according to the present invention. Restoring the compressed data received from the hard disk or the remote controller transmits the compressed data 214 stored in the host memory to the two recoverable video restoration processors through the PCI bus, the PCI bus interface, and the first data buffer (215). ). The video reconstruction processor reconstructs the received compressed data into the digital YUV signal (216) and then transmits the received compressed data to the video processor (217). The video processor inputting the digital YUV signal stores the 32-bit frame buffer data type in the frame buffer (218). The stored data is transmitted to the video signal output unit as 32-bit video signal data (219). The video signal output unit performs media DAC conversion on the video signal data (220). The DAC converted data is mixed with graphics data input through the feature connector (221) and output to the monitor (222).

3 is a flowchart illustrating an operation of restoring MPEG audio according to the present invention. Receiving MPEG compressed data from the host (301), the video / audio reconstruction processor separates the video and audio two compressed data (302). The compressed MPEG audio data is transmitted to the audio compression / restore processor (303). The audio compression / restore processor operates an internal MPEG algorithm to restore the compressed MPEG audio data (304) and transmit the compressed MPEG audio data to the audio input / output processor (305). The audio input / output processor converts the restored audio data into an analog signal, amplifies it (306), and outputs it through the speaker (307).

4A and 4B are flowcharts of processing audio data using a standard speech compression / reconstruction algorithm according to the present invention. 4A is a flowchart of processing audio data using a standard speech compression algorithm according to the present invention. In the compression process, the audio input / output processor inputs an analog voice signal from a microphone (401) and generates digital audio data through analog / digital conversion and sampling (402). The generated digital audio data is transmitted to the audio compression / restore processor (403). The audio compression / restore processor compresses the received digital audio data by standard speech compression algorithm (404) and transmits (405) the video / audio reconstruction processor. The video / audio reconstruction processor sends the compressed data to the first data buffer via the local bus (406). The data of the first data buffer is transferred to the host memory via the PCI bus interface and the PCI bus (407).

2B is a flowchart of processing audio data using a standard speech reconstruction algorithm according to the present invention. The decompression process is the reverse of the compression process, in which compressed audio data of the host memory is first received by the video / audio decompression processor via the PCI bus, the PCI bus interface, and the first data buffer (408). The video / audio reconstruction processor that receives the compressed audio data transmits it to the audio compression / restore processor (409). The audio compression / restore processor restores the compressed data using a standard speech decompression algorithm (410) and transmits the compressed data to the audio input / output processor (411). The audio input / output processor that receives the recovered data converts the digital data into an analog signal, amplifies (412), and outputs the same to the speaker (413).

5A and 5B are operational flowcharts of an audio codec according to the present invention. 5A is a flowchart illustrating a recording process of an audio codec according to the present invention. In the recording process, when the analog sound is input from the microphone (501), the analog / digital conversion 502 is performed through the sampling process to generate digital sound data (503). The generated digital sound data stores the digital sound data directly to the host memory via the second data buffer, the first data buffer, the PCI bus interface, and the PCI bus using a DMA transfer scheme through a local bus (504).

5B is a flowchart illustrating a reproduction process of an audio codec according to the present invention. The playback process transfers the digital sound data 505 in the video host memory directly to the audio codec via the PCI bus, PCI bus interface, first data buffer, second data buffer and local bus using the DMA transfer method (506). ). The received digital audio data is subjected to digital / analog conversion and analog signal amplification by the audio codec unit (507) and outputs a sound signal to the connected speaker (508).

As described above, the multimedia integrated structure proposed by the present invention not only supports various standard audio and video methods, but also supports multiple video restoration, bidirectional audio support, and high-speed data movement through local bus and DMA support. It can process information from text and voice to video data, which can be used for advanced / high quality multimedia data processing applications.

Claims (16)

Video stage that inputs analog video signal of still image or video, compresses and restores in real time and outputs the result to output device or transfers to host memory through local bus and peripheral component interconnect bus interface for other applications. An audio stage supporting voice compression / restore and recording / playback functions, a local bus controller responsible for efficient data movement between various functional blocks, a direct memory access controller supporting high-speed data transfer to host memory, And a peripheral component interconnect bus interface stage configured to transmit a signal received through a local bus from the video stage and the audio stage to a host memory and perform a bus master / slave function. The video signal input unit of claim 1, wherein the video terminal converts an analog composite video signal input from an external source into digital data, generates a video signal and a synchronization signal, and transmits the video signal to a video processor and a video compression / restore processor. Receives input data from the signal input unit and the video compression / restore processor or video / audio reconstruction processor to perform data processing such as format conversion and screen size scaling, and to transmit and receive the processed data to the frame buffer in the form of 32-bit frame buffer data. A processor, a frame buffer for converting the 32-bit frame buffer data received from the video processor into a form of 32-bit video signal data to be transmitted to the video signal output unit, and the video signal data and the feature connector received from the frame buffer. barrel A video signal output unit that outputs graphics by overlaying the received graphic data and includes a media digital / analog converter, a feature connector that transmits external graphics to the video signal output unit, and receives from the video signal input unit. And a data compression unit for compressing the brightness and color data of the analog signal to be transmitted to the host, and a data recovery unit for restoring the received compressed remote video data or the compressed data. The video compression / restore processor of claim 2, wherein the data compression unit receives brightness and color data of an analog signal from a video signal input unit, performs a compression / restoration algorithm, and transmits the data to a video processor. A first boot ROM which stores a compression algorithm upon initialization, a first DRAM storing data and video data necessary for performing the algorithm of the video compression / restore processor, and a first SRAM storing a compression algorithm received from a host. Structure of an integrated multimedia data processor, characterized in that made. The video / audio recovery unit of claim 2, wherein the data recovery unit restores the received compressed remote video data or the compressed data to the video processor, and performs a data transfer function between the audio compression / restore unit and the first data buffer. A second boot ROM for storing a compression algorithm upon initialization of the video / audio restoration processor, a second DRAM for storing data and video data necessary for performing the algorithm of the video / audio restoration processor, and a received data from a host. A second multimedia structure for storing the compression algorithm. The audio terminal of claim 1, wherein the audio stage receives an external analog signal, digitally converts and amplifies the analog signal, and transmits the digital signal to the audio compression / restoration processor, and converts and amplifies the digital signal input from the audio compression / restoration processor. Compresses the audio input / output processor and the digital audio data received from the audio input / output processor to the video / audio recovery processor, restores the compressed data received from the video / audio recovery processor, and transmits the compressed data to the audio input / output processor. Perform an audio compression / restore processor, a third SRAM storing various data necessary for performing compression / restore and startup of the audio compression / restore processor, and a voice compression and decompression algorithm of the audio compression / restore processor. Audio Compression / Restore And this pirom a startup program for the entire processor are stored, and performing reproducing / recording of the audio data input from the outside and the structure of the integrated multimedia data processor which is characterized by being a audio codec for inputting and outputting them to the second data buffer. 2. The system of claim 1, wherein the peripheral component interconnect bus interface stage comprises: a first data buffer for relaying data transfer between a data bus scheme inputted and outputted to a peripheral component interconnect bus interface and a local bus to which video is controlled; A peripheral component interconnect bus interface serving as a data relay between the data buffer and the peripheral component interconnect bus, a second data buffer for relaying data transfer between the local bus data bus method and the audio section, and a direct memory access controller. It is composed of a latch that holds the output address temporarily and maintains the previous address even though the address output from the direct memory access controller is changed until the peripheral component interconnect bus interface and the local bus controller read the corresponding data. Tong The structure of the sum multimedia data processor. 2. The structure of claim 1, wherein the local bus controller controls a video processor, a video compression / restore processor, a video / audio reconstruction processor, a first data buffer, a second data buffer and a latch. . After converting the analog video signal into a digital signal at the received video stage, the analog signal is converted into an analog signal, mixed with graphics data, and output to the monitor, and the analog signal is converted into a digital signal at the input video stage. A second step of compressing and storing the compressed video data stored in the host memory, converting the compressed video data stored in the host memory into a digital signal, mixing with graphics data, and outputting the graphic data to a monitor; A fourth step of restoring the compressed data and outputting it to the speaker through an analog conversion and amplification process; a fifth step of compressing the digital audio data at the audio terminal receiving the analog voice signal and storing the compressed audio data in a host memory; Received compressed audio data stored in A sixth step of recovering the compressed data from an audio terminal, converting the analog data into an analog signal, amplifying the amplified signal, and outputting the analog sound signal to a speaker; And converting the digital sound data stored in the host memory into an analog signal in the received audio codec, amplifying the analog signal, and outputting the analog sound signal to the speaker. 9. The method of claim 8, wherein the first step comprises receiving an analog video signal at a video signal input unit, converting the input analog video signal into a digital brightness / color signal, and converting the digital brightness / color signal into a video. Transmitting the digital brightness / color signal to a frame buffer in the form of 32-bit frame buffer data in a video processor inputted to the processor; and storing the data stored in the frame buffer in the form of 32-bit video signal data. Transmitting to the video signal output unit; converting the media digital signal into an analog signal at the input video signal output unit; and mixing the analog converted data with graphics data input through a feature connector. To output to the monitor Method of driving a multimedia data processor according to. 9. The method of claim 8, wherein the second step comprises inputting an analog video signal at a video signal input unit, converting the input analog video signal into a digital brightness / color signal, and converting the digital brightness / color data into a video. Transmitting to the compression / restore processor, compressing the received digital brightness / color data in a video compression / restore processor, and compressing the compressed data in a direct memory access transmission method through a video data bus of a local bus. And transmitting the received compressed data to a host memory through a peripheral component interconnection bus interface and a peripheral component interconnection bus in the first data buffer. Driving method. 10. The method of claim 8, wherein the third step transmits the compressed data stored in the host memory to the reconstructable video reconstruction processor of the two video reconstruction processors through the peripheral component interconnect bus, the peripheral component interconnect bus interface, and the first data buffer. Restoring the input compressed data to a digital brightness / color signal in a video reconstruction processor and transmitting the same to a video processor; and 32-bit frame buffer data form in the video processor inputting the digital brightness / color signal. Storing the data stored in the frame buffer in a raw frame buffer, transferring the data stored in the frame buffer to the video signal output unit as 32-bit video signal data, and converting the media digital / analog signal from the input video signal output unit. And the digital / analo Method of driving a multimedia data processing device, characterized in that consisting of the converted data in the mixing step and the graphics data inputted through the feature connector which outputs on the monitor. 9. The method of claim 8, wherein the fourth step comprises: receiving video expert group compressed data from a host in a video / audio compression processor; and video and audio compressed data in a video / audio reconstruction processor receiving the video expert group compressed data. Dividing the received video expert group audio data into an audio compression / restoration processor, restoring the received moving image expert group audio data by an audio compression / restore processor, and restoring the restored video. And transmitting the expert group audio data to an audio input / output processor, converting the received restored data into an analog signal in the audio input / output processor, amplifying the analog signal, and outputting the same through a speaker. Driving method. 9. The method of claim 8, wherein the fifth step comprises the steps of: inputting an analog audio signal from a microphone in an audio input / output processor, and performing an analog / digital conversion and sampling process in the audio input / output processor inputting the voice signal to perform digital audio data. Generating, transmitting the generated digital audio data to an audio compression / restore processor, compressing the received digital audio data by a standard voice compression algorithm in an audio compression / restore processor, and Transmitting audio data to a video / audio reconstruction processor, transmitting the received compressed audio data to a first data buffer via a local bus in a video / audio reconstruction processor, and transmitting data of the first data buffer to peripherals. Component interconnection bus interface And transmitting the data to the host memory via a peripheral component interconnect bus. 9. The method of claim 8, wherein the sixth step comprises: transmitting compressed audio data of a host memory to a video / audio recovery processor through a peripheral component interconnect bus, a principal component interconnect bus interface, and a first data buffer; Transmitting a piece of compressed audio data from a video / audio recovery processor to an audio compression / restore processor, restoring the compressed data by applying a standard speech reconstruction algorithm in the audio compression / restore processor receiving the compressed audio data; And transmitting the restored audio data to an audio input / output processor, and converting the digital data into an analog signal, amplifying the analog data, and outputting the restored audio data to an speaker. process A drive method. 9. The method of claim 8, wherein the seventh step comprises the steps of: inputting analog sound from a microphone in an audio codec, generating digital sound data through a sampling process and a digital conversion process in the audio codec in which the analog sound is input; Storing the generated digital sound data to a host memory via a second data buffer, a first data buffer, a peripheral component interconnect bus interface, and a peripheral component interconnect bus using a direct memory access transmission method through a local bus. Method of driving a multimedia data processor, characterized in that made. 9. The method of claim 8, wherein the eighth step comprises the process of transferring the digital sound data of the host memory to the peripheral component interconnect bus, the peripheral component interconnect bus interface, the first data buffer, the second data buffer and the local by using an integrated memory access transfer scheme. Transmitting to the audio codec through a bus; and converting the digital audio data The method of driving a multimedia data processor, characterized in that the step of outputting to the speaker through an analog signal amplification process.