KR19980027530A - ECC memory controller of digital video disc system - Google Patents

Abstract

The present invention discloses an ECC memory control apparatus of a DVD (Digital Video Disk) system. An ECC memory control apparatus of a DVD system according to the present invention includes a main memory unit for storing data picked up from an optical disk; An ECC unit for error correction of data stored in the main memory unit; First and second buffer memory units sequentially storing data of the main memory unit alternately with each other, and storing error data positions and error-corrected data of the stored data in the ECC unit; And a memory controller configured to control the main memory and the ECC unit to sequentially access the first and second buffer memory units.

According to the present invention, error correction is performed by alternately using two buffer RAMs separately from the main memory of the DVD system, so that error correction can be performed as independently as possible without affecting functions such as general data transmission and waiting for ECC operation. Reduce losses

Description

Error Correcting Code (ECC) Memory Control Unit in Digital Video Disc Systems

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ECC memory control apparatus of a digital video disk (DVD) system, and more particularly, to a memory control apparatus for calculation inside an ECC (error correcting code) block of a DVD system.

In general, a DVD system processes data based on a data sector and an ECC block. The data structure of each data sector includes 12 rows of 172 bytes as shown in FIG. 1, and the first 6 bytes of the sector are IDs. The end of the data and sectors contain four bytes of Error Detecting Code (EDC). In addition, as shown in FIG. 2, the ECC block of the DVD includes an information field composed of the sectors, a PI (182,172) composed of 10 bytes, and a PO (208,196) composed of 16 rows for correcting errors in the information region data. ). In FIG. 1, a denotes a code word composed of consecutive byte rows of an ECC block, and b denotes a codeword composed of byte columns.

In the ECC block data processing, data picked up from a disk (not shown) is stored in memory through EFM (Eight-Fifteen Modulation) Plus demodulation, and error correction proceeds by reading data of an ECC unit block from the ECC unit. The error corrected data is stored in main memory again. In order to prevent each function from accessing the memory at the same time, the memory controller has a function to control the priority of each function so that when a memory access command is received, data processing is performed according to the priority. However, the ECC unit occupies the largest number of accesses among the memory accesses, and accordingly, a memory controller for more efficient ECC is required.

An object of the present invention is to provide an ECC memory control device which improves data processing speed by reducing a timing loss that must be waited for ECC operation in a DVD system.

1 shows a data sector in a DVD system.

2 shows an ECC block in a DVD system.

3 is a block diagram showing a memory control apparatus of the DVD system according to the present invention.

4 is a timing diagram of the block shown in FIG. 3.

5 shows error correction when the minimum unit buffer RAM is used.

6A and 6B illustrate PI correction data allocated to an address at the time of reading when the minimum unit buffer RAM is used.

7A and 7B illustrate PO correction data allocated to an address at the time of reading when the minimum unit buffer RAM is used.

An ECC memory control apparatus of a DVD system for achieving the above object, comprising: a main memory unit for storing data picked up from an optical disc; An ECC unit for error correction of data stored in the main memory unit; First and second buffer memory units sequentially storing data of the main memory unit alternately with each other, and storing error data positions and error-corrected data of the stored data in the ECC unit; And a memory controller configured to control the main memory and the ECC unit to sequentially access the first and second buffer memory units.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

3 is a block diagram showing an ECC memory control device of a DVD system according to the present invention.

The apparatus shown in FIG. 3 includes a main memory unit 30, a first buffer ram 31, a second buffer ram 32, an ECC unit 33, and a memory controller 34. The memory controller 34 corrects the data stored in the first buffer RAM 31 or the second buffer RAM 32 in the ECC unit 33, and then corrects the data stored in the first buffer RAM 31 or the second buffer RAM 32. The corrected error data is stored in the buffer RAM 31 or the second buffer RAM 32, and the main memory unit 30 accesses one of the first and second buffer RAMs 31 and 32 to perform data processing. Upon completion, error correction is completed for the data stored in the first buffer ram 31 or the second buffer ram 32 by the main memory controller 35 and the ECC unit 33 which output a memory access completion signal infoMEM. After the correction completion signal infoECC is outputted, a buffer RAM controller 36 is provided to output a change signal changeBUF to the main memory controller 35 to switch the buffer RAM to access another buffer RAM. .

Referring to the operation according to the configuration of FIG. 3, when the ECC unit 33 performs error correction on data stored in one of the first and second buffer RAMs 30 and 31, the memory controller 34 may perform main memory. The control unit 30 controls the ECC unit 33 to store data by accessing the other buffer RAM which is not currently accessed. In addition, when the main memory 35 stores the data picked up from the optical disk in the first buffer ram 30 or the second buffer ram 31, the buffer RAM controller 36 may have the second second side of the other side. The buffer RAM 31 and the first buffer RAM 30 are accessed so that the stored data can be error-corrected. Here, the data of the DVD system is composed of 8-bit units, but in order to reduce the number of memory accesses, two bytes are grouped into one word unit to be accessed and processed in word units.

Main memory unit 30 for storing the EFM plus demodulated data and performing data transmission, and the ECC unit 33 for error correction of the data stored in the main memory unit 30 can be independently executed. The 30 and the ECC unit 33 alternately access the first buffer ram 31 and the second buffer ram 32.

First, the ECC unit 33 stores the picked-up data already stored in the second buffer ram 32 while the data picked up from the optical disk not shown are stored in the first buffer ram 31 from the main memory 30. Correct the error. Then, the ECC unit 33 completes error correction on the data stored in the second buffer ram 32, and then stores the corrected error data position and corrected data in the second buffer ram 32 and completes the error correction completion signal. When the infoECC is outputted to the buffer RAM controller 36, the buffer RAM controller 36 flows in an error correction completion signal infoECC output from the ECC controller 33, and sends the buffer switching signal to the main memory controller 35. changBUF). In addition, the main memory controller 35 injects the data error number signal numERROR outputted after the data error correction is completed in the ECC unit 33 and the buffer switching signal changeBUF output from the buffer RAM controller 36. The memory unit 30 is controlled. The main memory unit 30 switches among the first and second buffer RAMs 31 and 32 to complete buffer storage of data for current error correction, and the other buffer RAM, that is, the buffer RAM in which error correction is completed. To store the data for which error correction is completed in the main memory unit 35, and to store the data for error correction in the buffer RAM. The ECC unit 33 flows in the buffer switching signal changeBUF, terminates the access of the buffer RAM currently being accessed among the two buffer RAMs 31 and 32, and accesses the other buffer RAM to perform error correction. When the corresponding data processing stored in one of the two buffer RAMs 31 and 32 accessed by the main memory unit 30 is completed, the main memory controller 35 transmits a memory access completion signal to the buffer RAM controller 36. infoMEM) and the buffer RAM control unit 36 outputs a buffer switching signal changeBUF to the ECC unit 33. The ECC unit 33 receives the buffer switching signal changeBUF and performs the error correction of the other buffer RAM by switching to and accessing the buffer RAM from which the current error correction is completed.

4 is a timing diagram of a control signal output from each block illustrated in FIG. 3.

As shown in FIG. 4, when the infoMEM signal and the infoECC signal flow into the buffer RAM controller 36, the buffer RAM controller 36 outputs a changeBUF signal, and the ECC unit 33 that receives the changeBUF signal outputs a numERROR signal. . In FIG. 4, c denotes the time point at which data has been written to the currently accessed buffer RAM from the main memory unit 30 after error correction is finished, and d represents the buffer accessed from the main memory unit 30. FIG. After writing to the RAM, this indicates the time when error correction of data stored in the buffer RAM accessed by the ECC unit 33 is completed.

If the level of the infoMEM signal and the infofECC signal is 1, the level of the changeBUF signal of the buffer RAM control unit 36 becomes 1, and the first and second buffers 31 and 32 are connected to the main memory unit 30 and the ECC unit 33. ) Alternately access each other.

Here, the minimum size of one of the first and second buffer RAMs 31 and 32 is 252 words, 0 to 207 words are main data areas, and up to 208 to 239 words are stored corrected data and error positions. Is a correction data area, and the last 240 to 252 words are used as the final flag area.

The main data area stores two rows of data of 182 words in PI correction of an ECC block, or stores two rows of data of 208 words in PO correction of an ECC block. The correction data area can store 32 words using 8 bits of corrected data and 8 bits of the position of the data as one word. This is the size of storing 2 codewords at 16 maximum correction capabilities when PO erasure correction. Since the flag area requires 208 bits of flag when the PI correction is completed, an area of 208 bits / 16, that is, 13 words is required.

5 shows error correction when the minimum unit buffer RAM is used.

In FIG. 5, error correction is performed for the first codeword and the second codeword during the period of the changeBUF signal.

6A and 6B illustrate PI correction data allocated to an address at the time of reading when using the minimum unit buffer RAM. More specifically, FIG. 6A shows data corresponding to the address at the time of reading the first codeword and FIG. 6B is the second time. The data corresponding to the address at the codeword read is shown.

7A and 7B illustrate PO correction data allocated to an address at the time of reading when the minimum unit buffer RAM is used. More specifically, FIG. 7A shows error correction data corresponding to the address at the time of reading the first codeword. Shows error correction data corresponding to the address at the second codeword read.

As shown in Figs. 6A to 7B, in the PI correction, when one word is read, the lower one byte becomes a contiguous code, so addresses 0 through 90 read the data D0 through D181 of the first codeword. Addresses 91 to 181 read the data of the second codeword (D0 'to D181'). When PO is corrected, if one word is read, the data of the first codeword and the second codeword are simultaneously read by 8 bits. When correcting the first codeword, error correction is performed with data D0 to D207 which are upper bytes among data read one word at a time. In the PI and PO corrections, the correction results for the first codeword are stored in order from address 208, and the correction results for the second codeword are stored in order from address 224.

As described above, according to the present invention, error correction is performed by alternately using two buffer RAMs separately from the main memory of the DVD system, so that error correction can be performed as independently as possible without affecting functions such as general data transfer. Reduces timing loss that must be waited upon.

Claims (4)

A main memory unit for storing the data picked up from the optical disc and storing the last error corrected data using the error position and data stored as a result of the error correction; An ECC unit for error correction of data stored in the main memory unit; First and second buffer memory units which sequentially store data in the main memory unit alternately with each other and store error data positions and error corrected data processed by the ECC unit; And a memory control unit for controlling the main memory unit and the ECC unit to sequentially access the first and second buffer memory units. ECC memory control apparatus of the DVD system, characterized in that the data storage in the main memory unit and the first and second buffer memory unit is processed in units of words. The memory controller injects a memory access completion signal and an error correction completion signal from the ECC unit, outputs a buffer switching signal and the memory access completion signal, injects a buffer RAM switching signal, and accesses the buffer RAM and the main circuit. An ECC memory control apparatus for a DVD system, comprising: a main memory control unit for simultaneously switching a buffer RAM accessed by the memory unit. The apparatus of claim 1, wherein the minimum size of each of the first and second buffer RAMs is at least 252 words.