KR19980025486A - Semiconductor memory device to secure write recovery time - Google Patents

Abstract

The present invention relates to a semiconductor memory device, and an object of the present invention is to provide a semiconductor memory device that can be freely adjusted in the light recovery time and is easy in design. According to the technical idea for achieving the above object, the semiconductor memory device for ensuring the write recovery time includes a pulse generator for generating a pulse by detecting a level change of the external write enable signal input from the outside; A first logic having a first input terminal for inputting an external address and a second input terminal for inputting the pulse and providing a word line enable signal for activating a word line connected to a memory cell to be selected; A circuit is provided.

Description

Semiconductor memory device to secure write recovery time

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device required to secure a write recovery time.

In a conventional semiconductor memory device, write recovery time is a very important field, and many improvement methods have been proposed. However, there are a number of problems in using the memory device directly. Referring to FIG. 1 showing such a problem, the write enable signal Is a method of using a delay chain to generate a pulse through the pulse generator 104 and to disable the pulse after the bit line to be written is precharged. In the figure, reference numeral 101 denotes an address buffer for outputting an internal address by inputting an external address, and reference numeral 103 denotes a predecoder 103 for outputting a predecoded signal in response to the internal address. It is quite difficult to adjust the pulse width because the activation operation of the word line through this configuration is a different logical path from the bit line precharge signal and the pulse. In addition, if the pulse width is long enough to safely compensate for the light recovery time, the lead, that is, the lead, TAC-TWR time, becomes considerably longer after the write, which is slower than the normal access time TAC.

2 is a block diagram of circuits required to secure a light recovery time according to another embodiment of the prior art.

2, the data line pair SDL, Is precharged, the data line pair SDL, The next cell is designated by inputting a signal output through the NAND gate 107 that takes a signal of? And an internal address output through the address buffer 106 as an input. This means that all data line pairs SDL, Since a decoding circuit for inputting a signal of i.e., a predecoder 108 and a main decoder 109 is required, a large area is occupied in the design of a memory device, and a signal line becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can freely adjust the write recovery time and is easy in design.

Another object of the present invention is to provide a semiconductor memory device capable of securing a write recovery time.

Another object of the present invention is to provide a semiconductor memory device capable of increasing chip reliability.

1A and 1B are block diagrams illustrating a circuit required to secure a light recovery time according to an embodiment of the prior art.

2 is a block diagram illustrating a circuit required to secure a light recovery time according to an embodiment of the present invention.

3 is a timing diagram for FIG. 2.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

2 is a block diagram illustrating a circuit required to secure a write recovery time according to an exemplary embodiment of the present invention.

Referring to Fig. 2, an address buffer 201 for outputting an internal address by inputting an external address, and a signal pre-decoded by inputting this internal address. A predecoder 202 for outputting the signal and the external write enable signal; A write enable buffer 203 for outputting the internal write enable signal? WE as an input and a bitline precharge circuit 204 for outputting the bitline precharge signal BLPR in response to the internal write enable signal? WE. ), A noah gate 205 for outputting a logically combined signal ψ TWR by inputting the bit line precharge signal BLPR and the internal write enable signal ψWE; And a NOR gate 206 which outputs a signal WL for activating a word line by inputting the signal? TWR. This noble gate acts as the main decoder compared to the prior art.

3 is an output timing diagram for FIG. 2.

Referring to FIGS. 3 and 2, the read operation of the memory cell is performed. First, the signal ψ TWR is maintained at a low level, and the external write enable signal is used during the write operation. Only when is transitioned from the low level to the high level, this signal ψ TWR is pulsed.

Referring to FIG. 3, when the memory cell M1 is written to the memory cell M1, the signal? TWR is in a low level, and the word line of the memory cell M1 is normally enabled to perform the write operation. At this time, the external light enable signal Transitions from the low level state to the high level state, the write operation is terminated. When the data of the memory cell M2 is read, the word line of the memory cell M1 is disabled and the word line of the memory cell M2 is enabled. Here, conventionally, the external address address for selecting the memory cell M2 is the external write enable signal. In contrast, when the first transition is performed, the word line of the memory cell M2 is enabled before the bit line is precharged, and the write operation is performed in the memory cell M2 for reading. In order to prevent this, in the present invention, the word line is disabled in response to a level change of the internal write enable signal? WE, that is, a transition from a high level to a low level. At this time, the write operation is sufficiently made. Therefore, since the word line of the memory cell M2 is also disabled, the write operation is not performed in the memory cell M2. Thereafter, the bit line precharge enable signal BLPR is enabled to precharge the bit line, and also disable the signal ψ TWR. The signal, which is a normal address decoding output as the signal ψ TWR transitions to a disabled state, that is, a low level state The word line of the memory cell M2 is enabled by the input of. Here, the time for the signal? TWR to be disabled can be adjusted in various ways, and the access time TAC-TER from the end of the write operation to the start point of the read operation can be made the same as the address access time TAC.

As described above, the present invention has an advantage of sufficiently securing the margin of the light recovery time. In addition, the present invention has the advantage that it is possible to improve the characteristics of the time taken until the post-write lead. In addition, the present invention has the advantage that can be designed without increasing the chip area.

Claims (5)

A semiconductor memory device for securing a write recovery time: A pulse generator for detecting a level change of an external light enable signal input from the outside and generating a pulse; A first logic having a first input terminal for inputting an external address and a second input terminal for inputting the pulse and providing a word line enable signal for activating a word line connected to a memory cell to be selected; A semiconductor memory device comprising a circuit. The method of claim 1, wherein the pulse generator A write enable buffer for providing an internal write enable signal inverted in response to the external write enable signal, a bit line precharge circuit for providing a bit line precharge signal in response to the internal write enable signal; And a logic gate configured to input the internal write enable signal and the bit line precharge signal to output the pulse. The semiconductor memory device of claim 2, wherein the logic gate is a noble gate. The semiconductor memory device of claim 1, wherein the level change of the external write enable signal is a change from a low level to a high level. The semiconductor memory device of claim 1, wherein the first logic circuit is a non-gate.