KR100439046B1 - Auto precharge circuit in a semiconductor device - Google Patents

Abstract

The present invention relates to an auto precharge circuit of a semiconductor device, comprising: a column burst end signal generator for generating a column burst operation end control signal according to a column burst signal, and a row address strobe minimum time for which the column burst operation end signal is set; The auto precharge control signal and the auto precharge control signal for generating the auto precharge control signal immediately after the same time and for generating the auto precharge control signal after a predetermined time delay when it is shorter than the set row address strobe minimum time. There is provided an auto precharge circuit for a semiconductor device including an address strobe generator for generating an auto precharge signal in accordance with a precharge control signal.

Description

Auto precharge circuit in a semiconductor device

The present invention relates to an auto precharge circuit of a semiconductor device which automatically performs a precharge command when an external precharge command is not given. In particular, the present invention does not lose data that has been re-stored through sensing and restoring after row address activation. The present invention relates to an auto precharge circuit of a semiconductor device capable of being able to endure without satisfactory or satisfying a row address strobe minum time (tRAS) specification that guarantees time for data written upon writing to be sufficiently stored in a cell.

tRAS is RAS active time and it means the time from RAS active until read or write operation. The RAS active command decodes a row address to select one or more memory blocks in that bank and activates one word line in each memory block indicated by the decoded address. The activated word line enters the pass transistor of the DRAM cell into saturation mode to transfer the potential of the data of the storage node of the capacitor to the bit line. These data transfers cause charge sharing due to the difference between the capacitance of the bit line and the cell capacitor. In the bit line, the existence of data is represented by the potential value of which the force is very small from the potential that the original straw had. When this phenomenon is sufficiently completed, the bit line sense amplifier group starts to operate, and as a result, the fine signal of the bit line is stored in the capacitor through the cell's storage node with an amplified value of sufficient vdd level. This series of processes is called sensing and restoring. It is important to ensure that the resaved data is not lost for a long time, but the semiconductor specification does not allow for a long time.

FIG. 1 is a timing diagram for explaining a relationship between a column address strobe minimum time and an auto precharge start point according to a burst length in SDRAM.

In FIG. 1, when tCK (System clock cycle time) is set to 5ns, the column address strobe minimum time (tRASmim) specification is 35ns (7 clocks) and tRCD (RAS to CAS delay) is 3 clocks. In conventional circuits, the auto-precharge operating point is the clock immediately after the burst operation. As shown in FIG. 1, when tCK is set to 5 ns, tRASmim in BL4 is 7 clocks while BL2 and BL1 become 2 and 1 clocks, respectively. That is, BL4 starts the auto precharge operation after the fourth burst signal, BL2 starts the auto precharge operation after the second burst signal, and BL1 starts the auto precharge operation after the first burst signal. Therefore, BL4 performs auto precharge after the defined tRASmim time, but BL2 and BL1 perform auto precharge before the defined tRASmim time, which may cause an error in the data write operation.

A conventional auto precharge operation will be described with reference to FIGS. 2 to 4.

2 is a block diagram of a conventional auto precharge circuit.

When the external command is received by the combination of the RAS, CAS, and WE signals, the command decoder 10 generates a row active start signal rowatv6 and a column access (read and write) start signal casatv6.

The row active start signal rowatv6 is buffered by the row address strobe separator 20 and then input to the row address strobe generator 30 according to an external active command ACT. The row address strobe generator 30 generates a row bank separation signal rasatv according to an external command.

According to the WA (Write with autoprecharge) command, the column access start signal casatv6 is activated in the column address active signal generator 40, and a column start signal casatv8 for the corresponding column is generated in the generator 40. The column address strobe generator 50 generates a column address strobe signal ca8 to disable the column when another bank is reactivated or the burst operation ends.

The column burst signal generator 70 generates a column burst signal ybst during the burst write period according to the column access start signal casatv6. The column burst end signal generator 80 generates a column burst operation end signal ybnd-autopcg according to the column burst signal ybst and the clock signal clkt4.

The auto precharge control signal generator 60 includes a column start signal casatv8 from the column address strobe active signal generator 40, a column address strobe signal ca8 from the column address strobe generator 50 and a column burst end signal generator. The auto precharge control signal autopcg is generated in accordance with the thermal burst operation end signal ybnd_autopcg from 80. The row address strobe generator 30 generates an auto precharge signal raspcg for the auto precharge operation according to the auto precharge control signal autopcg. The auto precharge operation is started according to the auto precharge signal.

3 is a detailed circuit diagram of the column burst termination signal generator of FIG. 1.

The column burst signal ybst is inverted by the inversion gate G1, and the transistors Q1 and Q2 are turned off or off by the inverted signal. In addition, the transistor Q3 is turned on or off according to the clock signal clkt4_c, and the power up signal pwrup is inverted by the inversion gate G2. The transistor Q4 is turned on or off by the inverted power-up signal pwrupb, and the control signal ybst_1 is generated according to the operations of the transistors Q1, Q2, and Q3. The inverting gates G3 and G4 are connected to have a latch function, and latch the control signal ybst_1 according to the operation of the transistor Q4. The control signal ybst_1 is directly input to one input terminal of the NOR gate G9, while the NOA gate G9 is passed through the latch and inverting gates G5, G6, G7 and G8 composed of the inverting gates G3 and G4. It is input to the other input terminal of). The output of the NOR gate G9 is output through the inversion gates G10 and G11, and the output of the inversion gate G11 becomes the burst operation end signal ybnd_autopcg.

That is, the column burst end signal generator of FIG. 3 has the row burst signal enabled by the burst length by the column start signal casatv6 generated by the row start command, and then goes low again when the burst ends. ), The control signal (ybst_1) is set low at the rising edge of the next clock (the rising edge of clkt4_c). Therefore, the burst operation end signal ybnd_autopcg becomes a low pulse type.

FIG. 4 is a detailed circuit diagram of the auto precharge signal generator of FIG. 1.

The row address strobe active flag signal casatvfls and the auto precharge flag signal ab <10> are logically combined by the NAND gate G12. Transistor Q5 is turned on or off in response to the output of NAND gate G12, and transistor Q6 is turned on or off in accordance with power-up signal pwrup. The operation of the transistor Q7 is controlled by the column start signal casatv8, and the operation of the transistor Q8 is controlled by the signal a <10>. The potentials of the connection nodes a of the transistors Q6 and Q7 are latched in the latches composed of the inverting gates G13 and G14. The output aa of the latch is input to one input terminal ad of the NAND gate G20 through the inverting gates G15, G16, G17, and G18. In addition, the burst operation end signal ybnd_autopcg and a signal ca8 indicating that a read or write command has been entered into another bank are logically combined by the NAND gate G19, and then the other input terminal af of the NAND gate G20. Is entered. The output of the NAND gate G20 is inverted by the inversion gate G21, and the output of the inversion gate G21 becomes an auto precharge control signal autopcg.

That is, when the precharge command is externally performed, precharging is performed by the column address strobe precharge signal raspcg of FIG. 2, and when the precharge is performed by the internal command, address 10 is low, so ab <10> is high. And a <10> goes low and node ab goes low. In addition, the node a becomes high so that the auto precharge signal does not appear. Of course, initially, the power-up signal pwrup goes low and then goes high. When the power-up signal pwrup is low, the transistor Q6 is on. It goes high.

However, when auto precharge is performed, node a is low and node ad is high because address 10 (a <10>), which is an auto precharge flag signal, is high and column start signal casatv8 is high. It becomes a state. Therefore, when the node af becomes high, the auto precharge operation starts.

As described above, in the conventional auto precharge circuit, the auto precharge signal is generated at the next clock after the burst operation ends after a write with autopcg (WA) command. As a result, as shown in FIG. 1, there is a problem in that the row access strobe minimum time tRASmim cannot be guaranteed at the burst lengths BL1 and BL2.

Accordingly, an object of the present invention is to provide an auto precharge circuit of a semiconductor device capable of solving the above-described problem by preventing precharging from being performed when the row access strobe minimum time is not satisfied.

1 is a timing diagram for explaining a relationship between a column address strobe activation minimum time and an auto precharge start point.

Fig. 2 is a block diagram for explaining the operation of a conventional auto precharge circuit.

3 is a detailed circuit diagram of the column burst termination signal generator of FIG.

FIG. 4 is a detailed circuit diagram of the auto precharge signal generator of FIG. 2. FIG.

5 is a block diagram illustrating an auto precharge operation according to the present invention;

FIG. 6 is a detailed circuit diagram of the auto precharge control signal of FIG. 5. FIG.

7 is a detailed circuit diagram of a delay unit of FIG. 6.

8 is a timing diagram for explaining an auto precharge operation of a semiconductor device according to the present invention;

<Description of the symbols for the main parts of the drawings>

10: command decoder 20: row address strobe separator

30: row address strobe generator

40: column address strobe enable signal generator

50: column address strobe generator

60: Auto-Precharge Signal Generator

70: thermal burst signal generator 80: thermal burst end signal generator

90: auto precharge control signal 100: delay unit

An autoprecharge circuit of a semiconductor device according to the present invention comprises a command decoder for generating a row active start signal and a column access start signal;

Row address strobe separator for buffering the row active start signal according to an external active command:

A column address strobe activation signal generator for activating the column access start signal to generate a column address strobe activation signal for the corresponding column according to a write with autoprecharge (WA) command;

A column address strobe generator configured to generate a column address strobe signal to disable a corresponding column when another bank is reactivated or a burst operation ends according to the column address strobe activation signal;

A thermal burst signal generator for generating a thermal burst signal during a burst write period in accordance with the thermal access start signal;

A thermal burst end signal generator for generating a thermal burst end signal according to the thermal burst signal and a clock signal;

An auto precharge enable signal generator for generating an auto precharge enable signal according to the column address strobe activation signal, the column address strobe signal, and the column burst end signal;

Generate an auto precharge control signal according to the auto precharge enable signal and a sensing generation signal that causes the bit line sense amplifier to be amplified after charge sharing during an active command, but the burst operation is shorter than the set row address strobe minimum time. An auto precharge control signal for delaying until the row address minimum time is satisfied and then generating an auto precharge control signal;

And an address strobe generator for generating a row bank separation signal according to an external command and the buffered row active start signal and for generating an auto precharge signal according to the auto precharge control signal.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 is a block diagram of an auto precharge circuit of a semiconductor device according to the present invention.

Accepting an external command by a combination of the RAS, CAS, and WE signals causes the command decoder 10 to generate a row active start signal rowatv6 and a column access (read and write) start signal casatv6 as shown in FIG. Serve

The row active start signal rowatv6 is buffered by the row address strobe separator 20 and then input to the row address strobe generator 30 according to an external active command ACT. In response to an external command, the row address strobe generator 30 generates a row bank division signal rasatv as shown in FIG. 8.

According to the WA (Write with autoprecharge) command, the column access start signal casatv6 is activated in the column address strobe activation signal generator 40, and in this generator 40, the column start signal casatv8 for the corresponding column as shown in FIG. ) Is generated. The column address strobe generator 50 generates column address strobe signals ca8 <0> to <2> as shown in FIG. 8 to disable the corresponding column when another bank is activated again or the burst operation ends. do.

The column burst signal generator 70 generates a column burst signal ybst as shown in FIG. 8 during the burst write period in accordance with the column start signal casatv6. The column burst termination signal generator 80 generates a column burst operation termination signal ybnd-autopcg according to the column burst signal ybst and the clock signal clkt4 as shown in FIG. 8.

The auto precharge enable signal generator 60A (which has the same configuration as the auto precharge control signal generator in FIG. 2) is the column address strobe activation signal casatv8 from the column address strobe activation signal generator 40, the column address strobe signal generator The auto precharge enable signal ap_en is generated in accordance with the column address strobe signal ca8 from 50 and the column burst operation end signal ybnd_autopcg from the column burst end signal generator 80. The auto-pre charge control signal 90 as shown in FIG. 8 allows the bit line sense amplifier BLSA to be amplified after charge sharing during the auto precharge enable signal ap_en and active command ACT. If the burst length does not satisfy the row address strobe minimum time tRASmim as shown in BL1 or BL2 of FIG. 1, the auto precharge control signal autopcg is generated according to the sensing generation signal sg. After the delay, the auto precharge control signal autopcg is generated. If the row address strobe minimum time is satisfied, the auto precharge control signal autopcg is generated immediately after the burst operation is completed. The row address strobe generator 30 generates an auto precharge signal raspcg for the auto precharge operation according to the auto precharge control signal autopcg. The auto precharge operation is started according to the auto precharge signal.

FIG. 6 is a detailed circuit diagram of the auto precharge control signal of FIG. 5 and will be described with reference to FIG. 8.

The transistor Q9 or Q10 is operated according to the auto precharge enable signal ap_en. The potentials of the junction node node1 of the transistors Q9 and Q10 are latched in the latches composed of the inverting gates G22 and G23 and become one input of the NAND gate G25. The sensing generation signal ag is inverted by the inversion gate G24 and then delayed for a predetermined time in the delay unit 100. The output node2 of the delay unit 100 is input to another input terminal of the NAND gate G25. The output of the NAND gate G25 is directly input to one input terminal of the NAND gate G31 while being input to the other input terminal of the inverted gate G31 via the inversion gates G26, G27, G28, G29, and G30. . The output of the inverting gate G31 becomes an auto precharge control signal autopcg signal.

That is, when the auto precharge enable signal ap_en is in a high state, the node node1 is in a low state, and thus the auto precharge control signal autopcg is not immediately activated. The auto precharge control signal autopcg is activated when the sensing generation signal sg is delayed for a predetermined time in the delay unit 100 and the node node2 is turned low.

FIG. 7 is a detailed circuit diagram illustrating the delay unit of FIG. 6. It will be described in detail as follows.

As shown in FIG. 7, the delay unit includes first to eighth delay blocks 100A to 100G connected in series. The delay time dly is determined by the resistance element and the MOS capacitor, and the switching elements SW1 to SW8 may be appropriately adjusted. The delayed signal is applied to the NAND gate G25 of FIG. 6 through the NAND gate G32. Supplied to the generator 30.

As described above, according to the present invention, the time margin problem can be solved by ensuring the minimum row address time even when there is a need to perform auto precharging after a short burst operation.

Claims (5)

A command decoder for generating a row active start signal and a column access start signal; Row address strobe separator for buffering the row active start signal according to an external active command: A column address strobe activation signal generator for activating the column access start signal to generate a column address strobe activation signal for the corresponding column according to a write with autoprecharge (WA) command; A column address strobe generator configured to generate a column address strobe signal to disable a corresponding column when another bank is reactivated or a burst operation ends according to the column address strobe activation signal; A thermal burst signal generator for generating a thermal burst signal during a burst write period in accordance with the thermal access start signal; A thermal burst end signal generator for generating a thermal burst end signal according to the thermal burst signal and a clock signal; An auto precharge enable signal generator for generating an auto precharge enable signal according to the column address strobe activation signal, the column address strobe signal, and the column burst operation end signal; Generate an auto precharge control signal according to the auto precharge enable signal and a sensing generation signal that causes the bit line sense amplifier to be amplified after charge sharing during an active command, but the burst operation is shorter than the set row address strobe minimum time. An auto precharge control signal for delaying until the row address minimum time is satisfied and then generating an auto precharge control signal; And a row address strobe generator configured to generate a row bank separation signal according to an external command and the buffered row active start signal and to generate an auto precharge signal according to the auto precharge control signal. Auto precharge circuit. The method of claim 1, The auto precharge control signal includes: latch means for latching a logic signal generated according to an auto precharge enable control signal; Delay means for delaying the sensing generation signal for a predetermined time; First logic means for outputting data latched to the latch means in accordance with the output of the delay means; Delay and inversion means for delaying and inverting the output of the logic means; And second logic means for outputting the output of said first logic means in accordance with the output of said delay and inversion means to generate an auto-precharge control signal. The method of claim 2, And the delay means comprises a plurality of delay circuits connected in series. The method of claim 2, And each of said first and second logic means comprises a NAND gate. delete