KR19980020269A - Interleaving and Deinterleaving Address Generators - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

The present invention relates to an interleaving and deinterleaving address generator.

I. The technical problem to be solved by the invention

Simple configuration of the interleaving and deinterleaving address generator of the GSM terminal.

All. Summary of Solution of the Invention

The interleaving write and deinterleaving read address generators generate burst addresses that repeat sequential increments from 1 burst to 8 bursts, with 15 bits increasing from 4 to 5 bursts and 17 bits changing from 8 to 1 bursts. When the other burst increases, a bit address of which 16 bits is decreased is generated, and the burst address and the bit address are combined to generate an interleaving write and deinterleaving read address. The interleaving read and deinterleaving write address generator sequentially increases from 1 burst to 8 bursts, generates a burst address that repeats the increase again, and sequentially increases the bits from 0 to 113 as the burst increases. A bit address is generated to combine the burst address and the bit address to generate an interleaving write and deinterleaving read address.

la. Important uses of the invention

It can be used for interleaver and deinterleaver of GSM terminal.

Description

Interleaving and Deinterleaving Address Generators

The present invention relates to a Global System for Mobile communication (GSM), and more particularly to an interleaving and deinterleaving address generator for full rate speech of a GSM terminal.

In the GSM regulation, a rule for performing interleaving and deinterleaving is defined as a relationship between an order of an original signal and an order of interleaving and outputting an original signal. The relationship between the order of the original signal and the order of interleaving and outputting the original signal is expressed by Equation 1 below.

I (B, i) represents the order of data interleaved and output. And c (n, k) represents the order of one data input to be interleaved.

On the other hand, the relationship between B and n in Equation 1 is defined in Equation 2 below.

B in Equation 2 represents a burst of data to be output. In Equation 2, n represents an input data block. k represents the bit position in the data block to be input. In the case of the full rate speech, one data block includes 456 bits. Accordingly, k may represent bit positions from 0 to 455.

Here, it will be described in detail what value the B has according to the B ₀ , n, k. Initially, the B ₀ is 0, and the n and k are also 0. The B ₀ or n increases as the input data block increases, and the k increases as the bit of the data block increases. When the first data block c (0, k) is input, the B value increases sequentially as k increases sequentially. However, when k becomes 8, the B value becomes 0 again by mod (8), and again, the B value increases from 0 as the k value increases. Accordingly, when c (0, k) is input to the first data block, B is output in the order of 0,1,2 to 5,6,7,0,1 to 6,7,0,1 to.

On the other hand, Equation 3 defines the relationship between j and k.

J generated according to Equation 3 multiplies 49k by 2 when 49k is less than 57. The quotient generated by dividing the value of kmod (8) by 4 is obtained by adding the product of the product.

On the other hand, if the 49K is greater than 57, it goes back to zero. J generated according to Equation 3 is 0,98,82,66,51 to.

As a result, the order of data input sequentially is c (n, 0) ⇒ c (n-1,228) ⇒ c (n, 64) ⇒ c (n-1,292) ⇒ c (n, 128) ⇒ c (n- 1,356) ⇒ c (n, 192)-. N represents the current data block, and n-1 represents the previous data block.

As shown in the table in order of outputting data sequentially input as described above is FIG. The horizontal of FIG. 1 shows eight bursts b0 to b7. In addition, 0 to 112 bits are shown in which the vertical indicates the output bits. The first bit c (0,0) of the first input data c (0, k) shown in FIG. 1 is located at the first bit of the first burst, i (B0,0), at the time of output. The next bit c (0,1) is located at i (B1,98) at output. C (0,2) is i (B2,82), c (0,3) is i (B3,66), c (0,4) is i (B4,51), c (0,5) Is i (B5,35), c (0,6) is i (B6,19), c (0,7) is i (B7,3), c (0,8) is i (B1,100) to Located in In this manner, the first input data i (0, k) is evenly distributed over eight bursts. Meanwhile, the first bit c (1,0) of the second input data c (1, k) is located at the fifth bit of the first burst, that is, I (B4,0) at the time of output. The next bit c (1,1) is located at i (B5,98) at output. C (1,2) is i (B6,82), c (1,3) is i (B7,66), c (1,4) is i (B0,51), c (1,5) Is i (B1,35), c (1,6) is i (B2,19), c (1,7) is i (B3,3), c (1,8) is i (B4,100) to Located in As described above, the second input data i (1, k) starts spreading from the fifth burst and spreads evenly among the eight bursts.

On the other hand, when receiving and deinterleaving the data interleaved and spread as described above, original data can be obtained by using the above Equations 1 to 3 inversely.

An interleaving and deinterleaving apparatus is conventionally used to convert, interleave, and deinterleave the output order of input data.

The conventional interleaving and deinterleaving apparatus includes a hardware apparatus corresponding to Equations 1 to 3 to perform interleaving and deinterleaving. However, as the equations 1 to 3 are transferred to the hardware, the interleaving to the deinterleaving device have a very large hardware. This is because a plurality of multipliers and dividers are required to implement the above Equations 1 to 3 in hardware, because the multipliers and dividers are generally larger in volume than other calculators.

As described above, the conventional interleaving and deinterleaving apparatus has a large hardware size, thereby increasing the cost and increasing the volume of the apparatus.

An object of the present invention is to provide an interleaving and deinterleaving apparatus for performing interleaving and deinterleaving with simple hardware.

1 shows the output order of interleaved data.

2 illustrates a memory map in which data interleaved and output is stored in an output order.

3 is a block diagram of an interleaving apparatus according to a preferred embodiment of the present invention.

4 is a block diagram of a deinterleaving apparatus according to a preferred embodiment of the present invention.

5 illustrates an interleaving write and deinterleaving read address generator according to a preferred embodiment of the present invention.

6 is an operation timing diagram of FIG. 5.

7 illustrates an interleaving read and deinterleaving write address generator according to a preferred embodiment of the present invention.

8 is an operation timing diagram of FIG. 6.

The interleaving write and deinterleaving read address generators for achieving the above-mentioned objects generate burst addresses that repeat sequential increments from one burst to eight bursts, and 15 bits for four to five bursts, and eight to one. By generating a bit address that decreases 17 bits when changing to a burst and 16 bits when increasing another burst, the interleaved write and deinterleaving read addresses are generated by combining the burst address and the bit address. The interleaving read and deinterleaving write address generator sequentially increases from 1 burst to 8 bursts, generates a burst address that repeats the increase again, and sequentially increases the bits from 0 to 113 as the burst increases. A bit address is generated to combine the burst address and the bit address to generate an interleaving write and deinterleaving read address.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description and the annexed drawings, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

2 illustrates a memory map of a memory storing data to be interleaved and output according to an exemplary embodiment of the present invention. The memory map includes first input data c (0.k) spread in 1 to 8 bursts and second input data c (1, k) spread in eight bursts according to Equation 1 to Formula 3 above. The second input data c (1, k) diffused in 5 to 8 bursts is shown schematically. The hatched portion shown in FIG. 2, that is, 113 bits in 101 bits of each burst is an area not used in the present invention. In the memory map shown in FIG. 2, the bit of the input data increases and the change of the output position will be described in more detail. Table 1 shows the output position change of the first eight bits of the first input data c (0.k). In the burst conversion values shown in Table 1, since all bursts are eight, the value of change from 7 bursts to 0 bursts is set to 1.

Input data Output burst Output bit Burst change Bit change c (0,0) ⇒ c (0,1) 0 ⇒ 1 0 ⇒ 98 One (0 + 114) -16 c (0,1) ⇒ c (0,2) 1 ⇒ 2 98 ⇒ 82 One -16 c (0,2) ⇒ c (0,3) 2 ⇒ 3 82 ⇒ 66 One -16 c (0,3) ⇒ c (0,4) 3 ⇒ 4 66 ⇒ 51 One -15 c (0.4) ⇒ c (0,5) 4 ⇒ 5 51 ⇒ 33 One -16 c (0,5) ⇒ c (0,6) 5 ⇒ 6 33 ⇒ 19 One -16 c (0,6) ⇒ c (0,7) 6 ⇒ 7 19 ⇒ 3 One -16 c (0,7) ⇒ c (0,8) 7 ⇒ 0 3 ⇒ 100 One (3 + 114) -17

As shown in Table 1, when the burst changes from 0 to 1, 1 to 2, 2 to 3, 4 to 5, 5 to 6, and 6 to 7, 16 bits are changed. When the burst changes from 3 to 4, 15 bits change. When the burst changes from 7 to 0, 17 bits change. The bit change is reduced to 15, 16, or 17 in the current number of bits. When the current number of bits is smaller than the number to be reduced, it is changed to the value after adding 114 to the current value. The change in the number of bits as described above is constant as the burst changes, as shown in FIG.

As described above, it can be seen that the output order of the interleaved input data according to the GSM regulation has the above-described constant format. Accordingly, the present invention implements the interleaving and deinterleaving apparatus based on the above-described form. The interleaving apparatus receives the transmission data and stores the received data in the interleaving RAM. The interleaving apparatus provides the write address as described above so that the data is written in the form as described above. The read data written as described above is sequentially read from the first address to be provided to the transmitting apparatus. The deinterleaving apparatus receives the received data, writes the received data to the deinterleaving RAM in the received order, and reads the written data to the same address as the write address when interleaving the raw data.

3 is a block diagram of the interleaving apparatus as described above. The interleaving write address generator 10 of the interleaving apparatus generates a write address for writing the transmission data to the interleave RAM 16 in the data output order as shown in FIG. The generated write address is provided to the multiplexer 14. Meanwhile, the read address generator 12 generates a read address for reading data stored in the interleaved RAM 16. The read address is provided to the multiplexer 14. The multiplex 14 outputs any one of a read address and a write address input according to the selection signal IL-WR provided by the control unit of the GSM terminal to provide to the interleaved RAM 16. The interleaved RAM 16 receives the write address, writes transmission data to a position corresponding to the write address, and reads a read address to read data recorded at a position corresponding to the read address.

Meanwhile, FIG. 4 illustrates a deinterleaving apparatus according to a preferred embodiment of the present invention for deinterleaving when receiving interleaved data. The write address generator 20 of the deinterleaving apparatus generates a write address to be written on the deinterleave RAM 18 in the order of inputted transmission data. The write address is provided to the multiplexer 24. The deinterleaving read address generator 22 generates a read address of the same address as the write address at the time of interleaving in order to recover the received data written on the deinterleaved RAM 18 to the original data before interleaving. The read address is provided to the multiplexer 24. The multiplexer 24 outputs any one of a read address and a write address input according to the selection signal DIL-WR provided from the controller. The deinterleaving RAM 18 receives the write address and writes the reception data to a position corresponding to the write address. The deinterleaving RAM 18 reads the read address and reads and writes the data written at the position corresponding to the read address.

The interleaving write address generator 10 and the deinterleaving read address generator 22 of the interleaving apparatus and the deinterleaving apparatus generate the same address. That is, the address for writing the transmission data to the interleaving RAM 16 and the address for reading the reception data written to the deinterleaving RAM 18 are the same. Accordingly, the interleaving write address generator 10 and the deinterleaving read address generator 22 have the same configuration.

FIG. 5 shows a detailed block diagram of the interleaving write address generator 10 and the deinterleaving read address generator 22. As shown in FIG. 6 illustrates an operation timing diagram of the interleaving write address generator and the deinterleaving read address generator. The present invention will now be described in detail with reference to FIGS. 5 and 6. The WRRST of FIG. 5 is a signal generated for each data block as a write reset signal and is provided by the controller. WRSCK is provided by the controller as a write clock. The WRRST is generated every 456 WRCLK clocks as shown in FIG.

The WRRST is input to the MOD8 counter (CNT1). The MOD8 counter CNT1 is a counter that increases the count value at the falling edge of the clock and counts again from the beginning when the count value reaches 8. The MOD8 counter CNT1 also generates a REG1RST that occurs high while the count starts counting and performing count eight. The REG1RST is input to the reset terminal of the register R1. The count value of the MOD8 counter CNT1 is referred to as MOD80 (2: 0). The MOD80 (2: 0) repeats counting the WRCLK from 0 to 7, as shown in FIG. The MOD80 (2: 0) as described above is input to the first decoder DEC1. The first decoder DEC1 outputs 0 when MOD8 (2: 0) is 0, and outputs 1 when MOD8 (2: 0) is not 0. The output of the first decoder DEC1 is called ADD1I (2: 0). The ADD1I (2: 0) is input to the first adder ADD1.

The REG1RST is input to the reset terminal of the first register R1. WRCLK is input to the clock terminal of the first register R1. The first register R1 receives the output of the first adder ADD1 and latches it at the falling edge of WRCLK, and the first register R1 is reset at the rising edge of REG1RST. At this time, the output of the first register (R1) is referred to as REG10 (2: 0). The REG10 (2: 0) is input to the first adder ADD1. The first adder ADD1 receives and adds the REG10 (2: 0) and the ADD1I (2: 0). In this case, the output of the first adder ADD1 is referred to as ADD10 (2: 0). The first adder ADD1 receives 0 from the first decoder DEC1 at the first WRCLK. The first adder ADD1 is initially cleared. Accordingly, the output of the first adder ADD1 is 0, and the data output from the falling edge of the first WRCLK through the first decoder DEC1 is also 0. Accordingly, the first adder ADD1 adds 0 and 0 at the falling edge of the first WRCLK, so that ADD10 (2: 0) is zero. The ADD10 (2: 0) is input to the first register R1 so that the first register R1 latches the zero.

On the other hand, at the second falling edge, the MOD8 counter CNT1 performs a count, the count value 1 of the MOD8 counter CNT1 is input to the first decoder DEC1, and the first decoder DEC1 has a count value of 0. 1 is outputted. The output ADD1I (2: 0) of the first decoder DEC1 is input to the first adder ADD1, and the first adder ADD1 is latched by the first register ADD1I (2: 0) and the first register R1. Add 1 and output 1. The first is input to the first register R1 again, and the first register R1 latches the first. As the operation is performed as described above, REG10 (2: 0) repeats an increase from 0 to 6 as shown in FIG. 6, and ADD10 (2: 0) repeats an increase from 0 to 7 as shown in FIG. The ADD10 (2: 0) is input to the second adder ADD2.

On the other hand, DBNLSB is provided by the corresponding controller as a signal for changing the logic state at the rising edge of WRRST. The DBSLSB appears high at the rising edge of the first WRRST, and then goes high again at the next WRRST. The DBNLSB is input to the second decoder DEC2. The second decoder DEC2 outputs 0 when the DBNLSB is low and 4 when the DBNLSB is low. The output of the second decoder DEC2 is referred to as ADD2I (2: 0). The ADD2I (2: 0) is input to the second adder ADD2. The second adder ADD2 receives and adds the ADD2I (2: 0) and ADD10 (2: 0). The output of the second adder ADD2 is referred to as ADD20 (3: 0). As shown in FIG. 6, ADD20 (3: 0) repeats the increase from 0 to 7 after the rising edge of the first WRRST and increases from 4 to 11 after the rising edge of the second WRRST. Meanwhile, the ADD20 (3: 0) is input to the combiner CON1.

Meanwhile, the MOD80 (2: 0) is input to the third decoder DEC3. The third decoder DEC3 outputs 16 when the MOD80 (2; 0) is 1,2,3,5,6,7, 17 when 0, and 15 when 4. The output of the third decoder DEC3 is referred to as SUB1I (7: 0). The SUB1I (7: 0) is input to the first subtractor SUB1.

LOAD is a load signal provided from the controller. The load signal is input to the first multiplexer MUX1. The first multiplexer MUX1 outputs 17 input from the input terminal 1 when the load signal is input, and outputs a signal input from the input terminal 0 when the load signal is not input. Meanwhile, the output of the first multiplexer MUX1 is input to the second register R2.

On the other hand, the load clock signal LOADCLK and the WRCLK provided from the control unit are input to the first or gate OR1. The first oA gate OR1 outputs a signal appearing low only when the two signals are simultaneously low. The signal is input to the clock terminal of the second register R2. The second register R2 receives the signal and latches the output of the third decoder DEC3. The output of the second register R2 is referred to as REG20 (7: 0). The REG20 (7: 0) is input to the first subtractor SUB1. The first subtractor SUB1 receives the REG20 (7: 0) and the SUB1I (7: 0) and subtracts the SUB1I (7: 0) from the REG20 (7: 0). The output of the first subtractor SUB is referred to as SUB10 (7: 0). When SUB10 (7: 0) is first subtracted, 0 is outputted because REG20 (7: 0) is 17 and SUB1I (7: 0) is 17. The SUB10 (7: 0) is input to the fourth decoder DEC4, the third adder ADD3, and the second multiplexer MUX2. The third adder ADD3 receives 114 and adds it to SUB10 (7: 0) for output. The output is input to the second multiplexer MUX2.

On the other hand, the fourth decoder DEC4 receives the SUB10 (7: 0) and outputs 0 when the SUB10 (7: 0) is less than 0, and outputs 1 when the SUB10 (7: 0) is smaller than zero. At this time, the output of the fourth decoder DEC4 is input to the second multiplexer MUX2. If the output of the fourth decoder DEC4 is 0, the second multiplexer MUX2 outputs the output of the third adder ADD3, which is input to the input terminal 0, and if it is 1, the SUB10 inputted to the input terminal 1 (7: Output 0). At this time, the output of the second multiplexer MUX2 is referred to as MUX20 (7: 0). The MUX20 (7: 0) is 0, 98, 82, 66, 51, 35, as shown in FIG. This is the same as the bit address order shown in FIG.

Meanwhile, the first coupler CON1 receives the ADD20 (3: 0) and the MUX20 (6: 0), and the ADD20 (3: 0) is CON (10: 7), and the MUX20 (6: 0) is CON (6). Output by combining: 0). The output of the first coupler CON is called CON (10: 0). The output is input to an input terminal 1 of the third multiplexer DEC3, the second subtractor SUB2, and the fifth decoder DEC5. The fifth decoder DEC5 outputs 0 when the value is greater than 1023, and 1 when the other number is other. The value of the fifth decoder DEC5 is input to the third multiplexer MUX3. The second subtractor SUB2 receives 1024 and subtracts 1024 from CON (10: 0). The output of the second subtractor SUB2 is input to an input terminal 0 of the third multiplexer MUX3. When the output of the fifth decoder DEC5 is 0, the third multiplexer MUX3 outputs the output of the second subtractor SUB2 that is input to the input terminal 0, and when 1, the CON (10: 0) input to the input terminal 1 ) The output of the third multiplexer MUX3 is input to the third register R3. The third register R3 latches the output of the third multiplexer MUX3 every falling edge of WRRCLK. The latched value indicates an address on the interleaving RAM 16 and the deinterleaving RAM 18.

Meanwhile, the interleaving read address generator 12 and the deinterleaving write address generator 20 of the interleaving apparatus and the deinterleaving apparatus generate the same address. That is, the address at the time of reading the transmission data written to the interleaving RAM 16 and the address at the time of writing the reception data to the deinterleaving RAM 18 are the same. Accordingly, the read address generator 12 of the interleaving apparatus and the write address generator 20 of the deinterleaving apparatus have the same configuration.

7 shows a detailed block diagram of the read address generator 12 and the write address generator 20. 8 illustrates an operation timing diagram of the read address generator 12 and the write address generator 20. The present invention will now be described in detail with reference to FIGS. 7 and 8. The burst clock BurstCLK of FIG. 7 is provided by the controller, and occurs in each burst as shown in FIG. The BurstCLK is input to the MOD8 counter CNT2. The MO8 counter CNT2 counts the burst clock and repeats increments from 0 to 7. The output of the MOD8 counter CNT2 is called MOD8RO (2: 0). As shown in FIG. 8, MOR8RO (2: 0) is incremented by 1 every BurstCLK. When MOR8RO (2: 0) is increased from 0 to 7, the increase is repeated from 0 again. The MOD8RO (2: 0) is input to the fourth register R4. The fourth register R4 receives and latches MOD8R0 (2: 0). The output of the fourth register R4 is referred to as REG1RO (2: 0). The REG1RO (2: 0) is output after being delayed for each BurstCLK of the MOD8RO (2: 0). The REG1RO (2: 0) is input to the second combiner CON2.

RDCLK is input to the MOD 114 counter CNT3. The RDCLK is a clock composed of 114 clocks in one BurstCLK. The MOD 114 counter CNT3 repeats counting the RDCLK from 0 to 113. The count value is referred to as MOD114RO (6: 0). The MOD114RO (6: 0) starts counting 1 at the rising edge of the first RDCLK as shown in FIG. 8, and counts back to 0 at the 113 rising edge. The MOD114RO (6: 0) is input to the second combiner CON2. The second coupler CON2 receives REG1RO (2: 0) and MOD114RO (6: 0) and converts REG1RO (2: 0) to CONR (9: 7) and MOD114RO (6: 0) to CONR (6). Combine with: 0). The combined CONR (9: 0) as described above is input to the fifth register R5. The fifth register R5 receives RDCLK from the clock terminal to latch the CONR (9: 0). At this time, the output of the fifth register R5 is referred to as RDADDR (9: 0). The RDADDR (9: 0) represents an address indicated by the REG1RO (2: 0) and the MOD114RO (6: 0). The values shown in FIG. 8 are all converted to decimal numbers.

As described above, using the provision of full rate speech interleaving and deinterleaving of a GSM terminal, the interleaving and deinterleaving address generator can be simply configured using a mode counter and a decoder.

As described above, the present invention provides a simple interleaving write address and deinterleaving read address generator and interleaving read address and deinterleaving write address generator necessary for performing interleaving or deinterleaving in a full rate speech interleaving and deinterleaving apparatus of a GSM terminal. Can be configured. Accordingly, since the GSM terminal has a simple address generator, there is an advantage that the cost can be reduced and the size of the GSM terminal can be reduced.

Claims (3)

In the interleaving and deinterleaving address generator of the GSM terminal, In order to perform interleaving and deinterleaving reads, the transmission data is spread written to a memory area having 8 bursts and 114 bits, and the received data spread in the memory area is read in accordance with the order of one data before diffusion. To do this, we generate a burst address that increments sequentially from the first burst to the eighth burst, and repeats the increment again, with 15 bits increasing from 4 to 5 bursts and 17 converting from 8 to the first burst. An interleaving write and deinterleaving read address generator for generating a bit address in which a bit decreases when the other burst increases, and combining the burst address and the bit address to generate an interleaving write and deinterleaving read address; In order to perform interleaving read and deinterleaving write, transmission data spread out in the memory area as described above is read sequentially from the first bit of the first burst during interleaving read, and reception data is received during deinterleaving write. In order to write sequentially from the first bit of the first burst of such a memory area, a burst address that sequentially increases from the first burst to the eighth burst, repeats the increment again, and when the one burst increases And an interleaving read and deinterleaving write address generator that generates a bit address that sequentially increases the bits from 0 to 113 every time, and combines the burst address and the bit address to generate an interleaving write and a deinterleaving read address. Ugh Interleaving and de-interleaving address generator of the GSM terminal. The method of claim 1, wherein the interleaving write and deinterleaving read address generator comprises: a mode 8 counter for performing a mode 8 count in response to a write clock; A burst adder for adding 4 every time the mode 8 count is performed 114 times, A latch unit for latching an initial bit address and then latching a generated bit address; A bit for subtracting 15 from the latch value if the count value of the mode 6 counter is 4; subtracting 17 from the latch value if the count value of the mode 8 counter is 0; otherwise, subtracting 16 from the latch value Subtraction part, A bit adder for outputting a bit address by adding 114 to the subtracted value when the subtracted value is less than 0, and inputting the latch unit; An interleaving and deinterleaving address generator of a GSM terminal, comprising: an address output unit for combining the bit address and the burst address into one address and subtracting 1024 from the address when the address is greater than 1024 . The apparatus of claim 1, wherein the interleaving read and deinterleaving write address generator comprises: A mode 114 counter that performs mode 114 counts according to the read clock; A mode 8 counter that receives a burst clock that occurs once when the read clock occurs 114 times and performs a mode 8 count; And an address output unit for combining and outputting the mode 114 count value and the mode 8 count value into one address.