KR19980017778A - Orthogonal frequency division multiplexing reception system - Google Patents

Abstract

The present invention relates to an Orthogonal Frequency Division Multiplexing (OFDM) system, and more particularly to an OFDM system in which only an information signal is subjected to inverse fast fourier transform (IFFT) The present invention relates to a receiver of an orthogonal frequency division multiplexing system which transmits a transmission signal and detects a synchronization after fast Fourier transform (FFT) is performed in a reception system which receives the transmission signal. A memory 41 for storing data; A serial / parallel converter (42) for performing parallel conversion on N complex symbols in time slot units and outputting the result; An FFT chip 43 for FFT processing and outputting a complex symbol; A parallel / serial converter (44) for receiving the F complex processed N complex symbols, converting the received complex symbols into serial signals, and outputting the converted serial signals; A synchronization detector 45 for determining whether the symbol output from the parallel / serial converter 44 is the same as a time slot on the transmission side and outputting a synchronization detection signal SYNC; And a control unit 46 for controlling the output order of the symbols stored in the memory 41 according to the synchronization detection signal SYNC of the synchronization detection unit 45. When the synchronization detection signal SYNC becomes 0 So that it is possible to acquire the reconstructed signal from the correct synchronization. By acquiring the synchronization without inserting the synchronization signal separately, it is possible to solve the difficulty of implementing the channel and the system due to the significant subchannel occupied by the synchronization signal.

Description

Orthogonal frequency division multiplexing reception system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an Orthogonal Frequency Division Multiplexing (OFDM) system, and more particularly to an Inverse Fast Fourier Transform The present invention relates to an orthogonal frequency division multiplexing (OFDM) reception system for transmitting an OFDM transmission signal and performing fast Fourier transform (FFT) on the received reception system and then detecting synchronization.

In recent years, an OFDM scheme has been proposed which can operate robustly in a multi-channel transmission channel as a transmission method of digital audio broadcasting (DAB) and terrestrial broadcast high definition television (HDTV).

In the OFDM scheme, serial data having information is first converted into parallel data of block units, and then each signal modulated with a carrier wave having a different frequency is transmitted to the receiving side.

That is, since serial data is converted into parallel data in block units, the data rate of the parallel data is lower than that of the original data.

Therefore, in OFDM, fading due to multipath transmission can be considerably robust, and robustness against OFDM fading can be further improved by inserting a guard interval between symbols and symbols.

Another advantage of OFDM is that the spectrum of the signal can be made closer to a quadrangle as compared with the conventional digital modulator method, thereby further increasing the band efficiency. This is because the data rate of the modulated data is relatively low, so that the spectrum of the signal modulated by each carrier has a very narrow transition bandwidth, and the OFDM signal added thereto can also maintain a narrow transition bandwidth.

As described above, since the OFDM scheme modulates signals in the respective parallel channels and transmits the summed signals, independent sub-carriers corresponding to the number of parallel channels are required. The sub-carriers maintain mutual orthogonality in the frequency domain, Mutual motivation must be achieved.

Thus, in an implementation of an OFDM transceiver, an increase in the number of parallel subchannels causes an increase in the hardware complexity of the OFDM transceiver.

However, if the system is digitized, this process can be implemented in one FFT structure, which has the advantage of simple hardware implementation.

Here, a description will be made of a method of simplifying an OFDM receiver structure using an FFT technique.

As shown in FIG. 1, in the OFDM transmission scheme, a symbol to be transmitted is simultaneously modulated from N subchannels directly to each subcarrier, and symbols modulated in a time slot period are serially transmitted.

Here, Is the symbol transmitted from the 1 < th > time slot to the m < th > subchannel, Can be expressed by the following equation (1).

[Equation 1]

In Equation (1), N is the number of subchannels of OFDM, Represents the period of one time slot. When such a transmission signal is demodulated, Is detected from Equation (1) using Equation (2) using orthogonality of each subcarrier.

&Quot; (2) "

As shown in Equation (2), the OFDM receiver generates a subcarrier for each subchannel and then performs a multiplication and an integral operation. However, the OFDM reception signal is complex and is sampled by a digital technique, By doing this, you can eliminate the integral and reduce the number of multiplications. Here, To symbol Is expressed by the following equation (3).

&Quot; (3) "

As shown in Equation (3), the OFDM reception signal can be sampled and then FFT-transformed to decode the transmission symbol.

Therefore, if a receiver is implemented using an FFT chip, the multiplication operation in the reception process can be reduced and the orthogonality of each subcarrier can be maintained.

FIG. 2 is a block diagram of a general orthogonal frequency division multiplexing transmission system. The OFDM transmission system includes a serial / parallel conversion unit 21, an IFFT chip 23, and a parallel / serial conversion unit 33.

The serial-to-parallel converter 21 receives the data to be transmitted as a bit stream and outputs 2N bits in parallel. The IFFT chip 23 converts the first input bit into a real number component and the second input bit Serial conversion unit 25 outputs N complex symbols that are subjected to inverse Fourier transform (NF) in a serial manner, and outputs the N complex symbols in an OFDM transmission mode Signal.

3 is a block diagram of a general orthogonal frequency division multiplexing reception system. The OFDM reception system is composed of a serial / parallel conversion unit 31, an FFT chip 33, and a parallel / serial conversion unit 35.

The S / P converter 31 receives the OFDM reception signal input as a bit stream and outputs 2N bits in parallel. The FFT chip 33 receives the first input bit as a real component and the second input bit Serial conversion unit 35 serially outputs the N complex symbols subjected to the inverse Fourier transform and outputs the N complex symbols in the form of an original transmission And restores it to a desired signal.

Meanwhile, most digital communication systems including digital TVs transmit a series of sync signals together with data for frame synchronization. Since the acquisition of frame synchronization is the first operation performed on data streams in the baseband signal processing, the acquisition of synchronization should be designed to exhibit performance above a certain level even when noise or channel distortion is severe.

Generally, the transmission format of the synchronous signal can be divided into a synchronous word system and a frame marker system. The synchronization word is transmitted in the header of the data in the transmission of the data having the non-periodicity such as the burst transmission, while the marker is transmitted in the frame in the frame with the data in the system in which the data is repeatedly transmitted at a constant period.

The basic search algorithm used to acquire the synchronous signal includes a threshold based algorithm that determines similarity between the input data and the reference synchronous signal for each sample and determines the synchronous signal as a synchronous signal when the value exceeds a predetermined value, And a compare based algorithm that finds a delay value that maximizes the value in one frame.

In the OFDM system, since the original information is reconstructed by performing IFFT conversion on N symbols as a unit, transmitted in time slot units, and FFT-transforming the same time slot on the receiving side, the synchronization of the time slot must be accurately detected.

Therefore, since the conventional synchronous detection method inserts a synchronous signal for each time slot and transmits the synchronous signal together with the information signal, there is a problem that a significant subchannel occupied by the synchronous signal causes waste of resources required for channel and system implementation.

Also, since the increase of the number of actual subchannels leads to an increase of the FFT size, there is a problem that hardware implementation is difficult.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an orthogonal frequency division multiplexing (OFDM) reception system that detects synchronization using characteristics of an OFDM signal without inserting a synchronization signal It has its purpose.

In order to achieve the above object, the orthogonal frequency division multiplexing (OFDM) system of the present invention does not insert a synchronization signal for each time slot but IFFT-processes the information signal only in time slot units (N complex symbols) In the receiving system,

A memory for receiving and storing OFDM reception signals; A serial / parallel converter for receiving the complex symbol sequence output from the memory and parallel-converting the complex symbol sequence into N complex symbols in time slot units and outputting the complex symbols; An FFT chip that receives the N complex symbols output in parallel and performs FFT processing with the first bit of the complex symbol as a real number component and the second bit as an imaginary component; A parallel / serial converter for receiving the F complex processed N complex symbols and outputting them in series; A synchronization detector for determining whether a symbol output from the parallel / serial converter is the same as a time slot on a transmission side and outputting a synchronization detection signal; A control unit for controlling an output order of symbols stored in the memory according to a synchronization detection signal of the synchronization detection unit; .

In the OFDM reception system configured as described above, instead of synchronizing the time slots with the synchronous signal, the transmitting and receiving sides transmit the IFFT-processed OFDM transmission signal without inserting the synchronous signal at the transmitting side, And examines the FFT-processed symbols to detect the synchronization.

That is, if FFT is performed on the N complex symbol units corresponding to the original time slot, the value is extracted as two symbols every time slot interval using the characteristic of the OFDM signal having the original transmission signal size +1 or -1, It is possible to acquire the synchronization by checking whether or not the difference between the absolute values of " 0 "

1 is a signal diagram illustrating a transmission pattern of a symbol in an orthogonal frequency division multiplexing system,

2 is a block diagram of a general orthogonal frequency division multiplexing transmission system,

3 is a block diagram of a general orthogonal frequency division multiplexing reception system,

FIG. 4 is a block diagram of an orthogonal frequency division multiplexing reception system according to the present invention.

5 is a detailed circuit diagram of the synchronous detection circuit of the present invention shown in FIG.

Description of the Related Art [0002]

41: memory 42: serial /

43: FFT chip 44: parallel /

45: synchronization detecting section 46:

51: first absolute value calculator 52: first shift register

53: second absolute value calculator 54: second shift register

55: first adder 56: second adder

57: subtracter 58: third adder

59: counter 60: D flip flop

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

First, the principle of synchronous detection of an OFDM signal, which is a core of the present invention, will be described.

The time slot in which the information signal having a signal size of +1 or -1 on the transmitting side is N complex symbols and is transmitted by IFFT is +1 or -1 size when FFT is performed from the first symbol of the time slot on the receiving side The original information signal is obtained.

However, if the receiving side performs FFT processing from a symbol other than the first symbol of the time slot, a signal having a size different from the original information signal size is obtained.

Since the magnitude of the correctly reconstructed information signal is +1 or -1, the absolute values of the two symbols are obtained for each time slot interval. If the difference is 0, the reconstructed signal is correct. As shown in Fig.

&Quot; (4) "

In Equation (4), Re _{l, m} is the real number component of the mth symbol of the lth time slot, Im _{l, m} is the imaginary component of the mth symbol of the lth time slot, Re _l-1, 1 _{, m} is the imaginary component of the m-th symbol of the (1-l) -th time slot.

Assuming that the transmitted noise component has a Gaussian distribution on the received symbol, the average of the Gaussian distribution is zero, which can be expressed as a discrete sum as shown in Equation (4).

If the value is +1 or -1, the mth symbol of the l time slot and the mth symbol of the l-1 time slot are extracted to obtain the absolute value of each symbol, One SYNC value will be zero, and if the sync is out, the SYNC value is probably not zero.

4 is a block diagram of an OFDM receiving system according to the present invention. The system includes a memory 41, a serial / parallel converter 42, an FFT chip 43, a parallel / serial converter 44, A synchronization detecting section 45, and a control section 46.

The memory 41 receives and stores an OFDM reception signal. The serial / parallel conversion unit 42 receives the complex symbol sequence output from the memory 41 and performs parallel conversion on the N complex symbols in a time slot unit And outputs it.

The FFT chip 43 receives the N complex symbols output in parallel and performs FFT processing on the complex symbols with the first bit of the complex symbol as a real component and the second bit as an imaginary component.

The parallel / serial converter 44 receives the F complex processed N complex symbols, converts the received complex symbols into serial signals, and outputs the serialized signals.

The synchronization detector 45 determines whether the symbol output from the parallel / serial converter 44 is the same as the time slot on the transmission side and outputs a synchronization detection signal SYNC.

The control unit 46 controls the output order of the symbols stored in the memory 41 according to the synchronization detection signal SYNC of the synchronization detection unit 45.

Here, the synchronization detection signal SYNC is transmitted to a decoding unit connected to the rear end of the receiving system, and notifies the decoding unit of decoding only when the symbol is a FFT-converted symbol in correct synchronization.

Next, the operation and effect of the present invention configured as described above will be described in detail.

5, the synchronization detector 45 includes a first absolute value calculator 51, a first shift register 52, a second absolute value calculator 53, A second adder 56, a subtractor 57, a third adder 58, an up-down counter 59, and a D flip-flop 60. The first adder 56, the second adder 56,

The first absolute value calculator 51 calculates and outputs the absolute value of the real component Re ₁ , which is the first bit of the complex symbol, and outputs the output of the first absolute value calculator 51 to the first shift register 52. N clock is delayed to output Re _l-1 .

The second absolute value calculator 53 obtains and outputs the absolute value of the imaginary component Im _l which is the second bit of the complex symbol and the second shift register 54 outputs the output of the first absolute value calculator 53 N clock is delayed to output Iml _-1 .

The first adder 55 adds the output Re _l of the first absolute value calculator 51 and the output Re _{l -1} of the second absolute value calculator 52 and outputs the result.

The second adder 56 adds the output Re _l of the first shift register 52 and the output Re _l-1 of the second shift register 54 and outputs the result.

The subtracter 57 subtracts the output of the first adder 55 and the output of the second adder 56 and outputs the result.

The third adder 58 adds the output of the subtracter 57 and the value fed back from the D flip-flop 60 to the D flip-flop 60 again.

The up-down counter 59 counts the number of symbols of the time slot in synchronization with the bit clock, and counts from 0 to N-1, thereby clearing the D flip-flop 60 for each time slot.

Now, a description will be made of a process of detecting synchronization, for example, in a case where FFT processing is performed in an unsynchronized manner.

First, in a 2N information signal having a signal amplitude of +1 or -1 on the transmission side, N first complex symbols are formed by using a real number component as a first bit and an imaginary component as a second bit, And performs serial-to-serial conversion to transmit the OFDM transmission signal.

On the receiving side, if the FFT is performed from the first symbol of the time slot, the original information signal having the size of +1 or -1 can be obtained. However, if the FFT processing is performed from a symbol other than the first symbol of the time slot, Obtains signals of different sizes.

Now, with reference to FIG. 4 and FIG. 5, a process of acquiring synchronization without inserting a synchronization signal will be described.

The memory 41 receives and stores an OFDM reception signal and then outputs N complex symbols to the S / P converter 42 according to a control signal of the controller 46, and performs parallel conversion on N complex symbols And outputs it to the FFT chip 43.

The FFT chip 43 receives the N complex symbols output in parallel and FFT-processes the complex symbol with the first bit of the complex symbol as a real component and the second bit as an imaginary component, and outputs the resultant to the parallel / (44) receives the F complex processed N complex symbols, converts them into serial signals, and outputs them.

Here, a description will be made of a process of detecting synchronization, for example, in a case where FFT processing is performed in an unsynchronized manner.

Transmission stream on the transmission side:

X _0,0 X _0,1 X _0,2 ... X _{0, N-2} X _{0, N-1} X _1,0 X _1,1 X _1,2 X _1,3 X _1,4 ... X _{1, N-1} ...

The transmission symbol X _{l, m} subjected to the IFFT processing on the transmitting side is a complex symbol consisting of a bit representing a real number component and a bit representing an imaginary number component.

Of the 0th time slot a transmission symbol _{X 0,0 ~ X 0, N-} 1 from the second time slot of a transmit symbol _{X 1,0 ~ X 1, N-} 1 transmission during X _0,0 X _0,1 ~ two of the symbol is lost if the transfer from the X _0,2 in the receiving side, the receiving side by the N complex symbols that is, ~ X _0,2 X _1,1 in one time slot FFT processing, and X _1,2, X ~ _{2 , 1} as a time slot, and then converts the signal into a serial signal.

The first bit corresponding to the real component is input to the first absolute value calculator 51 and the second bit corresponding to the imaginary component is input to the second absolute value calculator 53, After the values are calculated, the respective absolute values are input to the N shift registers 52 and 54.

When the second symbol of the first time slot is input, the second symbol of the 0 th time slot is output in the shift registers (52, 54) delayed by N clocks. The first adder (55) The absolute value of the two symbols is obtained through a 2-adder 56, and the subtracter 57 calculates the difference between the two absolute values.

Subsequently, the absolute value of the two symbols is calculated up to N symbols, and the synchronization detection signal SYNC, which is a value obtained by adding the difference through the third adder 58, is output to the control section 46.

The controller 46 receives the synchronization detection signal SYNC and determines that the synchronization detection signal SYNC is not 0 and performs FFT processing on N symbols from the third symbol of the 0th time slot stored in the memory 41 as one time slot .

The synchronization detection signal SYNC value of the second symbol of the first time slot from the third symbol of the serial time-shifted FFT-processed 0 th time slot will not be 0, The control unit performs FFT transform on the third symbol of the first time slot from the 4 < th > symbol of the 0 < th > time slot as one time slot.

As a result of repeating the above operation, the FFT-processed signal from the first symbol to the last symbol of the first time slot as a time slot becomes 0 as a result of the check of the synchronization detection signal SYNC of the synchronization detector 45, Correct synchronization is detected, and the synchronization detection signal is transmitted to a decoding unit connected to the next stage, thereby notifying that decoding is performed only when the FFT-converted symbol is precisely synchronized.

As described above, instead of a method of inserting a synchronization signal for each time slot, an OFDM signal transmitted by IFFT processing only an information signal is stored in a memory, FFT processing is performed on symbols as much as a time slot size, 0 to obtain the recovered signal from the correct synchronization, thereby solving the difficulty of implementing the channel and the system due to the significant subchannel occupied by the synchronization signal.

Claims (2)

An orthogonal frequency division multiplexing (OFDM) system for transmitting an OFDM signal by performing inverse fast Fourier transform (IFFT) on an information signal only without inserting a synchronization signal, and detecting a synchronization using a signal obtained by a fast Fourier transform In the system, A memory 41 for receiving and storing an OFDM reception signal; A serial / parallel converter 42 for receiving the complex symbol sequence output from the memory 41 and parallel-converting the complex symbol sequence into N complex symbols in time slot units and outputting the result; An FFT chip 43 for receiving the N complex symbols output in parallel and performing an FFT process on the first complex data of the complex symbol as a real number component and the second bit as an imaginary component; A parallel / serial converter (44) for receiving the F complex processed N complex symbols, converting the received complex symbols into serial signals, and outputting the converted serial signals; A synchronization detector 45 for determining whether the symbol output from the parallel / serial converter 44 is the same as the time slot on the transmission side and outputting a synchronization detection signal SYNC; And a control unit (46) for controlling an output order of symbols stored in the memory (41) according to a synchronization detection signal (SYNC) of the synchronization detecting unit (45). The apparatus as claimed in claim 1, wherein the synchronization detector (45) A first absolute value calculator 51 for obtaining an absolute value of a real component Re ₁ , which is the first bit of the complex symbol, and outputting the absolute value; A first shift register (52) for delaying the output of the first absolute value calculation (51) by N clocks and outputting Re _-1 ; A second absolute value calculator 53 for calculating and outputting the absolute value of the imaginary component Im _l , which is the second bit of the complex symbol; A second shift register 54 for delaying the output of the first absolute value calculator 53 by N clocks; A first adder (55) for adding and outputting the output of the first absolute value calculator (51) and the output of the second absolute value calculator (52); A second adder (56) for adding and outputting the output of the first shift register (52) and the output of the second shift register (54); A subtractor 57 for subtracting and outputting the output of the first adder 55 and the output of the second adder 56; A third adder 58 for adding and outputting the output of the subtracter 57 and the feedback input value; An up-down counter 59 for counting the number of symbols in the time slot in synchronization with the bit clock, counting from 0 to N-1; The D flip-flop 60 receives the output of the third adder 58 and outputs the feedback to the third adder 58 and the D flip-flop 60 which is cleared by the up-down counter 58 every time slot period Wherein the orthogonal frequency division multiplexing system comprises: