KR19980017375A - Adaptive differential pulse code modulation restoration circuit - Google Patents

Abstract

The present invention relates to an adaptive differential pulse code modulation (ADPCM) decompress circuit.

An input register for inputting data compressed by adaptive differential pulse code modulation; An index generator which decodes the data output from the input register, generates an index unique to the data, and provides the index as an address; A step size generation unit for storing a predetermined step size corresponding to each address in advance, and outputting a step size corresponding to the address if an address is input from the index generation unit; A restoration unit for selecting a step size or ground data output from the step size generation unit according to each bit data state of the data output from the input register, and adding the selected data with the selected data one cycle before; And a data output unit for providing data obtained by adding the data output from the decompression unit and the output data one cycle earlier as output data,

It is possible to implement an adaptive differential pulse code modulation recovery circuit having a smaller chip area and operating faster than the conventional circuit.

Description

Adaptive differential pulse code modulation restoration circuit

The present invention relates to an adaptive differential pulse code modulation (ADPCM) decompressor circuit, and more specifically, to a linear code by inputting a compressed ADPCM code. It relates to a recovery circuit for converting to.

Pulse Code Modulation (PCM) for digital communication systems, digital audio, and sound cards or similar devices of personal computers. The data of the method is used a lot.

The PCM method is a modulation method that can transmit information more efficiently by converting an analog signal into a code based on a binary number.

Basically, PCM has a sampling, quantization, and encoding process. The sampling process is to detect the instantaneous values that appear at regular sampling times with respect to the level of the analog signal, and the quantization process is to approximate the detected instantaneous value to a value closest to a predetermined quantization level, and the encoding process is to approximate the approximated quantization level. Is to add a sign to.

Since the code obtained by the PCM scheme as described above is binary data, it has an advantage that it can be applied to the above-mentioned digital apparatus.

However, since the PCM method encodes an absolute level of an analog signal, when the analog signal is not so high as the average amplitude such as voice or sound, the efficiency is lowered, and the bit rate at the time of encoding is increased. Rate is a big problem.

In order to overcome the above drawbacks, a differential pulse code modulation (DPCM) scheme for encoding the difference in signal levels has been proposed. However, the DPCM method has a disadvantage in that a sufficient response cannot be obtained when the level of the signal changes abruptly.

Accordingly, the ADPCM scheme for changing the reference quantization width by a predefined weight corresponding to the difference of the change has been proposed, which enables highly efficient compression coding.

A sound generator using the ADPCM scheme is disclosed in US Patent Nos. 4, 989 and 246. The sound generator disclosed in the above-described US patent only counts the length of the silent section when converting the voice signal to the ADPCM code, but does not store the data of the silent section, and the count result when restoring the ADPCM code to the voice signal. This is to increase the efficiency of the memory by allowing the silence section to be reproduced.

However, the sound generator having the above-described structure not only uses two ROMs (Read Only Memory) in generating an index value, but also requires a counter and a separate control logic, which causes a complicated circuit. .

Therefore, an object of the present invention is to solve the conventional technical problems as described above, to obtain a unique step size by inputting a compressed ADPCM code, and using the input data and the obtained step size. It is to provide an ADPCM reconstruction circuit that generates linear data before compression.

1 is a block diagram of an adaptive differential pulse code modulation recovery circuit according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1: Input register 2: Index generator

3 step size generation unit 4 restoring unit 5 data output unit

As a technical means for achieving the above object, the adaptive differential pulse code modulation recovery circuit according to the present invention,

An input register for inputting data compressed by adaptive differential pulse code modulation and holding at the output stage;

An index generator for decoding the data output from the input register to generate an index unique to the data, checking whether there is an overflow or an underflow in the generated index, and outputting the data obtained as a result of the check as an address;

A step size generation unit for storing a predetermined step size corresponding to each address in advance, and outputting a step size corresponding to the address if an address is input from the index generation unit;

Selects the step size or ground data output from the step size generator according to the state of each bit data from the least significant bit to the most significant bit of the data output from the input register, and selects the selected data one cycle before Restoration unit for adding and outputting; And

A data output unit which adds data output from the decompression unit and output data one cycle earlier, checks whether there is an overflow or underflow in the added data, and provides data obtained as a result of the inspection as an output data; do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an adaptive differential pulse code modulation recovery circuit according to an embodiment of the present invention.

First, referring to FIG. 1, a configuration of an adaptive differential pulse code modulation recovery circuit according to an embodiment of the present invention will be described.

As shown in FIG. 1, an adaptive differential pulse code modulation recovery circuit according to an embodiment of the present invention includes: an input register (1) for receiving 4-bit input data compressed by an ADPCM and holding it at an output stage; An index generator (2) for inputting data output from the input register (1) to output predetermined address data; A step size generator (3) for inputting data output from the index generator (2) to output a 16-bit step size; A restoring unit 4 for outputting the 16-bit data restored by inputting the data output from the input register 1 and the step size output from the step size generator 3; and outputting from the restoring unit 4; And a data output section 5 for inputting the data to output 16-bit output data.

In more detail, the index generator 2 includes an index decoder 21, a first limiter 22, and an address register 23 that are sequentially connected. The address register 23 is connected such that output data is fed back to the first limiter 22.

The step size generator 3 inputs data output from the address register 23 and outputs a step size corresponding thereto, and a shift register 32 connected to an output terminal of the ROM 31. It is composed of

The recovery unit 4 inputs data output from the input register 1 as a selection signal, and multiplexer 41 for inputting the output data of the shift register 32 and the 16-bit ground data as two input signals. The first adder 42 and the temporary register 43 are sequentially connected to the output terminal of the multiplexer 41. The temporary register 43 is connected such that output data is fed back to the first adder 42.

The data output unit 5 includes a second adder 51, a second limiter 52, and an output register 53 sequentially connected to the output terminal of the temporary register 43. The output register 53 is connected such that the output data is fed back to the second adder 51.

The adaptive differential pulse code modulation recovery circuit according to the embodiment of the present invention configured as described above is implemented to operate each block by seven clock signals ph0ph6.

Next, the operation of the adaptive differential pulse code modulation recovery circuit according to the embodiment of the present invention will be described based on the above configuration.

When power is supplied and the operation of the circuit starts, 4-bit input data is input into the input register 1, which holds the input data at the output terminal. The 4-bit input data is data compressed by ADPCM.

The data output from the input register 1 is provided to the select signal terminals of the index decoder 21 and the multiplexer 41.

The index decoder 21 decodes the output to be fixed according to the output data of the input register 1 so as to generate an index unique to the data, and outputs the generated index to the first limiter 22.

The first limiter 22 inputs the index output from the index decoder 21 and the index one cycle from the address register 23, and overflows or underflows the input data. ) To see if it exists. That is, it is checked whether the data input to the first limiter 22 has a value between the maximum value and the minimum value that can be expressed as the number of bits thereof. If the data input to the first limiter 22 is not the value between the maximum value and the minimum value, the data is fixed to the maximum value or the minimum value.

The address register 23 receives data output from the first limiter 22 and holds the data at the output terminal, and provides the output terminal data to the ROM 31 as an address.

Each time the address is provided in the address register 23, the ROM 31 generates one corresponding to the address from a prestored step size and outputs it to the shift register 32. At this time, the step size output from the ROM 31 is 16-bit data.

The shift register 32 inputs the step size output from the ROM 31 by the shift operation, and maintains the input step size at the output terminal. This shift register 32 is to effectively replace the three addition processes required for outputting the step size from the ROM 31, and stores data while shifting the step size data one bit by one bit. For this reason, the data of the step size are divided by 1/2.

The multiplexer 41 accepts the 16-bit step size and 16-bit ground data output from the shift register 32 as input signals, and inputs the data output from the input register 1 as a selection signal.

The multiplexer 41 inputs the two inputs according to the state of each bit data from the least significant bit (LSB) to the most significant bit (MSB) among the data output from the input register 1. Select one of the signals. For example, if any bit of the data output from the input register 1 is '1', the data output from the shift register 32 is selected, and if the bit is '0', the ground data is selected. In this manner, the data selected by the multiplexer 41 is output to the first adder 42, which adds the restored data and the selected data one cycle before the feedback. The data obtained as a result of the addition is output to the temporary register 43, and the temporary register 43 keeps the input data at the output terminal and feeds it back to the first adder 42.

The second adder 51 adds the data output from the temporary register 43 and the output data one cycle before the feedback, and outputs the data obtained as a result of the addition to the second limiter 52.

Like the first limiter 22 described above, the second limiter 52 checks whether an overflow or underflow exists in the input data. However, the first limiter 22 handles 4 bits of input data, whereas the second limiter 52 handles 16 bits of input data. The data obtained as a result of the inspection of the second limiter 52 is output to the output register 53.

The output register 53 inputs and outputs data output from the second limiter 52 to the output terminal, and provides the output terminal data to the outside as restored 16-bit output data.

The function of the clock signal ph0ph6 supplied to each block will be described below.

ph0: Load 4-bit input data into the input register (1).

ph1, ph2, ph3: The step size output of the ROM 31 and the shift operation of the shift register 32 and the input register 1 are controlled. The shift clock sclk is generated by multiplying the clock signals ph0, ph1, and ph2, and the above operation is performed by the shift clock sclk.

PH2, PH3, PH4: The temporary register 43 stores two calculation results at the time points of the clock signals PH1, PH2, and PH3.

PH5: Controls input of data to the output register 53 to output the final operation result. In addition, the address register 23 controls input of data output from the first limiter 22.

PH6: The shift register 32 inputs data from the ROM 31, and the temporary register 43 controls the operation of resetting to input new data.

On the other hand, the address clock signal add-clk for controlling the operation of the address register is obtained by ANDing the clock signals ph1, ph2, ph3, and ph4, and thus the clock signals ph1, ph2, ph3, and ph4. An address is generated every time.

As described above, according to the exemplary embodiment of the present invention, an ADPCM recovery circuit having a smaller chip area and operating faster than the existing circuit can be implemented.

That is, the conventional circuit requires not only a register for holding data but also a counter for controlling the circuit and accompanying glue logic. However, the present invention uses a shift register to simply implement an ADPCM recovery circuit. Can be implemented.

Claims (7)

An input register for inputting data compressed by adaptive differential pulse code modulation and holding at the output stage; An index generator for decoding the data output from the input register to generate an index unique to the data, checking whether there is an overflow or an underflow in the generated index, and outputting the data obtained as a result of the check as an address; A step size generation unit for storing a predetermined step size corresponding to each address in advance, and outputting a step size corresponding to the address if an address is input from the index generation unit; Selects the step size or ground data output from the step size generator according to the state of each bit data from the least significant bit to the most significant bit of the data output from the input register, and selects the selected data one cycle before Restoration unit for adding and outputting; And A data output unit which adds data output from the decompression unit and output data one cycle earlier, checks whether there is an overflow or underflow in the added data, and provides data obtained as a result of the inspection as an output data; Adaptive differential pulse code modulation recovery circuit. The method of claim 1, wherein the index generator An index decoder for generating an index by decoding data output from the input register; Examine whether there is an overflow or an underflow in the index output from the index decoder and an index before the fed back period, and when there is an overflow or an underflow, the maximum value or the maximum value that can be expressed by the number of bits of each index. And a first limiter for outputting the input data as it is, when there is no overflow and underflow; and An adaptive differential pulse code modulation recovery circuit comprising: an address register for inputting data output from said first limiter to be held at an output terminal and provided to said step size generator as address data. The method of claim 2, wherein the step size generation unit A pre-stored predetermined step size corresponding to each address, and outputting a corresponding step size each time an address is input; and And a shift register for inputting the step size output from the ROM by a shift operation, and holding the input data at an output terminal. 4. The adaptive differential pulse code modulation and recovery circuit according to claim 3, wherein the step size stored in the ROM has an extended number of bits compared to the data compressed by the adaptive differential pulse code modulation. The method of claim 3, wherein the restoration unit The ground data of the same number of bits as the step size and the step size output from the shift register are input as two input signals, and the data output from the input register is input as a selection signal, and the two bits are changed depending on the state of each bit data of the selection signal. Selecting means for selecting one of the input signals; A first adder for adding the data selected by the selecting means and the restored data one cycle before the feedback; and And a temporary register configured to hold data output from the first adder at an output stage and to feed back the output stage data as data restored to the first adder. 6. The adaptive differential pulse code modulation recovery circuit according to claim 5, wherein said selecting means is a multiplexer. The method of claim 5, wherein the data output unit A second adder for adding data output from the temporary register and output data one cycle before the feedback; A second limiter for checking whether there is an overflow or an underflow in the data output from the second adder; and And an output register for inputting data obtained as a result of the inspection of said second limiter and holding it at an output stage.