KR0182182B1 - Adaptive differential pcm compression circuit - Google Patents

Abstract

The present invention relates to an adaptive differential pulse code modulation (ADPCM) compression circuit,

A compressed sample generating unit 2, a compressed sample output unit 3, a step size generating unit 4, and a prediction data generating unit 5,

By generating the difference between the 16-bit input data and the prediction data, comparing the difference with the step size determined by the output data one cycle before, and compressing to generate 4-bit output data,

It requires less storage space than in the prior art and requires only one ROM for storing the step size, thereby preventing the system from becoming complicated.

Description

Adaptive Differential Pulse Code Modulation Compression Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive differential pulse code modulation (ADPCM) compression circuit. More specifically, the present invention relates to an ADPCM (Adaptive Differential Pulse Code Modulation) To the compression circuit.

Pulse Code Modulation (hereinafter referred to as PCM) is applied to a sound card of a digital communication system, a digital audio system, a personal computer, or the like. Data is often used.

Such a PCM scheme is a modulation scheme that can transmit information more efficiently by changing an analog signal to a code based on a binary number. Basically, the PCM has sampling, quantization, and encoding processes. The sampling process is to detect an instantaneous value appearing at a predetermined sampling time with respect to the level of the analog signal, and the quantization process approximates the detected instantaneous value to a value closest to a predetermined level. Is added.

Since the code obtained by the PCM method is binary digital data, it has an advantage that it can be applied to the above-mentioned digital device.

However, since the PCM scheme encodes the absolute level of the analog signal, the efficiency becomes low when the maximum amplitude of the analog signal, such as voice or sound, is not so high as compared with the average amplitude.

In order to overcome such disadvantages, Differential Pulse Code Modulation (DPCM) method for coding a difference in signal level has been proposed. However, in the DPCM scheme, when the level of the signal is rapidly changed, a sufficient response can not be obtained with respect to the change.

Accordingly, an ADPCM scheme for changing the reference quantization width by a predefined weight corresponding to the difference between the changes is proposed, and this scheme enables highly efficient compression coding.

A sound generator employing such an ADPCM scheme is disclosed in U.S. Patent No. 4,989,246. The sound generator disclosed in the above-mentioned U.S. patent only counts the length of a silence section when converting a voice signal into an ADPCM code, but does not store data of a silent section, and when restoring an ADPCM code into a voice signal, So as to increase the efficiency of the memory.

However, the sound generator having the above-described structure uses two ROMs (Read Only Memory) in generating an index value, and also requires a counter and a separate control logic, thus complicating the circuit .

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned conventional technical problems, and it is an object of the present invention to provide an ADPCM code having a reduced number of bits by comparing the difference with the step size, And a compression circuit.

1 is a configuration diagram of an adaptive differential pulse code modulation / compression circuit according to an embodiment of the present invention;

2 is a detailed configuration diagram of the compressed sample generator shown in FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

1: differential generating unit 2: compressed sample generating unit

3: Compressed sample output unit 4: Step size generator

5: prediction data generator

As a means for achieving the above object, an adaptive differential pulse code modulation compression circuit according to the present invention comprises:

A difference generator for inputting the predicted data and the linear data of the sampled predetermined bits, calculating a difference between the two data, and outputting the difference;

One of the differential data output from the difference generator and the previous compressed sample data is selected in accordance with the compressed sample data of one cycle before and the compressed data of the selected sample is added by adding the inverted step size data to the selected data A compression sample generation unit for generating a compression sample;

The maximum valid bit of the difference data output from the difference generator is taken as a sign bit of the output data, the compressed sample data generated by the compressed sample generator is received a predetermined number of times, A compressed sample output section for generating output data by taking it as data bits;

A step of generating an index by decoding the input data of the compressed sample output unit, adding the generated index to an index before one cycle, inverting the corresponding step size according to the added result, A step size generator for generating a step size; And

A step size input unit for inputting and decoding the output data generated by the compression sample output unit, a step size input unit for inputting a step size provided by the step size generation unit, and selecting a corresponding one of the step sizes according to the decoded value, And outputs the generated prediction data to the difference generation unit.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of an adaptive differential pulse code modulation / compression circuit according to an embodiment of the present invention,

2 is a detailed configuration diagram of the compressed sample generator shown in FIG.

First, the configuration of an adaptive differential pulse code modulation compression circuit according to an embodiment of the present invention will be described with reference to Fig.

1, an adaptive differential pulse code modulation circuit according to an embodiment of the present invention includes a differential generating unit 1, a compressed sample generating unit 2, a compressed sample output unit 3, (4) and a prediction data generator (5).

More specifically, the difference generator (1) includes a first register (11) for receiving sampled 16-bit linear data and holding it at the output stage; A fifth adder 12 for adding the predictive data and the predictive data one cycle before; A first limiter 13 and a fourth resistor 14 sequentially connected to the output terminal of the fifth adder 12; An inverter (15) connected to the output of the fourth register (14); A first adder (16) for receiving the outputs of the first register (11) and the inverter (15); An exclusive OR unit 17 for inputting the most significant bits and the remaining bits among the outputs of the first adder 16 and a second register 18 connected to the output terminal of the exclusive OR unit 17 .

The compression sample generator 2 includes a first multiplexer 21 for receiving the output of the second register 18 and a feedback value; A second multiplex 22 for inputting the output of the first multiplex 21 and the feedback value; A second adder 23 for inputting and adding the step size and the output of the second multiplex 22; A third register 24 for receiving the output of the second adder 23 and providing it as the feedback value to the first and second multiplexes 21 and 22, And register selection logic 25 for providing an output signal to the first and second multiplexes 21 and 22 as a selection signal.

The compressed sample output unit 3 includes an inverter 31 for inputting a most significant bit (MSB) of the second adder 23; A 1-bit output register (32, 33, 34) connected to sequentially input the output of the inverter (31); And a 1-bit output register (35) connected to input the most significant bit among the output data of the first adder (16).

The step size generator 4 includes an index decoder 41 for inputting 4-bit output data of the output register 3235; A third adder (42) for inputting and adding the output of the index decoder (41) and the previous index value of the feedback period; A second limiter and a ninth resistor 44 sequentially connected to an output terminal of the third adder 42; A ROM 45 storing a variable step size corresponding to each address, inputting the output data of the ninth register 44 as an address, and outputting a step size corresponding to the address; A shift register 46 for inputting the step size output from the ROM 45 and providing the step size to the prediction data generator 5 and a step size output from the shift register 46 to be inverted, To the second adder (23).

The prediction data generator 5 includes a compression sample decoder 55 for inputting 4-bit data of the output register 3235; A fifth eighth register 5154 for sequentially inputting the step size output from the shift register 46; A fourth adder 56 for inputting and adding the output of the compressed sample decoder 55 and the output of the fifth eighth register 5154 and a fourth adder 56 for adding the output of the fourth adder 56 and the output of the output register 35, And an exclusive OR unit 57 for performing an exclusive-OR operation on the output of the adder 12 and providing the result to the fifth adder 12.

The adaptive differential pulse code modulation / compression circuit according to an embodiment of the present invention configured as described above is implemented by an IMA (Interactive Multimedia Association) ADPCM algorithm in hardware.

Next, the operation of the adaptive differential pulse code modulation / compression circuit according to the embodiment of the present invention will be described based on the above configuration.

When power is supplied, the operation of the circuit is started, and the sampled 16-bit input data is input to the first register 11. The input data is linear data. The first register 11 holds the 16-bit input data at the output stage.

The fifth adder 12 adds the current prediction data to the prediction data one cycle before and the first limiter 13 adds overflow or underflow to the output data of the fifth adder 12 under flow.

If an overflow occurs in the output data of the fifth adder 12, the first limiter 13 outputs a maximum value that can be represented by the current number of bits. If an underflow occurs, Outputs the minimum value that can be expressed.

The fourth register 14 receives the output of the first limiter 13 and holds it at the output terminal and the inverter 15 inverts the output of the fourth register 14.

By the inversion of the inverter 15, the result obtained at the output of the first adder 16 is the value obtained by subtracting the current prediction data from the 16-bit input data, which is the difference between the input data and the prediction data.

The data output from the first adder 16 is divided into the most significant bits and the remaining bits and is input to the exclusive OR unit 16. Accordingly, the exclusive-OR unit 16 performs an exclusive-OR operation on the maximum significant bit and the remaining bits, which are sign bits.

If the most significant bit is '1', the remaining bits are inverted. If the most significant bit is '0', the remaining bits are passed through. This is for converting to a positive number when the difference is negative. The output of the exclusive-OR unit 17 is input to the second register 18, and the second register 18 holds the input data at the output terminal.

On the other hand, the most significant bit among the output data of the first adder 16 is provided to the output register 35, which holds the input bit as the most significant bit of the 4-bit output data at the output stage . This is to match the sign between the modulated 4-bit output data and the 16-bit input data.

The output of the second register 18 is input to the first multiplex 21 together with the output of the third register 24 and the first multiplex 21 receives the output signal of the register selection logic 25 To select one of the two inputs. The output of the third register 24 is sample data one cycle before.

The second multiplexer 22 selects one of the output of the first multiplexer 21 and the output of the third register 24 in accordance with the output of the register selection logic 25.

More specifically, the operation of the register selection logic 25 will be described with reference to FIG. 2 attached hereto.

As shown in FIG. 2, the register selection logic 25 includes three registers mp2, mp3 and mp4. The most significant bit MSB of the output of the second adder 23, And generates the selection signals SEL1 and SEL2 according to the phase signals ph1 to ph4 to be outputted to the first and second multiplexers 21 and 22, respectively. The phase signals ph1 to ph4 are for determining the internal operation mode of the register selection logic 25, each of which has a sequential high period. The registers mp2, mp3 and mp4 store predetermined data according to the mode determined by the phase signals ph1 to ph4. The register selection logic 25 stores the data in the registers mp2, mp3 and mp4. To generate the selection signals SEL1 and SEL2.

Table 1 below shows that the selection signals SEL1 and SEL2 generated in the register selection logic 25 in each mode of the phase signal are determined.

SEL1 SEL2 mp2 mp3 mp4 Initial mode 0 One 0 0 0 ph1 0 One 0 0 0 ph2 MSB = 0 0 0 0 0 0 MSB = 1 0 One One 0 0 ph3 MSB = 0 0 0 maintain 0 0 MSB = 1 / mp2 One maintain One 0 ph4 MSB = 0 0 0 maintain maintain 0 MSB = 1 mp2 + / mp3 One maintain maintain One

In Table 1, when the selection signal SEL1 is 0, the '0' input terminal of the first multiplex 21 shown in FIG. 2 is selected, and when it is 1, the '1' input terminal is selected. When the selection signal SEL2 is 0, the '0' input terminal of the second multiplex 22 shown in FIG. 2 is selected, and when it is 1, the '1' input terminal is selected.

Depending on the operation of the register selection logic 25 described above, one input of the second adder 23 is connected to the output of the second register 18 in accordance with the most significant bit MSB of the output and the phase signals ph1 to ph4 Or the output of the adder 23 before one cycle.

The second adder 23 adds the inverted step size output from the inverter 47 to the output of the second multiplex 22 and the added result is input to the third register 24 and the register selection logic 25 . The output of the second adder 23 is obtained by subtracting the step size from the difference.

The most significant bit among the outputs of the second adder 23 is input to the inverter 31. Each time an output occurs in the second adder 23, the most significant bit is input to the inverter 31, and the inverter 31 and the output register 3234 receive the most significant bit generated in the output register 3234 So that they are sequentially input. Each output register 3234 is a 1-bit register and stores 3 bits NS0, NS1, and NS2, respectively, from the least significant bit of the 4-bit output data.

For example, the most significant bit of the first output of the second adder 23 is input to the output register 34 via the inverter 31 and the most significant bit of the next output of the adder 23 is input to the output register 33, and the most significant bit of the next output of the adder 23 is input to the output register 32. [

The 4-bit output data of each output register 3235 obtained as described above is externally provided as ADPCM data.

The 4-bit output data of the output register 32 is input to the index decoder 41, and the index decoder 41 decodes the 4-bit data to generate a data-specific index. The generated index is input to the third adder 42 and the third adder 42 adds the index of one cycle previous to the output of the ninth register 44 and the index generated by the decoder 41 .

The output of the third adder 42 is input to the second limiter 43 and the second limiter 43 checks overflow or underflow of the input data like the first limiter 13 already described . The output of the second limiter 43 is input to the ninth register 44 and the ninth register 44 holds the input data at the output terminal.

The output data of the ninth register 44 is provided as the address of the ROM 45, and the ROM 45 outputs the data corresponding to the input address. Here, the data of the ROM 45 is the step size, which is obtained by experiment and stored in advance in the ROM 45 corresponding to the index.

The step size of the ROM 45 is input to the shift register 46 and the shift register 46 outputs the step size to the inverter 47 and the fifth eighth register 5154. For example, when a new step size is input, the shift register 46 outputs the currently held step size to the fifth register 51, and the next step size transferred by the shift operation is stored in the sixth register 52, And outputs the step size to the seventh register 53 and the eighth register 54 in the same manner as described above. The shift register 46 is a 16-bit register, and stores data by shifting the step size data to the right by one bit. This is to reduce the data of the step size by half.

The inverter 47 inverts the input step size and provides it to the input of the second adder 23.

On the other hand, the compressed sample decoder 55 receives and decodes the 4-bit output data, and outputs the decoded result to the fourth adder 56. [ Each register 5154 holds the step size input from the shift register 46 at the output stage.

The fourth adder 56 selects and adds one output of the register 5154 in accordance with the value output from the compression sample decoder 56 and outputs the added data to the exclusive OR unit 57.

The exclusive OR unit 57 performs an exclusive-OR operation on the output of the fourth adder 56 and the sign bit NS3 of the 4-bit output data, which is a positive integer when the sign of the 4-bit output data is negative Conversion. The result of the exclusive OR operation thus obtained is provided to the fifth adder 12.

As described above, the adaptive differential pulse code modulation / compression circuit according to the embodiment of the present invention generates the difference between the 16-bit input data and the prediction data, and outputs the difference as a step size To produce 4-bit output data.

Thus, the compression circuit according to the invention requires less storage space than in the prior art. In addition, since only one ROM for storing the step size is required, the compression circuit according to the present invention can prevent the system from becoming complicated.

Claims (8)

A difference generator for inputting the predicted data and the linear data of the sampled predetermined bits, calculating a difference between the two data, and outputting the difference; One of the differential data output from the difference generator and the previous compressed sample data is selected in accordance with the compressed sample data of one cycle before and the compressed data of the selected sample is added by adding the inverted step size data to the selected data A compression sample generation unit for generating a compression sample; The maximum valid bit of the difference data output from the difference generator is taken as a sign bit of the output data, the compressed sample data generated by the compressed sample generator is received a predetermined number of times, A compressed sample output section for generating output data by taking it as data bits; A step of generating an index by inputting the output data of the compressed sample output unit, adding the generated index to an index before one cycle, searching for a step size corresponding to the index, A step size generator for providing a step size; And A step size input unit for inputting and decoding the output data generated by the compression sample output unit, a step size input unit for inputting a step size provided by the step size generation unit, and selecting a corresponding one of the step sizes according to the decoded value, And outputting the generated prediction data to the difference generation unit. The adaptive differential pulse code modulation / 2. The apparatus of claim 1, wherein the difference generator An adder (12) for adding the predictive data output from the predictive data generator to the predictive data preceding one cycle; The data output from the adder 12 is checked to see if there is an overflow or an underflow. If the data is within a predetermined range, the data is passed. Otherwise, the maximum value is represented by the number of bits of the data. A limiter 13 for outputting a minimum value; An inverter (15) for inverting the output of the limiter (13); An adder 16 for adding the sampled bit data of the predetermined number of bits to the output of the inverter 15, And an exclusive OR unit (17) for performing an exclusive OR operation on the sign bit and the remaining bits of the data output from the adder (16). 3. The adder according to claim 2, further comprising: a register (11) connected to an input of the adder (16) for inputting sampled linear data of a predetermined bit to the input of the adder (16); A resistor 14 connected between the limiter 13 and the inverter 15 for providing the output of the limiter 13 to the input of the inverter 15, And a register (18) connected to an output terminal of the exclusive-OR unit (17) for holding the result of the exclusive-OR operation as differential data at an output terminal. 3. The apparatus of claim 2, wherein the compressed sample generator Switching means (21, 22) for selecting one of differential data output from the difference generator and feedback sample data before one cycle in response to a selection control signal; An adder (23) for adding the step size data inverted from the data selected by the switching means (21, 22) to generate compressed sample data; A register selection logic (25) for generating a predetermined selection control signal from the compressed sample data output from the adder (23) and providing the selected selection control signal to the switching means (21, 22) And a register (24) for holding the compressed sample data output from the adder (23) at the output terminal and providing the same to the switching means (21, 22) as compressed sample data one cycle before. 5. The apparatus of claim 4, wherein the compressed sample output section An inverting unit 31 for inputting and inverting the most significant bit of the compressed sample data output from the compressed sample generating unit; At least one register 3234 for sequentially inputting the inverted value of the most significant bit in the inverter 31 and holding it at the output terminal, And a register 35 for receiving the maximum valid bit of the difference data output from the adder 16 of the difference generator and holding the same at the output terminal. The output data of each register 3235 is supplied to the outside as modulated output data Adaptive differential pulse code modulation and compression circuit. 6. The apparatus of claim 5, wherein the step size generator An index decoder 41 for inputting and decoding output data provided from the compressed sample data, thereby generating an index unique to the data; An adder 42 for adding an index generated by the index decoder 41 and an index before one cycle; A limiter 43 for checking whether there is an overflow or an underflow in the data output from the adder 42 and outputting data determined according to the result of the check; A ROM 45 for storing a step size corresponding to each address in advance and inputting data output from the limiter 43 as an address and outputting a step size corresponding thereto; A shift register 46 for providing the step size output from the ROM 45 to the outside by shifting; And an inverter 47 for inverting the step size output from the shift register 46 and providing it to the adder 23 of the compressed sample generator. The semiconductor memory device according to claim 6, further comprising a register (44) connected between the limiter (43) and the ROM (45) and providing data output from the limiter (43) Adaptive differential pulse code modulation and compression circuit. 7. The apparatus of claim 6, wherein the prediction data generator A compressed sample decoder 55 for decoding the output data provided by the compressed sample output unit and outputting the result; A register 5154 for sequentially inputting a step size output from the shift register 46 of the step size generator and holding the step size at the output stage; An adder 56 for selecting and adding one output stage data of the register 5154 based on the decoding result outputted from the compression sample decoder 55 and outputting the result; An exclusive OR operation for performing an exclusive OR operation on the data output from the adder 56 and the maximum valid bit of the output data provided by the step size output unit and providing the result of the operation as predictive data to the difference generator, Unit (57).