KR100585637B1 - Video compression circuit - Google Patents

Abstract

The present invention relates to a technology for compressing and storing an image generated in the decoding process and decompressing it when necessary to reduce the capacity of an external memory required in the decoding process of MPEG used for various video transmission. An object of the present invention includes: a first error detector (11) for predicting next pixel data according to sequentially input pixel data (PD) and obtaining a difference between the predicted data and actual data; A bit size determiner 12 which receives the output signal of the first error detector 11 and determines the number of bits that can be used in each column based on the sum of the maximum prediction error values; A second error detection unit (13) which sequentially reads pixel data from the block memory (15) to predict the next pixel, and indicates the prediction error as the number of bits output from the bit size determination unit (12); A pack for arranging and outputting the predicted error value calculated by the second error detector 13 into a size of 1 byte that can be stored in the memory at one time according to the number of bits of information output from the bit size determiner 12 (14); This is achieved by a decoder that separately supplies bytes read sequentially from memory into the block initial pixel value, the number of bits for the maximum prediction error of each column, and the prediction error value of each pixel.

Description

Video compression circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology that can reduce the amount of external memory required in the decoding process of MPEG (MPEG), which is in the spotlight for various video transmission, and particularly, compresses an image generated in the decoding process. The present invention relates to an image compression circuit that is stored and decompressed when necessary.

Conventional MPEG decoders are intended to store first I-pictures, P-pictures, and B-pictures, and a method of reducing data amount by 30% by using optimization for B-pictures has been proposed. In addition, a decoder having a specific type of memory for a B-picture is provided inside the decoder, and a decoder that does not store B-picture data exists in the external memory. However, this type of decoder has an external memory of a capacity that substantially depends on the screen resolution since at least the data of the I-picture and the P-picture should be stored in the external memory.

Several decoders using image compression have been developed as a means to solve this problem. The decoder includes a compression / decompression circuit between the MPEG decoder core and the memory.

Since the B-picture is not used as a reference picture in the MPEG decoder, it does not need to be stored in an external memory, and only the data generated by the B-picture generation is transmitted to the display apparatus. B-pictures are created in 8 by 8 pixels, which does not match the raster scan order that appears on the screen.

Accordingly, the 8 × 8 blocks that are sequentially generated may be buffered and transmitted to the display device so as to be suitable for the sequential scanning order. Such a circuit is called a “macroblock to raster scan” circuit. This circuit simply consists of a buffer memory and a control circuit for the operation described above, the buffer memory having a size of 8 x N bytes. Where N is the number of macroblocks per scan

There are many ways to reduce the capacity of external memory by performing image compression. However, in most cases, an adaptive differential pulse code modulation (ADPCM) and an additional encoding method are used to simplify the structure of the hardware. Known still image compression algorithms are used.

Algorithms that show excellent compression ratios may be used, but due to problems in hardware implementation, they are difficult to use unless they are hardware only for image compression. In addition, these algorithms have the advantage of lossless compression, but because they have different compression ratios for different still images, they cannot be used in fields with limited memory resources.

On the other hand, the encoding method using ADPCM has the advantage of obtaining a constant compression ratio, but has the disadvantage of lossy compression.

As described above, in the prior art, when the compression is not used, a large capacity external memory is required, thereby increasing the cost of the system. In addition, in the compression method using ADPCM or the like, encoding is performed using the same number of bits in all the pixels in a block, which causes a problem of causing an error in the quantization process due to wasting bits or lacking in representing one pixel.

Accordingly, an object of the present invention is to reduce the capacity of an external memory through image compression when storing image data in an external memory, and to predict pixel data and encode the information to have a variable bit size. In providing.

1 is a block diagram showing an embodiment of an encoder in an image compression circuit for achieving the object of the present invention, as shown here, predicts the next pixel data according to the sequentially input pixel data (PD) A first error detector (11) for obtaining a difference between the predicted data and the actual data; A bit size determiner 12 which receives the output signal of the first error detector 11 and determines the number of bits that can be used in each column based on the sum of the maximum prediction error values; A second error detection unit (13) which sequentially reads pixel data from the block memory (15) to predict the next pixel, and indicates the prediction error as the number of bits output from the bit size determination unit (12); A pack for arranging and outputting the predicted error value calculated by the second error detector 13 into a size of 1 byte that can be stored in the memory at one time according to the number of bits of information output from the bit size determiner 12 It consisted of (14).

FIG. 2 is a block diagram showing an embodiment of a decoder in an image compression circuit for achieving the object of the present invention. As shown therein, information related to block information is sequentially detected from compressed image data CP. Unpack (UNPACK) (21) for detecting each bit in the data input in units of 1 byte from the number of bits of information and rearranged to the size of 8 bits; A bit size determiner 22 which receives the output signal of the unpack 21 and determines the number of bits that can be used in each column based on the sum of the prediction error maximum values; The decompression unit 23 outputs the decompressed pixel DP by accumulating prediction error values sequentially input from the bit size determination unit 22.

Referring to Figure 3 attached to the operation of the present invention configured as described above in detail as follows.

The encoder as shown in FIG. 1 stores the pixel data PD sequentially input in the internal buffer memory, that is, the block memory 15. At this time, the first error detection unit 11 receives the pixel information from the pixel data PD. The prediction is performed to find the difference between the predicted data and the actual data, and the compression is started from the first error detection unit 11.

In the prediction algorithm used by the first error detector 11, when the information to be predicted is p '(x, y) and the original data is p (x, y), p' (x, y) = { p (x, y-1) + p (x-1, y)} / 2. As a result, the output of the first error detection unit 11 is | p (x, y) -p '(x, y) | = | p (x, y)-(p (x, y-1) + p (x-1, y)) / 2 |

The bit size determiner 12 receives the output signal of the first error detector 11 and compares the prediction error occurring in each column and | p (x, y) -p '(x, y) | The maximum prediction error for each column is found. The eight maximum prediction error values obtained through this comparison process are converted into the minimum number of bits for indicating the maximum prediction error by the bit size calculator 12E.

For example, when the maximum prediction error occurring in any column is "00000100", it may represent any prediction error occurring in one column using at least 3 bits. In this case, the bit size determination unit 12 turns " 00000100 " at the comparator 12D stage, outputs " 011 " at the bit size calculation unit 12E, and stores the result in the register unit 12F.

The eight maximum prediction errors in each column are added together by the adder 12H, which is the number of bytes needed to represent one block. Therefore, if this number is larger than the memory size allocated to one image block, compression problems will occur.

As a result, in order to compress and store one image block in a predetermined memory space, the number of bits representing information of each column is determined based on the total number of bytes. The number of bits allocated to the data of each column can be obtained as follows.

Number of bits allocated = Maximum number of prediction error bits-(Total bytes-28) / 8

Here, 28 may be any value, and example 28 is a value for obtaining a 2: 1 compression ratio.

Next, the actual compression coding is started by the second error detection unit 13. The second error detector 13 sequentially reads pixel data from the block memory 15 to predict the next pixel, and expresses the prediction error as the number of bits output from the bit size determiner 12 to pack 14. To the () side.

The transformed prediction error value is then added to the prediction value and stored at that location in the block memory 15 so that it can be used for prediction of data of another pixel.

The pack 14 simply arranges and outputs the variable bit size data output from the second error detector 13, the number of bits for the maximum prediction error of each column, and the first pixel value of the block in units of 1 byte. do.

On the other hand, the decoder as shown in Figure 2 serves to separately supply the sequential bytes read from the memory as the block initial pixel value, the number of bits for the maximum prediction error of each column, the prediction error value of each pixel. The bit size determiner 22 performs the same role as that of the encoder. The decompression unit 23 accumulates the prediction error values sequentially input and outputs the pixel DP of the form in which the compression is finally decompressed. The row buffer 23 is used to store one column information previously input in order to implement a prediction algorithm in the decompression unit 23.

3 illustrates an example in which an 8 × 8 input block is compressed by 2: 1 and stored.

In the above description, the first error detection unit 11 uses only two pixels on the upper left side to predict the pixel data. However, an improved prediction circuit may be used as necessary. In addition, by designing the bit size determiner 12 as an FSM, it is possible to more dynamically allocate the number of allocated bits in each column. In addition, by allowing the bit size determination unit 12 to input the reference value of the sum of bits from the outside, another compression ratio can be obtained as necessary.

The image compression circuit of the present invention can be used in not only the compression storage of the reference data of the MPEG decoder but also all the circuits storing the purified images in the memory.

As described in detail above, the present invention predicts pixel data when storing image data required by an MPEG decoder in an external memory and encodes the information to have a variable bit size, thereby reducing the capacity of the external memory by 1/2. It is effective in minimizing quantization error by making more efficient use of finite memory bits.

1 is an exemplary block diagram of an encoder in an image compression circuit according to the present invention;

2 is an exemplary block diagram of a decoder in an image compression circuit according to the present invention;

Figure 3 is an exemplary view showing a form in which the 8 × 8 input block is 2: 1 compressed by the present invention.

*** Description of the symbols for the main parts of the drawings ***

11: first error detection unit 12, 22: bit size determination unit

13: 2nd error detection unit 14: Pack

15: block memory 21: unpack

23: kidney

Claims (5)

A first error detector for predicting the next pixel data according to sequentially input pixel data to obtain a difference from the actual data; A bit size determiner which receives the output signal of the first error detector and determines the number of bits that can be used in each column based on the sum of the maximum prediction error values; A second error detection section for sequentially reading pixel data from the block memory to predict the next pixel, and indicating the prediction error as the number of bits output from the bit size determination section; A pack for arranging prediction error values calculated and output by the second error detector in units that can be stored in a memory at one time according to the number of bits output by the bit size determiner; And a decoder configured to separately supply bytes read sequentially from the internal memory of the pack into a block initial pixel value, a number of bits for the maximum prediction error of each column, and a prediction error value of each pixel. The image compression circuit of claim 1, wherein the first error detection unit is configured to use two pixels on the left side and the top side to predict pixel data. 2. The apparatus of claim 1, wherein the bit size determination unit comprises: a comparator for obtaining a maximum value of prediction errors occurring in each of eight columns; And a memory for storing eight prediction error maximum values. The video compression circuit as claimed in claim 1, wherein the bit size determining unit is configured to obtain the number of bits allocated to the data of each column as follows. Number of allocated bits = maximum predicted error bits- (total bytes-value to obtain compression rate) / number of columns Here, the maximum number of prediction error bits is the minimum number of bits for indicating the maximum prediction error, and the total number of bytes is the number of bytes for compressing and storing one image block in a predetermined memory space. The unpack according to claim 1, wherein the decoder detects information related to block information from sequentially input compressed image data, detects each bit in data input in units of 1 byte from the number of bits, and rearranges the bit into 8 bits. and; A bit size determiner which receives the output signal of the unpack and determines the number of bits that can be used in each column based on the sum of prediction maximum values; And an expansion unit configured to accumulate prediction error values sequentially input from the bit size determination unit and output a decompressed pixel.