KR19980014202A - Output Buffer Type Asynchronous Transfer Mode Switching Device Using Bypass Link - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Output buffer type asynchronous transfer mode switching device.

2. The technical problem to be solved by the invention

When the ATM switching device is NxN, the cell address is divided into n partial addresses of the same size and sequentially routed by partial addresses. When a collision occurs, an output buffer using a bypass link that can be rerouted from the partial address when a collision occurs. To provide a type ATM switching device.

3. Summary of Solution to Invention

In the output buffer type ATM switch network, a bypass link is provided between switching stages to divide the output address of the input cell into a partial address of an arbitrary size. Outputs unchanged, cells that are bypassed and occupied by normal link different from the partial address are outputted with the pointer value as initial value, and when the cell is output to the next switching stage through the target normal link, pointer value is returned. When the pointer value reaches 0, it is output through the output buffer of the corresponding output terminal.

4. Important uses of the invention

Used in switching devices.

Description

Output Buffer Type Asynchronous Transfer Mode Switching Device Using Bypass Link

The present invention relates to an output buffer type asynchronous transfer mode (ATM) switching device using a bypass link.

1 is a block diagram of a general NxN size output buffer type ATM switch device, in which '11' represents an input terminal, '12' represents a routing network, '13' represents an output buffer, and '14' represents an output terminal.

A typical output buffer type ATM switching device routes a plurality of cells inputted to the input terminal 11 to the corresponding output terminal according to the address of each cell. The input terminal 11 receives the cells from an external line and routes them inside the switch. This function converts the output to the correct form.

The routing network 12 performs the function of routing the cells converted in the input terminal 11 to the corresponding output terminal according to the address of each cell, and the output buffer 13 is one output terminal input from the routing network 12. The cells arriving at the same time are buffered and output to the output terminal 14, and the output terminal 14 performs a function of converting the cells to be suitable for external transmission.

2 is a block diagram of a Tandem Banyan switching device, which is a conventional output buffer type switching device, in which '21' is an input terminal, '22' is a banyan network, '23' is an output buffer, and '24' is an output terminal, respectively. Indicates.

Tandem Banyan switching device is connected to the output of K banyan network 22 and each banyan network 22 connected in a line to route the cells converted at the input terminal 21 to the corresponding output terminal according to each cell address. It consists of an output buffer 23 for storing routed cells and an output stage 24 connected thereto.

The Tandem Banyan switch routes the input cells in the first banyan network 22. In the banyan network 22, there may be cells that could not be routed to the destination due to collisions between the cells. The Tandem Banyan switch indicates that there was a collision by sending these cells to the other exit of the banyan network 22. .

In the second and subsequent banyan network 22, only the cells that do not reach the destination due to collision in the front banyan network 22 are inputted and routed, and the cells that have reached the destination are output to the output buffer 23. Save it.

The output buffer type ATM switching device has better performance than the input buffer type ATM switching device or the shared buffer type switching device, but has a problem in that the amount of hardware required to implement the switch is large.

In particular, Tandem Banyan switching devices cannot start routing again immediately after a collision, when a cell routed in the banyan network 22 cannot reach its original destination due to a collision, it loses all routed processes prior to the collision and always Since it must be routed from, there is a problem that reduces the overall performance.

Accordingly, the present invention devised to solve the above-mentioned problems of the prior art divides the cell address into n partial addresses of the same size when the ATM switching device is NxN, and sequentially routes by partial addresses when a collision occurs. An object of the present invention is to provide an output buffered ATM switching device using a bypass link that can be rerouted from a partial address when a collision occurs.

1 is a structural diagram of a typical output balanced ATM switching device,

2 is a structural diagram of a conventional Tandem banyan switching device,

3 is a structural diagram of an output buffer type ATM switching device using a bypass link according to the present invention;

4 is a structural diagram of a switching module according to the present invention;

Explanation of symbols on the main parts of the drawings

31: switching module 32,33: switching stage

34,35: output buffer 41: input regulator

42: shuffle exchange network 43: adder

44: demultiplexer 45: normal output regulator

46: bypass output regulator

Looking at the configuration of the present invention for achieving the above object, the present invention forms a plurality of switching stages using a plurality of switching modules having any p + b input stage, any p normal output stage and b bypass output stage The switching module at the front end is connected to all the switching modules at the rear end through p normal links, and is connected through any b bypass link between any k-th switching module at the front end and any k-th switching module at the rear end. From the nth switching stage to the mth switching stage, a plurality of output buffers are connected according to the output address to form a switching network, the output address of the input cell is divided into partial addresses of arbitrary sizes, and the switching is performed. Depending on the pointer to the part that should be routed in the module, due to the collision between the cells to be output in the same path during routing, the destination path will not be output. Cells that cannot be sent are output to the next switching stage without changing the pointer value through the bypass link, and all the bypass links are occupied by other cells, and cells output to the normal link different from the partial address have the pointer value as the initial value. If the cell is output to the next switching stage through the target normal link, the pointer value is decreased by one and the pointer is finally outputted through the output buffer of the corresponding output terminal.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

3 is a structural diagram of an output buffer type ATM switching device using a bypass link according to the present invention, in which '31' is a switching module, '32' is a first switching stage, '33' is an m switching stage, and '34' 'Represents the first output buffer, and' 35 'represents the Nth output buffer.

The switching module 31 has an arbitrary p + b input stage, any p normal output stage numbered from 0 to p-1 and any b bypass output stage, connected to the input stage p-1 to the input stage p-1. Route the cells according to the output address of each cell. By dividing into) equal parts, the value of pointer Fcp is set to n to point to the highest part address, and then routed to the corresponding normal output terminal according to the part address indicated by this pointer Fcp.

Here, cells that cannot be output to the destination path are first outputted to the bypass output terminal due to collision between cells to be output to the same path during routing, and even the bypass output terminal is routed to another normal output terminal when all the other output cells are occupied by other cells. Therefore, the value of the pointer (Fcp) that points to the next partial address to be routed is decreased by '1' when the cell reaches the destination normal output, and the cell routed to the bypass output is left as it is. The pointer Fcp of the cell transmitted to the output terminal is changed back to the initial value n and output at each output terminal.

The first switching stage 32 is composed of arbitrary N / p switching modules to receive and route cells from the N input terminals from the input terminal 0 to the input terminal N-1.

Like the first switching stage 32, the m-th switching stage 33 is composed of arbitrary N / p switching modules and receives the cells output from the previous switching stage, and thus the routing is not terminated because the target output stage has not yet been reached. Cells which have not been routed according to the corresponding partial address indicated by the pointer of the cell are sent to the output buffer 35, and all of the cells which have not been destroyed are destroyed.

The path link connects two successive switching stages, and by connecting the normal output stage at the front stage and the input stage at the rear stage, it becomes the transmission path of the cells that reach the target output stage without collision at the front stage. From the 1 switching module to the N / p switching module, when the number 0, 1, 2, .... ) Is connected to the input terminal of the switching module.

The bypass link connects any two consecutive switching stages. By connecting the bypass output stages of the k (1≤k≤N / p) th switching module at the front stage with the input stage of the kth switching module at the rear stage, Allows the rerouting of the partial address portion where the collision occurred at the next stage of cells that were not routed to the normal output due to the collision.

The first output buffer 34 is connected to the 0th normal output terminal from any nth switching stage to any mth switching stage 33 to receive a cell, and among the input cells, only the cell having the output address 0 is received. Accept and store in a buffer in a FIFO fashion.

Cells input to the output buffer are delayed for a predetermined time according to the output switching stage, and cells simultaneously input to the switch are simultaneously stored in the output buffer and output one by one in the order in which they are stored.

The Nth output buffer 35 is connected to an N-1 normal output terminal from an nth switching stage to an mth switching stage 33 to receive a cell, and receives an input address N-1 of the input cells. Only cells that have them are accepted and stored in a buffer in a FIFO manner.

4 shows a structural diagram of a switching module according to the present invention.

The switching module consists of a plurality of input regulators 41 and 2x2 crossbars that receive only cells that have not yet reached their destination output and calculate and output routing markers for routing from the partial address indicated by the pointer (Fcp) to be routed. A plurality of stages are provided to route the outputs of the plurality of input regulators 41 according to the routing indicators, and when two cells are output to the same output stage in one crossbar, one is refracted to the other output to the cells. Display the shuffle switching network 42 and the cells routed from the shuffle switching network 42, which routes the cells to the corresponding output terminal, and calculates the number of collided and refracted cells among the input cells. Compute and output the address of the bypass output to be used, or bypass output to other refracted cells If two are allocated, the other cells input the cells from the demultiplexer 44 and the demultiplexer 44 which demultiplexes and outputs the cells inputted from the flow adder 43 to the normal output stage. The value of pointer Fcp that indicates the partial address to be routed next to the cell that has been received and routed normally to the destination output terminal is decreased by 1, and the pointers of cells that are refracted by collision but output to the normal output terminal are changed to the initial value n. By reducing the cells that have been refracted by the collision to the normal cell to the next stage or the output buffer to the normal output regulator 45 and the demultiplexer 44 receives the cells from the demultiplexer 44 and outputs the bypass link 46 It is provided.

Looking at the operation of the switching module configured as described above are as follows.

The first input coordinator receives only the cells that have not yet reached the destination output stage and obtains the routing beacon required by the shuffle switching network from the corresponding partial address j according to the value of the pointer (Fcp) indicating the cell's output address and the partial address. Calculate accordingly, write the result in the corresponding field of the cell, and output it to the 0 th input terminal of the shuffle switching network 42.

The p + b input regulator receives only cells that have not yet reached the destination output terminal and is required by the shuffle switching network 42 from the corresponding partial address j according to the value of the pointer Fcp indicating the output address and the partial address of the cell. Routing markers , at (i = p + b-1) If + p + b 2p = + p + b as routing marker, or Is calculated as a routing mark and recorded in the corresponding field of the cell, and then output to the p + b-1th input terminal of the shuffle switching network 42.

The shuffle switching network 42 constitutes one stage with (p + b) / 2 2x2 crossbars, and includes [log (p + b)] stages such that i + 1 (i = 0, 1, ... p + b-1) Input J (output of input regulator 41) And the output I of the crossbar of each stage is the input of the crossbar of the next stage. And routing cells according to the routing beacon at the input coordinator, i.e. according to the most significant bit of the routing beacon at the first end and according to the next higher bit of the beacon at the next end, When two cells in one crossbar are going to the same output, one is refracted to the other output to indicate that the cell is refracted and routed to the corresponding output stage and output to the flow adder 43 at the last stage.

The first adder is connected to an output terminal 0 of the shuffle exchange network 42 and a second adder, and receives a value of a pointer indicating an unassigned bypass exit input from a cell that has passed the shuffle exchange network 42 and the second adder. When the cell is refracted due to collision and the value of the pointer is smaller than b, the address of the bypass output terminal indicated by the pointer of the cell is allocated and output to the first demultiplexer. Otherwise, the cell is output to the first demultiplexer as it is.

The p + b adder is connected to the p + b th output of the shuffle exchange network 42 and inputs a value 0 of a pointer indicating an unassigned bypass output stage when a cell refracted by collision in the shuffle exchange network 42 is input. Assigns to the first cell and outputs it to the first bypass output regulator, and increases the value of the pointer by 1 to output to the p + b-1 adder. Output with b-1 adder.

The first demultiplexer is connected to the first adder and the cell inputted from the adder is refracted, and if the address of the assigned bypass output terminal is smaller than b, the first demultiplexer outputs to the output regulator of the assigned address, and otherwise to the first output regulator. .

The p + b demultiplexer is connected to the p + b adder and outputs the cell to the corresponding bypass output regulator according to the address of the bypass output terminal allocated by the cell input from the adder.

The first normal output regulator is connected to the first demultiplexer and receives a cell. The cell normally routed according to the partial address decreases the value of the pointer (Ecp) indicating the partial address to be routed in the next stage and outputs it by one. The cell refracted by the collision will initialize the value of the pointer Fcp to n and output it.

The pth normal output regulator is connected to the pth demultiplexer and receives a cell. The cell normally routed according to the partial address outputs the value of the pointer (Ecp) decremented by 1 indicating the partial address to be routed in the next stage. The cell refracted by the collision will initialize the value of the pointer Fcp to n and output it.

The first bypass output regulator is connected to all the demultiplexers of the preceding stage and receives the cell assigned to the address 0 of the bypass output stage from the adder and outputs the cell to the next stage.

The b-th bypass output regulator is connected to all the demultiplexers of the preceding stage, and receives the cell assigned to the address b-1 of the bypass output stage from the adder and outputs the cell to the next stage.

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

The present invention constructed and operated as described above divides the cell address into n partial addresses having the same size and sequentially routes the partial addresses with respect to cells inputted from several N input terminals. It can be rerouted from the partial address at the time of occurrence to maximize the performance of the system.

Claims (2)

Multiple switching modules are formed using multiple switching modules with any p + b input stages, any p normal output stages and b bypass output stages, with the switching module at the front stage having all the switching modules at the rear stage and the p normals. Connected via a link, between any k th switching module at the front end and any k th switching module at the rear end, via any b bypass link, and output from any n th switching end to any m th switching end Multiple output buffers are connected according to addresses to form a switching network. The output address of the input cell is divided into partial addresses of arbitrary size, and the same path is routed according to the pointer indicating the part to be routed in the switching module. Cells that cannot be output to the destination path due to collisions between cells to be output to the next switch are switched to the next switch without changing the pointer value through the detour link. All the bypass links are occupied by other cells and output to normal links that are different from the partial address. The cells are output with the pointer value as the initial value. Output buffer type asynchronous transfer mode switching device configured to output through the output buffer of the output terminal when the pointer value reaches 0 when the output is reduced by 1 when the output to the output. The method of claim 1, The switching module, A plurality of input adjusting means (41) for receiving only a cell which has not yet reached the destination output stage and calculating and outputting a routing mark necessary for routing from a partial address indicated by a pointer (Fcp) to be routed of the cell; A plurality of stages composed of 2x2 crossbars are provided to route the outputs of the plurality of input adjusting means 41 according to a routing mark, and when two cells are output to the same output stage in one crossbar, one is refracted to the other output stage. A shuffle exchange means 42 for displaying this on a cell and routing the cells to a corresponding output terminal; The cells routed from the shuffle exchanger 42 are input to calculate the number of collided and refracted cells among the input cells, and accordingly, the address of the bypass link to output the refracted cells is output or the bypass link is different. A plurality of flow adding means 43 for outputting the normal cells when all of the refracted cells are allocated; A plurality of demultiplexing means (44) for demultiplexing and outputting cells inputted from the plurality of flow adding means (43); Receives the cells from the plurality of demultiplexing means 44 and decreases the value of the pointer Fcp indicating the partial address to be routed next to the cell that is normally routed and reaches the destination output terminal by 1, and is refracted by collision but is normal. Pointers of the cells output to the output stage is a plurality of normal output adjusting means 45 for changing to the initial value n to reduce the cell indicating that the refracted by the collision to a normal cell to transmit to the next stage or the output buffer; And Output buffer type asynchronous transfer mode switching device characterized in that it comprises a plurality of bypass output adjusting means 46 for receiving the cells from the demultiplexing means 44 and outputs them to the bypass link.