JPH06216932A - Atm switch - Google Patents

Abstract

PURPOSE:To give a uniform queuing time to cells by giving cell control information of a cell buffer A, which is provided at one intersection, to each cell sent from the buffer A to a cell buffer B which is provided at another intersection above one intersection and comparing cell control information of buffers A and B to set the connection order. CONSTITUTION:For the purpose of dividing a load among first cell buffers Bu 111 to 1nn in consideration of the unevenness of load among input lines 211 to 21n, the operation is performed as follows; the number of cells stored in buffers 111 to 1nn at the time of reading out each cell from buffers 111 to 1nn is given as cell control information to this cell, and the cell read out from buffers 111 to 1nn is transferred to second buffers 311 to 3nn before respective intersections, and the number of stored cells given to this cell is extracted and is compared with the number of cells stored in buffers 111 to 1nn to set the connection order. Thus, buffers 111 to 1nn which the number of cells stored is larger are preferentially connected to outgoing lines 221 to 22n, and the increase of the number of stored cells is suppressed to give a uniform queuing time to cells.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention finds use in digital telecommunications switching equipment. In particular, it relates to a technique for improving throughput of an ATM (asynchronous transfer mode) switching device.

[0002]

2. Description of the Related Art A having N incoming lines and M outgoing lines
As a TM switch, there is a one-stage matrix switch in which a cell buffer is arranged at each intersection of N × M matrix switches. A conventional example will be described with reference to FIGS. 4 and 5.
FIG. 4 is a block diagram of a conventional device. FIG. 5 is a diagram showing a cell buffer and a multiplexing control circuit of a conventional device.

A conventional device will be described as an N × N matrix switch as shown in FIG. Incoming lines 211-2
Cells that are asynchronously input from 1n are output lines 221 to 2
2n multiplexed and output. Incoming line 211 at this time
Contention control between cells input from ~ 21n is performed. As a result, cells that have missed the transmission opportunity are not discarded, so that the incoming lines 211 to 21n and the outgoing lines 221 to 22n are not discarded.
The cell buffers 111 to 1nn are provided at each intersection with. Input cells from each of the incoming lines 211 to 21n are sorted by an address filter (not shown), and the corresponding cell buffer 1
It is temporarily stored in 11 to 1nn.

In this ATM switch, the outgoing line 221
The cell multiplexing to 22n is arranged at each intersection of the incoming lines 211 to 21n and the outgoing lines 221 to 22n, and the outgoing lines 221 to 2 are arranged between the distributed cell buffers 111 to 1nn.
The cell read order to 2n is determined, and outgoing lines 221 to 22
It is realized by performing cell multiplexing on n.

As shown in FIG. 5, cell buffers 111 to 111
1nn indicates a multiplex request signal to the multiplex control circuits 71 to 7n when the cells exist in each buffer.
Notify via nn. The multiplex control circuits 71 to 7n poll the cell transmission right 51, which is a multiplex request signal of each cell buffer 111 to 1nn, in a predetermined order, and check the first cell of the cell buffers 111 to 1nn that generated the cell transmission right 51. One cell is connected to the outgoing lines 221 to 22n. For example, when the cells of the cell buffer 111 are connected last time, the cell buffers 112 to 1 which are first accumulating the cells after the cell buffer 112 and generate the connection request.
The operation of connecting nn to the outgoing lines 221 to 22n is repeated. By this operation, the plurality of cell buffers 111 to 1
The cells from nn can be multiplexed and output.

Next, another conventional example will be described with reference to FIGS. FIG. 6 is a block diagram of another conventional device. FIG. 7 shows a multiplex control circuit 411 to 11 of another conventional device.
It is a figure which shows 4nn. FIG. 8 is a diagram showing an output situation of the conventional device. In the conventional device shown in FIG. 6, multiplexing control circuits 411 to 4nn are provided in the cell buffers 111 to 1nn, respectively. FIG. 7 shows multiple control circuits 411-4.
nn connections are shown. The token circulates through the internal wirings 41 to 4n. This token includes the cell transmission right 51. The multiplex control circuits 411 to 4nn that have received the cell transmission right 51 are
If there is a cell to be transmitted in the cell buffers 111 to 1nn managed by 4nn, the cell buffers 111 to 1nn
From the first cell to the outgoing lines 221 to 22n.
If there is no cell to be transmitted to the cell buffers 111 to 1nn, the token including the cell transmission right 51 is immediately circulated to the next multiplex control circuits 411 to 4nn. By performing this operation in each of the multiplexing control circuits 411 to 4nn, cells from the plurality of cell buffers 111 to 1nn can be multiplexed and output.

As shown in FIG. 8, cell buffers 111 to 111
The cells accumulated at the head of 1n4 are outgoing lines 221 to 22n
, The cells from the second cell onward are sequentially multiplexed.

[0008]

In such multiplex control to the outgoing line of the ATM switch, polling by the central control means of the cell buffer accumulating cells or
By circulating the cell transmission right among the multiplexing control circuits, cell multiplexing is realized by avoiding cell discard due to cell collision at the time of outgoing line multiplexing. However, in such a scheme, when cells are arriving at multiple inputs on average, there is no problem,
It is necessary to prepare a large-scale memory in the corresponding cell buffer to suppress cell discard under the traffic condition where the input is biased to a specific incoming line. In order to guarantee a sufficiently low cell loss rate for arbitrary traffic, the cell buffer needs to have a very large buffer capacity.

When applied to an ATM switch operating at high speed, the transfer time of the connection request signal and cell transmission right between the multiplex control circuit and each cell buffer or the transfer time of the cell transmission right between a plurality of multiplex control circuits. Is a factor and causes a problem in performing high-speed cell multiplexing with control.

The present invention has been made against such a background, and the arrival of cells biased to a specific incoming line is determined by using the memory capacity evenly arranged on each incoming line. It is an object of the present invention to provide an ATM switch that can be processed so as to maintain fairness. Another object of the present invention is to provide an ATM switch that can omit the control signal transfer path and shorten the transfer time.

[0011]

SUMMARY OF THE INVENTION The present invention comprises a plurality of incoming lines to which cells arrive and a plurality of outgoing lines to which cells are sent out.
A first cell buffer, which is provided at each intersection of the incoming line and the outgoing line and temporarily stores cells waiting to pass through the intersection, and controls cell transmission to the outgoing line of the first cell buffer. An ATM switch having a multiplex control circuit.

Here, a feature of the present invention is that a second cell buffer for temporarily accumulating cells that have passed through an upstream intersection on the outgoing line of each intersection is provided for each of the intersections. The cell accumulated in the cell buffer is provided with means for giving cell control information in the first cell buffer to which the cell is transmitted, and the multiplex control circuit includes a first cell buffer connected to the same intersection and Controlling transmission of cells according to the cell control information of the first cell accumulated in the second cell buffer and the cell control information of the cell transmitted first from the first cell buffer for the second cell buffer There is a means to do it.

[0013] It is preferable that the means for adding includes a means for adding, as cell control information, information on the number of cells accumulated in the first cell buffer of the cell transmission source and / or the cell transmission time.

[0014]

The number of accumulated cells remaining in the first cell buffer at that time and / or the cell transmission time is added to the cells transmitted from the first cell buffer as cell control information.

This cell is accumulated in a second cell buffer downstream of the matrix switch in the outgoing line direction, and this cell control information is compared with the number of accumulated cells in the first cell buffer at the same position downstream. As a result, the one with the larger number is preferentially sent out further downstream.

By repeating this operation up to the outgoing line terminal, the cells having a large number of accumulated cells in the first cell buffer are preferentially transmitted to the outgoing line and the number of cells biased toward the incoming line is determined. Can be treated evenly.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

According to the present invention, N incoming lines 2 from which cells arrive
11 to 21n and N outgoing lines 221 to which cells are sent
22n, and the incoming lines 211 to 21n and outgoing line 2
A first cell buffer 1 provided at each intersection of 21 to 22n and temporarily storing cells waiting to pass through this intersection.
11 to 1nn and the first cell buffers 111 to 1n
ATM switch having multiple control circuits 411 to 4nn for controlling cell transmission to n output lines 221 to 22n.

Here, the feature of the present invention is that second cell buffers 311 to 3nn for temporarily accumulating cells passing through the upstream intersections on the outgoing line of each intersection are provided for each intersection. For the cells accumulated in the second cell buffers 311 to 3nn, means for giving the cell control information in the first cell buffers 111 to 1nn to which the cells are transmitted is provided in the first cell buffers 111 to 1nn, The multiplex control circuits 411 to 4nn use the second cell buffer 3 for the first cell buffers 111 to 1nn and the second cell buffers 311 to 3nn connected to the same intersection.
It includes means for controlling transmission of cells according to the cell control information of the first cell accumulated in 11 to 3 nn and the cell control information of the cell transmitted to the earliest of the first cell buffers 111 to 1 nn. .

The assigning means is configured to include means for assigning the cell accumulation number of the first cell buffers 111 to 1nn of the cell transmission source as cell control information.

Next, the operation of the embodiment of the present invention will be described with reference to FIG. FIG. 2 is a diagram showing a configuration between the incoming lines 211 to 21n and the outgoing line 221. Here, in order to make the description easy to understand, a cell input from the input line 211 and output to the output line 221 will be described. Incoming line 21
The cells input from 1 and output to the output line 221 are accumulated in the first cell buffer 111. Multiplex control circuit 41
When a token including the cell transmission right 51 arrives at 1, the first cell buffer 111 transmits the earliest cell.

At this time, information on the number of cells accumulated in the first cell buffer 111 at the transmission timing is added to this cell. The multiplexing control circuit 411 extracts the information on the cell accumulation number of the earliest cell transmitted from the first cell buffer 111 and the information on the cell accumulation number accumulated at the head of the second cell buffer 311. And compare. The second cell buffer 3 located on the most upstream side on the outgoing line 221
There is no cell to be compared with 11, and the cell transmitted from the first cell buffer 111 is the next intersection point downstream of the outgoing line 221 of the matrix switch network by the selector 511 controlled by the multiplex control circuit 411. Selector 5
It is stored in the second cell buffer 312 provided in front of 12.

Here, the second cell buffer 311 is at the most upstream position on the outgoing line 221, and no cell is actually input here. Therefore, this second cell buffer 3
11 may be omitted. However, in consideration of expansion, the second cell buffer 311 is always provided as an empty buffer.

The cells transmitted from the first cell buffer 111 are compared with each other at each passing intersection for information on the number of accumulated cells which is cell control information. If the number of cells accumulated in the first cell buffer 111 is different from that of the other first cell buffers 112 to 112 ...
When it is the largest as compared with 11n, this cell is sequentially passed through the second cell buffer 312 → selector 512 → ... → second cell buffer 31n → selector 51n and connected to the outgoing line 221. In this way, the first cell buffer 1 in the selectors 511 to 51n provided at each intersection
11 and the read order of the cells stored in the second cell buffers 311 to 31n are determined by the cell control information given to each cell.

Next, cell competition control will be described with reference to FIG. FIG. 3 is a diagram showing the relationship between input cells and output cells. Here, in order to make the description easy to understand, the incoming lines 211 to 214 and the outgoing line 221 will be described. Cells are stored in the first cell buffer 111,
Cells are stored in the first cell buffer 112, cells are stored in the first cell buffer 113,
Cells are accumulated in the first cell buffer 114. Here, the cells are biased to the first cell buffer 113.

The token including the cell transmission right 51 is circulated in order from the multiplex control circuit 411. First, the multiplexing control circuit 411 compares the cell control information of the earliest cell of the first cell buffer 111 with the cell control information of the leading cell accumulated in the second cell buffer 311. In this case, since the second cell buffer 311 is located at the most upstream side in the direction of the outgoing line 221, it is always empty and there is no head cell to be compared. Therefore, the cell to which the information “1” of the cell accumulation number of the first cell buffer 111 is added as the cell control information is transferred to the second cell buffer 312 via the selector 511.

The cell transmission right 51 is transferred to the multiplex control circuit 412, and the multiplex control circuit 412 receives the first cell buffer 11.
2 is compared with the cell control information of the cell transmitted first, and the cell control information of the first cell, that is, the cell stored in the second cell buffer 312. The information of the cell accumulation number of the first cell buffer 111, which is the cell control information of the cell, is “1”, and the cell accumulation number of the first cell buffer 112 is also “1”. Here, the multiplexing control circuit 412
If both have the same number, the cell already transmitted from the first cell buffer 111 is prioritized. As a result, the cell is not sent from the first cell buffer 112, and the cell passes through the selector 512 and is transferred to the second cell buffer 313.

The cell transmission right 51 is transferred to the multiplex control circuit 413, and the multiplex control circuit 413 receives the first cell buffer 11.
3 is compared with the cell control information of the cell transmitted first, that is, the cell control information of the first cell stored in the second cell buffer 313, that is, the cell control information of the cell. The cell accumulation information of the first cell buffer 111, which is the cell control information of the cell, is “1”, and the cell accumulation number of the first cell buffer 113 is “5”. Here, the multiplexing control circuit 413
Gives priority to the transmission of cells from the first cell buffer 113. As a result, the cell becomes the second cell buffer 31.
3 is untransmitted, and the cell is the first cell buffer 11
3 through the selector 513 and the second cell buffer 3
Accumulated in 14.

The cell transmission right 51 is transferred to the multiplex control circuit 414, and the multiplex control circuit 414 is transferred to the first cell buffer 11.
4 is compared with the cell control information of the cell transmitted first, that is, the cell control information of the first cell stored in the second cell buffer 314, that is, the cell. The information on the cell accumulation number of the first cell buffer 113, which is the cell control information of the cell, is “5”, and the cell accumulation number that is the cell control information of the first cell transmitted to the first cell buffer 114 is It is "2". Here, the multiplexing control circuit 414 gives priority to the transmission of cells from the second cell buffer 314. As a result, the cell is not sent from the first cell buffer 114, and the cell of the second cell buffer 314 is sent to the outgoing line 221 through the selector 514.

The cell transmission right 51 is transferred to the multiplex control circuit 411 again.
However, since there is no cell in either the first cell buffer 111 or the second cell buffer 311, the cell transmission right 51 is immediately transferred to the multiplexing control circuit 412.

The multiplexing control circuit 412 stores the cell accumulation number, which is the cell control information of the cell transmitted first in the first cell buffer 112, and the cell control information of the leading cell accumulated in the second cell buffer 312. In comparison, in this case, there is no cell in the second cell buffer 312, and the cell passes through the selector 512 and is transferred to the second cell buffer 313. In the second cell buffer 313, the cell accumulated at the previous cell transmission timing and the cell transferred this time are simultaneously accumulated at this point.

The cell transmission right 51 is transferred to the multiplex control circuit 413, and the multiplex control circuit 413 receives the first cell buffer 11.
3 is compared with the cell control information of the cell transmitted first in 3 and the cell control information of the leading cell accumulated in the second cell buffer 313. The accumulated cell number, which is the cell control information of the cell that is transmitted first in the first cell buffer 113, is “4”, and the cell control information of the cell that is the head cell of the second cell buffer 313 is “1”. Therefore, the cell which is the head cell of the first cell buffer 113 is the selector 5
13 and is transferred to the second cell buffer 314.

The cell transmission right 51 is transferred to the multiplex control circuit 414, and the multiplex control circuit 414 is transferred to the first cell buffer 11.
4 is compared with the cell control information of the cell that is transmitted first, and the cell control information of the leading cell accumulated in the second cell buffer 314. The accumulated cell number, which is the cell control information of the first cell of the first cell buffer 114, is “2”, and the cell control information of the cell that is the head cell of the second cell buffer 314 is “4”. Therefore, the cells stored in the second cell buffer 314 are stored in the selector 514.
Is transmitted to the outgoing line 221.

The cell transmission right 51 is transferred to the multiplex control circuit 411 again.
However, since there is no cell in either the first cell buffer 111 or the second cell buffer 311, the cell transmission right 51 is immediately transferred to the multiplexing control circuit 412. However, here again, since there are no cells in the first cell buffer 112 and the second cell buffer 312, the cell transmission right 51 is immediately transferred to the multiplexing control circuit 413. The multiplex control circuit 413 is “3” which is the cell control information of the cell transmitted first in the first cell buffer 113.
And the cell control information “1” of the cell that is the leading cell accumulated in the second cell buffer 313.
As a result, the cell passes through the selector 513 and is transferred to the second cell buffer 314.

The cell transmission right 51 is transferred to the multiplex control circuit 414, and the multiplex control circuit 414 receives the first cell buffer 11.
The number of stored cells “2”, which is the cell control information of the cell to be transmitted first in 4, is compared with the cell control information “3” of the head cell of the second cell buffer 314. As a result, the cell passes through the selector 514 and is sent to the outgoing line 221.

The cell transmission right 51 is transferred to the multiplex control circuit 411 again.
To the multiplex control circuit 412 because there are no cells in the first cell buffer 111 and the second cell buffer 311.
12 and the second cell buffer 312 have no cells, so that they are transferred to the multiplex control circuit 413. The multiplexing control circuit 413 stores the number of accumulated cells “2”, which is the cell control information of the cell transmitted first in the first cell buffer 113,
The cell control information “1” of the leading cell accumulated in the second cell buffer 313 is compared. As a result, the cell that is the leading cell of the first cell buffer 113 is the selector 5
13 and is transferred to the second cell buffer 314.

The cell transmission right 51 is transferred to the multiplex control circuit 414, and the stored cell number "2" which is the cell control information of the cell transmitted first in the first cell buffer 114 and the second cell buffer 314. The cell control information “2” of the first cell of the above is compared. Here, the multiplexing control circuit 414 gives priority to the cell already transmitted from the first cell buffer 113 when both have the same number. As a result, the cell passes through the selector 514 and goes out the outgoing line 22.
Sent to 1.

The cell transmission right 51 is transferred to the multiplex control circuit 411 again.
Through 412 to the multiplex control circuit 413. The multiplex control circuit 413 stores the number of stored cells “1”, which is the cell control information of the cell transmitted first in the first cell buffer 113, and the cell control information “of the cell that is the head cell of the second cell buffer 313”. 1 ". Here, when both of the multiplex control circuits 413 have the same number,
Priority is given to cells already transmitted from the first cell buffer 111. As a result, the cell becomes the selector 513.
And is transferred to the second cell buffer 314.

The cell transmission right 51 is transferred to the multiplex control circuit 414, and the multiplex control circuit 414 is transferred to the first cell buffer 11.
The stored cell number “2”, which is the cell control information of the cell that is transmitted first in 4, is compared with the cell control information “1” of the cell that is the head cell of the second cell buffer 314. As a result, the cell that is the head cell of the first cell buffer 114 passes through the selector 514 and is sent to the outgoing line 221.

The cell transmission right 51 is transferred to the multiplex control circuit 411 again.
Through 412 to the multiplex control circuit 413. The multiplex control circuit 413 stores the number of stored cells “1”, which is the cell control information of the cell transmitted first in the first cell buffer 113, and the cell control information “of the cell that is the head cell of the second cell buffer 313”. 1 ". Here, when both of the multiplex control circuits 413 have the same number,
The cells already sent from the first cell buffer 112 are prioritized. As a result, the cell becomes the selector 513.
And is transferred to the second cell buffer 314. In the second cell buffer 314, the cell accumulated at the previous cell transmission timing and the cell transferred this time are simultaneously accumulated at this point.

The cell transmission right 51 is transferred to the multiplex control circuit 414, and the multiplex control circuit 414 is transferred to the first cell buffer 11.
The stored cell number “1”, which is the cell control information of the cell transmitted first in 4, is compared with the cell control information “1” of the head cell, which is stored in the second cell buffer 314. Here, the multiplexing control circuit 414 gives priority to the cell already transmitted from the first cell buffer 111 when both have the same number. As a result, the cell passes through the selector 514 and is sent to the outgoing line 221.

The cell transmission right 51 is transferred to the multiplex control circuit 411 again.
Through 412 to the multiplexing control circuit 413.
The multiplex control circuit 413 compares the cell storage number “1”, which is the cell control information of the cell transmitted first in the first cell buffer 113, with the cell control information of the leading cell of the second cell buffer 313. However, since there is no cell in the second cell buffer 313 at this point, the cell passes through the selector 513 and is transferred to the second cell buffer 314. In the second cell buffer 314, the cell accumulated at the previous cell transmission timing and the cell transferred this time are simultaneously accumulated at this point.

The cell transmission right 51 is transferred to the multiplex control circuit 414, and the multiplex control circuit 414 is transferred to the first cell buffer 11.
The stored cell number “1”, which is the cell control information of the cell that is transmitted first in 4, is compared with the cell control information “1” of the cell that is the head cell of the second cell buffer 314. Here, the multiplexing control circuit 414 gives priority to the cell already transmitted from the first cell buffer 112 when both have the same number. As a result, the cell is the selector 5
After passing through 14, the signal is sent to the outgoing line 221.

The cell transmission right 51 is transferred to the multiplex control circuit 411 again.
˜412 to 413, the data is transferred to the multiplex control circuit 414. The multiplexing control circuit 414 uses the first cell buffer 11
The cell accumulation number “1”, which is the cell control information of the cell that is transmitted first in 4, is compared with the cell control information “1” of the cell that is the head cell of the second cell buffer 314. Here, the multiplexing control circuit 414 gives priority to the cell already transmitted from the first cell buffer 113 when both have the same number. As a result, the cell is the selector 5
After passing through 14, the signal is sent to the outgoing line 221.

The cell transmission right 51 is again transferred to the multiplex control circuit 411.
˜412 to 413 to the multiplex control circuit 414. The multiplexing control circuit 414 uses the first cell buffer 114.
The cell storage number “1”, which is the cell control information of the cell that is transmitted first, is compared with the cell control information of the first cell of the second cell buffer 314. At this point, the second cell buffer 314 is compared. Since there is no cell in the cell, the cell passes through the selector 514 and is sent to the outgoing line 221. As a result, the multiplexed output cell OUT is obtained.

As described above, in consideration of the uneven load on the incoming lines 211 to 21n, the plurality of first cell buffers 111 to 1n are provided.
As cell control information for realizing load division between nn, the first cell buffers 111 to 1n at the time when each cell is read from the first cell buffers 111 to 11n.
The number of cells stored in n is given. The cells read from the first cell buffers 111 to 1nn are transferred to the second cell buffers 311 to 3n in front of each intersection, and the added cell accumulation numbers are extracted and arranged at each intersection. The connection order is set by comparison with the number of accumulated cells in the first cell buffers 111 to 1nn.

As a result, the first cell buffers 111 to 1nn having a large cell storage number are preferentially output to the outgoing lines 221 to 221.
2n, and the specific first cell buffers 111 to 1n
It is possible to suppress an increase in the number of accumulated cells at n. Further, it is not necessary to send and receive the control signal between the plurality of first cell buffers 111 to 1nn, and the transfer time of the cell control information does not become a problem.

In the embodiment of the present invention, the cell control information has been described as the information on the number of cells accumulated in the first cell buffers 111 to 1nn, but it includes the information on the cell transmission time from the first cell buffers 111 to 1nn. It is also possible to configure cell control information. Accordingly, it is possible to adopt a configuration in which the contention control is performed in consideration of the length of the cell waiting time.

[0049]

As described above, according to the present invention,
The arrival of cells biased to a specific incoming line can be processed so that the fairness of the waiting time of the cell can be maintained by using the memory capacity evenly arranged on each incoming line. Further, a signal line for a control signal is not required, and an ATM switch which has a high speed and a small amount of hardware can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration between an incoming line and an outgoing line according to the embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between an input cell and an output cell.

FIG. 4 is a configuration diagram of a conventional device.

FIG. 5 is a diagram showing a cell buffer and a multiplexing control circuit of a conventional device.

FIG. 6 is a block diagram of another conventional device.

FIG. 7 is a diagram showing a multiplex control circuit of another conventional device.

FIG. 8 is a diagram showing the output status of a conventional device.

[Explanation of symbols]

 111-1nn First cell buffer 211-21n In-line 221-22n Out-line 311-3nn Second cell buffer 71-7n, 411-4nn Multiple control circuit 41-4n, 811-8nn Internal wiring 511-5nn Selector 51 Cell transmission right OUT output cell

Claims (2)

[Claims] 1. A plurality of incoming lines to which cells arrive, a plurality of outgoing lines to which cells are sent, and a cell which is provided at each intersection of these incoming lines and outgoing lines and which waits to pass through these intersections. In an ATM switch equipped with a first cell buffer for accumulating and a multiplex control circuit for controlling cell transmission of the first cell buffer to the output line, an upstream crossing point on the output line of each crossing point is passed. A second cell buffer for temporarily storing cells is provided at each of the intersections, and means for adding to the cells stored in the second cell buffer the cell control information in the first cell buffer to which the cells are transmitted. Is provided, the multiplex control circuit, for the first cell buffer and the second cell buffer connected to the same intersection, the cell control information of the leading cell accumulated in the second cell buffer. An ATM switch comprising means for controlling the transmission of cells according to the cell information and the cell control information of the cell transmitted first from this first cell buffer. 2. The ATM switch according to claim 1, wherein said adding means includes means for adding, as cell control information, information on the number of cells accumulated in the first cell buffer of the cell transmission source and / or cell transmission time.