KR19980014041U - Reset signal generation circuit - Google Patents

Abstract

The present invention relates to a reset signal generation circuit that can prevent chattering of the reset signal generated from the contact portion of the power switch when the power switch is operated when the power is turned on. Power supply waveform converting means 18 for delaying and inverting a high level signal of power supply Vcc by a predetermined clock; Clock dividing means (20) for dividing and outputting the system clock from the system controller (n); The predetermined clock delayed low level signal from the power waveform converting means 18 is input to the input terminal D, and the divided clock signal from the clock distributing means 20 is input to the clock terminal CLK, thereby providing the clock. And a D flip-flop 22 outputted from the output terminal Q by selecting a logic value of the signal input to the input terminal D at the rising time of the signal.

Description

A circuit for generating the reset signal

The present invention relates to a reset signal generating circuit, and particularly, when the power switch is operated when the power is turned on, the reset signal generating circuit can prevent chattering of the reset signal generated from the contact portion of the power switch. It is about.

1 is a block diagram showing an example of a general reset signal generation circuit. As shown in the drawing, the reset signal generation circuit includes a reset switch 30, a reset circuit 32, and a D flip-flop 34. As shown in FIG. The reset circuit 32 is configured by connecting a resistor R and a capacitor C in series, and is configured to apply a reset signal generated when the power supply Vcc is turned on.

First, when it is assumed that there is no charged current in the capacitor C when the power supply Vcc is first input, the input of the D flip-flop 34 is a logic low level signal, for example, 0, the D flip-flop 34. The output (Q) of becomes logical 0. Therefore, the output ( ) Becomes a logic high level signal, such as 1, so that a reset signal is output, such that a predetermined device, such as a microprocessor, is reset.

The capacitor C maintains the state for a predetermined time until the power supply Vcc rises to reach a predetermined voltage. Thereafter, when the power supply Vcc rises to become a predetermined voltage or more, when the input of the D flip-flop 34 becomes logic 1, the output Q of the D flip-flop 34 becomes logic 0. Therefore, the output ( ) Becomes logic 1, which resets the reset state.

Then, when the reset switch 30 is pressed, for example, when the reset switch 30 is turned on, the current charged in the capacitor C is discharged so that the input of the D flip-flop 34 returns to logic 0 again. Will be reset. All these operations are synchronized with the system clock.

On the other hand, the D flip-flop 34 has an asynchronous input so that it can be used to bring the flip-flop into a special state irrespective of the input of the clock input terminal CLK and the input terminal D. As the input terminal, the preset terminal PR and the erase terminal CLR are used.

In such a reset circuit, there is a limit in the ability to generate a reset signal at power-on, depending on conditions such as the magnitude of the power supply voltage and the tendency of the power supply voltage to rise, which are used by the integrated circuit receiving the reset signal. For example, when the power is turned on, the reset circuit causes the reset signal to reset the system to become somewhat unstable, causing the system to malfunction or to troubleshoot the initial value of the register.

In addition, when the power switch is operated when the power is turned on, an unstable reset signal caused by the power generated from the contact portion of the power switch, for example, a reset signal including a chattering phenomenon is generated and the system becomes unstable. The chattering phenomenon is a distortion phenomenon of the reset signal generated at the contact portion of the power switch when the power is turned on, and there is a problem that the reset signal is unstable by the chattering.

In order to solve the above problems, the present invention provides a reset signal generation circuit capable of preventing chattering of the reset signal generated from the contact portion of the power switch when the power switch is operated when the power is turned on. The purpose is to provide.

The present invention for achieving the above object is a power waveform conversion means for delaying and inverting a predetermined clock delay and a high level signal of the power supply during operation of the power switch; Clock dividing means for dividing and outputting the system clock from the system controller n; A low level signal delayed by the predetermined clock delay from the power waveform converting means is input to the input terminal, and the divided clock signal from the clock divider is input to the clock terminal and input to the input terminal at the rising time of the clock signal. It is characterized in that it comprises a D flip-flop is selected from the logic value is output from the output terminal.

According to the present invention configured as described above, when the power switch is operated when the power is turned on, chattering of the reset signal generated from the contact portion of the power switch can be prevented, thereby preventing malfunction of the system.

1 is a circuit diagram showing an example of a general reset signal generation circuit;

2 is a circuit diagram showing one embodiment of a reset signal generation circuit according to the present invention;

3A to 3G are waveform diagrams showing a process of forming a reset signal in the reset signal generation circuit shown in FIG.

It is a figure which shows the operation waveform diagram for demonstrating this.

Explanation of symbols on the main parts of the drawings

10, 12: first and second delay elements, 14: inverter element,

16: NAND gate, 18: power waveform conversion section,

20: clock divider, 22: D flip-flop.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

2 is a circuit diagram showing an embodiment of a reset signal generation circuit according to the present invention. As shown, the reset signal generation circuit according to the present invention includes a power waveform converter 18, a clock divider 20, and a D flip-flop 22.

The power waveform converting unit 18 includes first and second delay elements 10 and 12, an inverter element 14, and a NAND gate 16. The first delay element 10 is a power switch (not shown). If a high level signal, for example, logic 1, is input during the operation of the control unit, the logic 1 is delayed by a first predetermined clock, for example, 10 clocks. The second delay element 12 delays a high level signal delayed 10 clocks from the first delay element 10 by a second predetermined clock, for example, 10 clocks.

In addition, the inverter element 14 inverts the 10 clock delayed high level signal from the second delay element 12, and the NAND gate 16 outputs an output signal from the inverter element 14, for example, a high level signal. And an output signal from the output terminal of the first delay element 10, for example, a high level signal delayed by 10 clocks, is output.

On the other hand, an output terminal of the NAND gate 16 of the power waveform converter 18 is connected to an input terminal D of the D flip-flop 22, and a predetermined division of the system clock is applied to the clock input terminal CLK. The clock divider 20 to be executed is connected.

The D flip-flop 22 has an asynchronous input so that the flip-flop 22 can be used to bring the flip-flop into a special state regardless of the inputs of the clock input terminal CLK and the input terminal D. As such, the preset terminal PR and the erase terminal CLR are used as the input terminals. In addition, the erasing terminal CLRN of the D flip-flop 22 outputs the output of the output terminal Q as a default signal, eg, logic 0, in a negative-edge-trigger, for example, a falling edge signal.

In the embodiment shown in FIG. 2, the clock signal CLK may be a system clock, for example, a clock used for normal operation of an integrated circuit, but is not limited thereto.

Next, when the power switch (not shown) is operated in the reset signal generation circuit of Fig. 2, while the power switch is in the on state, the power supply Vcc input to the power waveform conversion section 18 is converted into a high level signal. In the off state, the signal becomes a low level signal. At this time, while the power switch is in the on state, chattering generated by the contact portion of the power switch occurs, distorting the waveform of the reset signal. Accordingly, when the power supply Vcc is turned on, the high level signal of the power supply Vcc including the chattering phenomenon is input to the first delay element 10 of the power waveform converter 18 by the power switch.

The first delay element 10 outputs the high level signal by delaying a predetermined clock, for example, 10 clocks, and the second delay element 12 is a high level signal delayed by 10 clocks from the first delay element 10. Delays a predetermined clock, eg, 10 clocks.

The inverter element 14 inverts the 10 clock delayed high level signal from the second delay element 12 to output a 10 clock delayed low level signal. Thereafter, the NAND gate 16 performs a D flip-flop operation on the low level signal formed by calculating the high level signal from the output terminal of the first delay element 10 and the inverted low level signal from the inverter element 14. Input is performed through the input terminal D of 22).

The clock terminal CLK of the D flip-flop 22 receives a clock signal obtained by dividing a predetermined system clock, for example, 10 times, from the clock divider 20, and the input terminal D at the rising time of the clock signal. The logic value inputted into) is selected and outputted from the output terminal Q.

At this time, the chattering phenomenon is removed from the low level signal including the chattering phenomenon inputted to the input terminal of the D flip-flop 22 by the clock signal in the above process. The reset signal is output from the output terminal Q.

Next, the formation process of the reset signal shown in FIG. 3 will be described with reference to the reset signal generation circuit shown in FIG. Here, the chattering phenomenon occurring during the operation of the power switch (not shown) is assumed to occur within one cycle of the clock inputted to the clock terminal CLK of the D flip-flop 22.

First, FIG. 3A is a diagram illustrating a time point at which power is turned on by an operation of a power switch. In this case, when the power switch is turned on, the input power supply Vcc becomes a high level signal, and when it is off, a low level signal is turned on. It is shown. In addition, the waveform of the high level signal including the chattering phenomenon at the input terminal 1 of the power waveform conversion unit 18 during operation of the power switch is shown.

3B illustrates a waveform in which the waveform of the high level signal shown in FIG. 3A is delayed by 10 clocks by the first delay element 10, and FIG. 3C illustrates the waveform of the high level signal illustrated in FIG. 3B in the second delay element 12. Shows a waveform delayed by 10 clocks by " 3D is a view showing the waveform of the low level signal in which the waveform of the high level signal shown in FIG. 3C is inverted by the inverter element 14.

FIG. 3E is a diagram showing the waveform of the 10 clock low level signal in which the waveform of the high level signal shown in FIG. 3B and the waveform of the low level signal shown in FIG. 3D are calculated by the NAND gate 16. 3F illustrates a clock signal in which the system clock is divided by the clock divider 20, the clock used in the normal operation of the integrated circuit may be used, but is not limited thereto.

3G shows the waveform of the output clock output from the output terminal Q of the D flip-flop 22 of a 10 clock low level signal. Here, when the low level signal including the chattering phenomenon shown in FIG. 3E is inputted to the input terminal D of the flip-flop 22, the input terminal D is provided at the rising time of the divided clock signal shown in FIG. 3F. A logic value of an input signal is selected to represent a waveform of a predetermined clock, for example, a 10 clock low level signal, output from the output terminal Q.

On the other hand, reference numerals denoted in the configuration requirements of the claims of the present application to facilitate the understanding of the present invention, not intended to limit the technical scope of the present invention to the embodiments shown in the drawings.

As described above, according to the present invention, when the power switch is operated when the power is turned on, chattering of the reset signal generated from the contact portion of the power switch can be prevented, thereby preventing malfunction of the system.

Claims (4)

Power supply waveform converting means (18) for delaying and inverting a high level signal of power supply (Vcc) by a predetermined clock during operation of the power supply switch; Clock dividing means (20) for dividing and outputting the system clock from the system controller (n); The predetermined clock delayed low level signal from the power waveform converting means 18 is input to the input terminal D, and the divided clock signal from the clock distributing means 20 is input to the clock terminal CLK, thereby providing the clock. And a D flip-flop (22) outputted from the output terminal (Q) by selecting a logic value of the signal input to the input terminal (D) at the rising time of the signal. 2. The power supply waveform converting means (18) according to claim 1, further comprising: a first delay element (10) for delaying a high level signal of a power supply (Vcc) by a predetermined clock; A second delay element 12 for delaying a predetermined clock delayed high level signal from the first delay element 12 by a predetermined clock; An inverter element 14 for inverting the high level signal from the second delay element 12; A reset signal generation, characterized in that it comprises an inverted low level signal of the inverter element 14 and a NAND gate 16 for calculating and outputting a high level signal input from an output terminal of the first delay element 10. Circuit. 3. The first delay element (10) according to claim 2, wherein the first delay element (10) delays the high level signal of the power supply (Vcc) by 10 clocks, and the second delay element (12) is the high level from the first delay element (10). A reset signal generation circuit comprising delaying a signal by 10 clocks. 3. The reset signal generating circuit according to claim 2, wherein the clock divider (20) divides the system clock from the system controller by 10.