KR102680526B1 - Display device - Google Patents

Abstract

The present invention relates to a display device. The display device according to the present invention includes a substrate including a display area having a special corner and a non-display area around the display area, the display area including the special corner, and a transistor, respectively. a plurality of pixels including a plurality of pixels, a gate driver disposed in the non-display area and supplying a gate signal, a first gate wire disposed in the non-display area and extending from the gate driver, and electrically connected to the first gate wire. a second gate wire that transmits the gate signal to the transistor and a power supply wire extending in the same direction as the second gate wire in the non-display area, wherein the first gate wire and the power supply wire are connected to the transistor. It may be the same material as the source electrode and drain electrode. Accordingly, the size of the bezel of the display device can be minimized and the luminance uniformity of the display device can be improved.

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more specifically, to a display device in which luminance uniformity is improved and the width of the bezel at the corner is minimized.

Currently, various display devices are being developed and sold. For example, liquid crystal display device (LCD), field emission display device (FED), electrophoretic display device (EPD), electro-wetting display device There are display devices such as display device (EWD), organic light emitting display device (OLED), and quantum dot display device (QD).

A display device includes a display area where a plurality of pixels are arranged to display an image, and a non-display area surrounding the display area where an image is not displayed. At this time, a plurality of pixels may be defined in the display area. Additionally, wiring and circuits for transmitting various signals to a plurality of pixels are arranged in the non-display area.

As technology for implementing such display devices develops and many products are mass-produced, display devices are developing with a focus on technology for implementing designs desired by consumers. One of them is the diversification of the form of the display area where images are implemented. Specifically, the display area is required to have a variety of shapes beyond the rectangular shape. For example, efforts are needed to secure flexibility in product design by diversifying the shape of the display area of display devices with various purposes, such as wearable display devices. Additionally, as the shape of the display area is diversified, it is necessary to change the design of the shape of the non-display area surrounding the display area and the wiring arranged in the non-display area.

The inventors of the present invention developed a display device having a display area with unusual corners in response to consumers' requests for various design changes. A deformed corner refers to a corner of various shapes, such as a round corner, rather than a corner having a rectangular shape. Additionally, it has been invented that by having the display area have a special corner, the corner of the non-display area corresponding to the special corner also has a shape corresponding to the special corner. However, it was recognized that there is a limit to reducing the area of the non-display area due to the gate driver located on both sides of the display area.

Additionally, the inventors of the present invention recognized that it is important to uniformly supply power voltage to a plurality of pixels. However, the inventors of the present invention found that when the corners of the display area are implemented as unusual corners, the number of wires that must be placed increases compared to the conductive layer disposed in the non-display area corresponding to the unusual corners, so there is no horizontal line for supplying the power voltage. It was recognized that it would be difficult to place the wiring to a special corner.

Accordingly, the inventors of the present invention changed the design of the wiring and gate driver for the non-display area corresponding to the display area having the unusual corner, thereby minimizing the width of the non-display area corresponding to the unusual corner and simultaneously creating a plurality of A display device with a new structure that can uniformly supply power voltage to pixels has been developed.

The problem to be solved by the present invention is to provide a display device in which the bezel area of the unusual corner area is reduced by arranging the gate driver in a non-display area that does not correspond to the unusual corner.

Additionally, the problem to be solved by the present invention is to provide a display device in which contact holes are positioned so that data wires and gate wires arranged in a non-display area corresponding to an unusual corner do not intersect each other.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment of the present invention includes a substrate including a display area having an unusual corner and a non-display area around the display area, and a plurality of devices located in the display area including the unusual corner and each including a transistor. A pixel, a gate driver disposed in the non-display area and supplying a gate signal, a first gate wire disposed in the non-display area and extending from the gate driver, and electrically connected to the first gate wire to transmit the transistor to the transistor. A second gate wire transmitting a gate signal and a power supply wire extending in the same direction as the second gate wire in the non-display area, wherein the first gate wire and the power supply wire are the source electrode of the transistor and It may be the same material as the drain electrode.

The present invention can reduce the bezel area by not disposing the gate driver in the non-display area corresponding to the unusual corner.

In addition, the present invention can supply a uniform power voltage to all of each pixel by arranging the power supply wiring in the display area, thereby improving the uniformity of luminance.

In addition, the present invention can supply a high potential voltage to each pixel by positioning the contact hole so that the data wire and the gate wire arranged in the non-display area corresponding to the unusual corner do not intersect each other.

The effects according to the present invention are not limited to the contents exemplified above, and further various effects are included in the present specification.

1 is a plan view of a display device according to an embodiment of the present invention.
FIG. 2 is an enlarged plan view of areas A and B of FIG. 1.
FIG. 3 is a cross-sectional view of lines IIIa-IIIa' and IIIb-IIIb' of FIG. 2.
Figure 4 is an enlarged plan view of a display device according to another embodiment of the present invention.
FIG. 5 is a cross-sectional view taken along lines Va-Va' and Vb-Vb' of FIG. 4.
Figure 6 is an enlarged plan view of a display device according to another embodiment of the present invention.
Figure 7 is an enlarged plan view of a display device according to another embodiment of the present invention.
Figure 8 is an enlarged plan view of a display device according to another embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

When an element or layer is referred to as “on” another element or layer, it includes instances where the other layer or other element is directly on top of or interposed between the other elements.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

The size and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the components shown.

Each feature of the various embodiments of the present invention can be partially or fully combined or combined with each other, and as can be fully understood by those skilled in the art, various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other. It may be possible to conduct them together due to a related relationship.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is a plan view of a display device according to an embodiment of the present invention. Referring to FIG. 1 , the display device 100 includes a substrate 110, a gate driver 120, and a power supply wire 130.

The substrate 110 is used to support and protect various components of the display device 100. The substrate 110 may be made of glass or a plastic material with flexibility. If the substrate 110 is made of a plastic material, for example, it may be made of polyimide (PI). However, it is not limited to this.

The substrate 110 includes a display area AA and a non-display area NA adjacent to the display area AA.

The display area AA is an area where an image is displayed in the display device 100, and a display element and various driving elements for driving the display element are disposed in the display area AA. The corners of the display area AA may be irregular corners. Anomalous corners refer to corners of various shapes rather than rectangular corners like the corners of a typical display area (AA). For example, the unusual corner may be a round corner, or may be a part of a pentagon or hexagon, but is not limited thereto.

The non-display area (NA) is an area adjacent to the display area (AA). The non-display area (NA) is an area adjacent to the display area (AA) and surrounding the display area (AA). The non-display area (NA) is an area where images are not displayed, and wiring and circuit parts are formed. For example, the gate driver 120 and the power supply wire 130 may be disposed in the non-display area (NA). The non-display area (NA) may have unusual corners as shown in FIG. 1 . However, it is not limited to this and may have a corner having two vertical sides.

The gate driver 120 is a circuit for supplying a gate signal to the pixel PX. As shown in FIG. 1, the gate driver 120 may be placed on both sides of the display area AA, but may also be placed on one side of the display area AA. The gate driver 120 may supply a gate signal to each pixel in the display area AA.

The power supply wire 130 is located in the non-display area (NA) and is used to supply power voltage to the pixel. For example, the power supply line 130 may supply a power voltage to each pixel of the display area AA.

Although not shown in FIG. 1, the display device 100 may include an external module, for example, a Chip On Film (COF). The COF may be bonded to the non-display area (NA) and electrically connected to the substrate 110 through a pad. The COF may include a base film made of an insulating material and a driver IC formed on the base film. The COF can supply power voltage and data voltage to the display area (AA) through the pad.

Hereinafter, FIGS. 2 and 3 will be referred to together for a more detailed description of the display device 100.

Figure 2 is an enlarged plan view of areas A and B of Figure 1. FIG. 3 is a cross-sectional view taken along lines IIIa-IIIa' and IIIb-IIIb' of FIG. 2. Areas A and B of FIG. 2 are plan views enlarging the irregular corner portion of the display area AA. Since area A and area B may be configured symmetrically, duplicate descriptions are omitted.

Referring to FIGS. 2 and 3 , the display area AA includes a plurality of pixels PX. A plurality of pixels (PX) are in the display area (AA) and include elements such as the transistor 140. Each of the plurality of pixels (PX) is connected to a gate line (GL), a data line (DL), and a power line (VDDL). The gate wire (GL) is a wire that transmits a gate signal to a plurality of pixels (PX), the data wire (DL) is a wire that transmits a data signal to a plurality of pixels (PX), and the power wire (VDDL) is a wire that transmits a gate signal to a plurality of pixels (PX). This is a wiring that supplies power voltage to the pixel (PX).

Referring to FIG. 3 for a description of the structure of each pixel PX in the display area AA, a transistor 140 is disposed on the substrate 110. Specifically, an active layer 141 in which a channel of the transistor 140 is formed is formed on the substrate 110, and a gate insulating layer 111 is formed on the active layer 141. The gate insulating layer 111 is made of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx), and may be a single layer or a plurality of layers, but is not limited thereto. A gate electrode 142 is formed on the gate insulating layer 111. A first interlayer insulating layer 112 is formed on the gate electrode 142. The first interlayer insulating layer 112 may be made of, for example, silicon nitride (SiNx), but is not limited thereto. A second interlayer insulating layer 113 is formed on the first interlayer insulating layer 112. The second interlayer insulating layer 113 may be formed of the same material as the first interlayer insulating layer 112, but is not limited thereto. The source electrode 143 and the drain electrode 144 of the transistor 140 may be formed on the second interlayer insulating layer 113. The source electrode 143 and the drain electrode 144 are electrically connected to the active layer 141 through contact holes formed in the gate insulating layer 111, the first interlayer insulating layer 112, and the second interlayer insulating layer 113. connected. In FIG. 3, the transistor 140 is shown as a top gate type coplanar structure transistor 140, but the stacked structure of the transistor 140 is not limited to this. Also, in FIG. 3, the gate insulating layer 111 and the second interlayer insulating layer 113 are shown to flatten the upper portion, but this is not limited to this, and the gate insulating layer 111 and the second interlayer insulating layer 113 are It may be arranged conformally according to the shape of the surface of the components arranged below.

A conductive layer 150 may be disposed between the first interlayer insulating layer 112 and the second interlayer insulating layer 113. For example, in the display device 100 according to an embodiment of the present invention, two interlayer insulating layers 112 and 113 are used between the first interlayer insulating layer 112 and the second interlayer insulating layer 113. As the additional conductive layer 150 is disposed, the conductive layer 150 may be disposed between the source electrode 143 and drain electrode 144 of the transistor 140 and the gate electrode 142 of the transistor 140. . Accordingly, as the number of conductive patterns and wires that can be additionally placed increases, it is possible to provide a display device 100 with higher resolution, a wire with lower resistance, and a capacitor in the display device 100. Capacitance can also be improved by additionally connecting in parallel.

And, referring to FIG. 2 , the power supply wiring 130 extends in the same direction as the plurality of gate wirings GL and is disposed in the non-display area NA. For example, the power supply wire 130 may extend in the same direction as the direction in which the plurality of second gate wires GL2 disposed in the display area among the plurality of gate wires GL extend.

And, the power supply wire 130 is connected to a plurality of power wires VDDL. The plurality of power supply wires VDDL are wires branched from the power supply wire 130 and supply high potential voltages to the plurality of pixels PX. The plurality of power wiring lines VDDL may be made of the same material as the power supply wiring 130 and may be formed by branching from the power supply wiring 130 . For example, the power supply wiring 130 and the plurality of power wiring lines VDDL may be formed in one process. At this time, the power supply wiring 130 and the plurality of power wiring lines VDDL may be made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140.

In addition, the width W1 of the power supply wire 130 in the direction in which the plurality of gate wires GL extends is equal to the distance D2 between the outermost power supply wires VDDL among the plurality of power wires VDDL. It could be more than that. The width W1 of the power supply wiring 130 refers to the width of the power supply wiring 130 in a direction parallel to the direction in which the plurality of gate wirings GL extend. The gap D2 between the outermost power wires (VDDL) may be the gap between the two power wires (VDDL) located at the outermost of the plurality of power wires (VDDL) branched from the power supply wire 130. . Additionally, the power supply wiring 130 may be arranged to correspond to the entire display area AA. The width W3 of the display area AA may be the maximum width of the display area AA in the direction in which the plurality of gate wires GL extend. For example, as shown in FIG. 2, the width W1 of the power supply wire 130 is equal to the width W3 of the display area AA and may correspond to the entire display area AA.

Alternatively, the power supply wiring 130 may be formed to be larger than the width W3 of the display area AA. For example, the width W1 of the power supply wiring 130 may be larger than the width W3 of the display area AA.

When the width W1 of the power supply wire 130 is greater than or equal to the gap D2 between the outermost power wires VDDL or greater than the width W3 of the display area AA, the branched wire 130 is branched from the power supply wire 130. The outermost power supply lines (VDDL) among the plurality of power supply lines (VDDL) may supply power voltage to the pixel (PX) located at the outermost position among the plurality of pixels (PX). Accordingly, all of the plurality of pixels PX can receive a high potential voltage through the plurality of power wiring lines VDDL branched from the power supply wiring 130 .

Referring to FIG. 2 , the gate driver 120 disposed on both sides of the display area AA includes a plurality of stages 121 and 122. Each of the plurality of stages 121 and 122 is connected to each of the plurality of gate wires GL to transmit the gate signal to the plurality of pixels PX. The gate driver 120 is located on both sides of the display area AA excluding the unusual corners of the display area AA. For example, the corner area CA may be a non-display area NA corresponding to an unusual corner of the display area AA, and the plurality of stages 121 and 122 of the gate driver 120 may be a corner area CA. ) can only be placed in the non-display area (NA).

2 and 3, a plurality of gate wires GL are connected to each of the plurality of stages 121 and 122 of the gate driver 120, and transmit a gate signal from the gate driver 120 to a plurality of pixels PX. ) This is the wiring that is transmitted to each. The plurality of gate wires GL includes a plurality of first gate wires GL1 and a plurality of second gate wires GL2. The plurality of first gate wires GL1 refer to wires extending from the gate driver 120 and are made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140. In addition, the plurality of second gate wires GL2 refers to wires connected to the plurality of first gate wires GL1 and extending into the display area AA, and are made of the same material as the gate electrode 142 of the transistor 140. am. Referring to FIG. 3, the plurality of first gate wires GL1 and the plurality of second gate wires GL2 are a plurality of second contacts formed on the first interlayer insulating layer 112 and the second interlayer insulating layer 113. They are electrically connected through each hole (CH2).

Referring to FIG. 2, each of the plurality of second contact holes (CH2) through which each of the plurality of first gate wires (GL1) and each of the plurality of second gate wires (GL2) contacts the plurality of power wires (VDDL) and the plurality of second contact holes (CH2). It is located outside the data wire (DL). Specifically, the plurality of second contact holes CH2 may be located outside the outermost power line VDDL among the plurality of power line lines VDDL. Additionally, the plurality of second contact holes CH2 may be located outside the data line DL, which is located at the outermost position among the plurality of data lines DL.

Accordingly, the plurality of first gate wires GL1 may be arranged in an area different from the area where the plurality of power wires VDDL and the plurality of data wires DL are arranged. Specifically, the plurality of first gate wires GL1 are connected to each of the plurality of stages 121 and 121, and are connected to the plurality of second gate wires GL2 through each of the plurality of second contact holes CH2. . Accordingly, the plurality of first gate wires GL1 are located outside the plurality of second contact holes CH2. Since the plurality of second contact holes CH2 are located outside the plurality of power wiring lines VDDL and the plurality of data lines DL, the plurality of first gate wirings GL1 are different from the plurality of power wiring lines VDDL. Can be placed in an area. Additionally, the plurality of first gate wires GL1 may be disposed in a different area from the plurality of data wires DL.

Referring to FIG. 2 , the plurality of data lines DL are arranged parallel to the plurality of power lines VDDL and may be connected to each of the plurality of pixels PX to supply data signals. The plurality of data lines DL may be made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140.

A plurality of data lines (DL) may be connected to a plurality of data link lines (DLL). A plurality of data link lines (DLL) are disposed in the non-display area (NA) and may supply data signals to a plurality of data line lines (DL). The plurality of data link lines (DLL) include a first data link line (DLL1), a second data link line (DLL2), a third data link line (DLL3), a fourth data link line (DLL4), and a fifth data link line. (DLL5) may be included. The number of data link lines (DLLs) is not limited to this, and a larger number of data link lines (DLLs) may be present.

Also, some of the plurality of data link lines (DLL) may be made of the same material as the gate electrode 142 of the transistor 140, and other parts may be made of the same material as the conductive layer 150. For example, the first data link and the third data link may be made of the same material as the gate electrode 142, and the second data link and the fourth data link may be made of the same material as the conductive layer 150. For example, data link wires DLL1, DLL3, and DLL5 made of the same material as the gate electrode 142 and data link wires DLL2, DLL4 made of the same material as the conductive layer 150 may be alternately arranged. However, it is not limited to this.

Referring to FIG. 2, the plurality of first contact holes CH1 through which each of the plurality of data lines DL and each of the plurality of data link lines DLL contact each other is the power supply line 130 among the plurality of gate lines GL. ) and is located between the gate wiring (GL) and the power supply wiring (130) closest to the gate wiring (GL). Specifically, the plurality of first contact holes CH1 may be located above the uppermost wiring among the plurality of gate wirings GL, that is, the gate wiring GL closest to the power supply wiring 130. . And, it may be located lower than the power supply wiring 130.

For example, the first data link line (DLL1), the third data link line (DLL3), and the fifth data link line (DLL5), which are made of the same material as the gate electrode 142, each have a first interlayer insulating layer 112 and It is connected to each of the plurality of data lines DL through the plurality of first contact holes CH1 formed in the second interlayer insulating layer 113. In addition, each of the second data link line (DLL2) and the fourth data link line (DLL), which are made of the same material as the conductive layer 150, has a plurality of first contact holes (CH1) formed in the second interlayer insulating layer 113. It is connected to each of a plurality of data lines (DL) through. The plurality of first contact holes CH1 are located between the gate wiring GL closest to the power supply wiring 130 among the plurality of gate wirings GL and the power supply wiring 130, thereby forming a plurality of data link wirings ( DLL) may not be formed in the same area as the plurality of gate lines GL.

In the case of a general display device, since the number of conductive layers is less than the number of wirings present in the non-display area, the power supply wiring cannot be arranged up to the non-display area corresponding to the unusual corner of the display area. Accordingly, the power supply wiring was placed in a non-display area excluding the special corner. Accordingly, the power voltage could be supplied only to pixels arranged in the display area excluding the unusual corner. Accordingly, in the case of pixels placed at unusual corners, the power voltage was supplied using a conductive layer different from the power supply wiring. Accordingly, a larger voltage drop may occur in the power voltage supplied to pixels placed in an unusual corner compared to the power voltage supplied to a pixel placed in an area other than an unusual corner. Accordingly, the strength of the power voltage supplied to the plurality of pixels was uneven, reducing luminance uniformity.

In the display device 100 according to an embodiment of the present invention, the width W1 of the power supply wire 130 is formed to be greater than or equal to the distance D2 between the outermost power wires VDDL or the display area AA ) may be formed to be greater than or equal to the width W3 of the display area AA. Accordingly, the luminance uniformity of the display device 100 can be improved. For example, when the width W1 of the power supply wire 130 is smaller than the gap D2 between the outermost power wires VDDL or smaller than the width W3 of the display device 100, the power supply wire 130 The plurality of power lines (VDDL) branching from 130 may not directly apply a high potential voltage to all of the plurality of pixels (PX). That is, among the plurality of pixels (PX), the pixel (PX) placed at the corner cannot be directly connected to the plurality of power lines (VDDL), and cannot be directly connected to the power line (VDDL) located in the center area excluding the corner area (CA). Power voltage can be supplied through branched wiring. Accordingly, the power voltage applied to the plurality of pixels (PX) arranged in the unusual corner may have a larger voltage drop than the power voltage applied to the plurality of pixels (PX) arranged in the area other than the unusual corner. Accordingly, the luminance may be reduced compared to the pixel PX disposed in the center of the display area AA, and the luminance uniformity of the entire display device 100 may be reduced. Therefore, in the display device 100 according to an embodiment of the present invention, the width W1 of the power supply wire 130 is formed to be greater than or equal to the distance D2 between the outermost power wires VDDL or the display area (AA) can be formed to be larger than the width (W3) of the display area (AA) so as to correspond to the entire display area (AA). Accordingly, the power line VDDL branched from the power supply line 130 can be directly connected to the pixel PX disposed at the corner, and a high-potential power supply voltage can be supplied to all pixels PX. To this end, the luminance uniformity of the entire display area AA can be improved.

In addition, the display device 100 according to an embodiment of the present invention has a plurality of second contact holes (CH2) through which each of the plurality of first gate wires (GL1) and each of the plurality of second gate wires (GL2) contact each other. By being located outside the power line VDDL and the plurality of data lines DL, a high potential voltage can be supplied to all of the plurality of pixels PX. For example, as described above, as the power supply wire 130 is formed to be long corresponding to the display area AA, a plurality of power supply wires VDDL branching from the power supply wire 130 are connected to a plurality of pixels ( High potential voltage can be supplied to the entire PX). Accordingly, the outermost power line VDDL among the plurality of power line lines VDDL may also be connected to the pixel PX located at the outermost side among the plurality of pixels PX. At this time, the second contact hole (CH2) where each of the plurality of first gate wires (GL1) and each of the plurality of second gate wires (GL2) contact each other is inside the plurality of power wires (VDDL) and the plurality of data wires (DL). When located in , the plurality of first gate wires GL1 may be arranged in the same area as the plurality of power wires VDDL and the plurality of data wires DL. At this time, the plurality of first gate wires GL1, the plurality of power wires VDDL, and the plurality of data wires DL are formed of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140. . Accordingly, a problem may occur in which a plurality of power lines (VDDL), a plurality of data lines (DL), and a plurality of first gate lines (GL1) are disposed in the same area. Accordingly, the display device 100 according to an embodiment of the present invention has a plurality of second contact holes CH2 through which each of the plurality of first gate wires GL1 and each of the plurality of second gate wires GL2 contact each other. By being located outside the power line VDDL and the plurality of data lines DL, a high potential voltage can be supplied to each of the plurality of pixels PX.

In the display device 100 according to an embodiment of the present invention, some of the plurality of data link lines (DLL) are made of the same material as the gate electrode 142, and other parts are made of the same material as the conductive layer 150. . Accordingly, the area occupied by the plurality of data link lines (DLLs) can be reduced. For example, if multiple data link lines (DLLs) are all made of the same material and are placed on the same layer, the space between each data link line (DLL) may be reduced due to limitations in the photoresist process for forming the plurality of data link lines (DLLs). The spacing cannot be reduced below the minimum spacing. However, when some of the plurality of data link wires (DLL) are made of the same material as the gate electrode 142 and other parts are made of the same material as the conductive layer 150, the plurality of data link wires (DLL) are located on different layers. can be placed. Accordingly, the spacing between each data link line (DLL) can be reduced to less than the minimum spacing described above. Accordingly, the area occupied by the plurality of data link lines (DLLs) can be reduced.

Figure 4 is an enlarged plan view of a display device according to another embodiment of the present invention. FIG. 5 is a cross-sectional view taken along lines Va-Va' and Vb-Vb' of FIG. 4. The display device 400 shown in FIG. 4 is substantially the same as the display device 100 shown in FIGS. 1 to 3 except for a different configuration of the plurality of gate wires GL, so duplicate description is omitted. Or you can explain it briefly.

Referring to FIGS. 4 and 5 , the plurality of gate wires GL includes a plurality of first gate wires GL1, a plurality of second gate wires GL2, and a plurality of third gate wires GL3.

The plurality of first gate wires GL1 refers to a wire extending from the gate driver 120 among the plurality of gate wires GL. The plurality of first gate wires GL1 may be made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140.

And, the plurality of second gate wires GL2 refers to a wire extending into the display area AA among the plurality of gate wires GL. The plurality of second gate wires GL2 may be made of the same material as the gate electrode 142 of the thin film transistor.

And, the plurality of third gate wires GL3 refers to a wire connecting the plurality of first gate wires GL1 and the plurality of second gate wires GL2 among the plurality of gate wires GL. Some of the plurality of third gate wires GL3 may be made of the same material as the gate electrode 142 of the transistor 140, and other parts may be made of the same material as the conductive layer 150. For example, the plurality of third gate wires GL3 may include a third sub-gate wire GL3a and a third sub-gate wire GL3b. The third sub-gate wire GL3a may be made of the same material as the gate electrode 142 of the transistor 140, and the third sub-gate wire GL3b may be made of the same material as the conductive layer 150. For example, in the plurality of third gate wires GL3, wires made of the same material as the gate electrode 142 of the transistor 140 and wires made of the same material as the conductive layer 150 may be alternately arranged.

In the display device 400 according to another embodiment of the present invention, part (GL3a) of the plurality of third gate wires (GL3) is made of the same material as the gate electrode 142 of the transistor 140, and another part (GL3b) is made of the same material as the gate electrode 142 of the transistor 140. is made of the same material as the conductive layer 150, so that the gate signal, data signal, and power signal can be stably supplied to each of the plurality of pixels (PX). For example, when the positions of the plurality of first gate contact units C1 are disposed on the right side of the outermost data line DL or the outermost power line VDDL, unlike the positions shown in FIG. 4, the plurality of data The wiring DL and the plurality of third gate wirings GL3 may overlap. If the plurality of third gate wires GL3 are made of the same material as the source electrode 143 and the drain electrode 144 of the plurality of transistors 140, the gate signal may overlap with the data signal or power signal, causing a problem. do. Accordingly, in the display device 400 according to another embodiment of the present invention, part (GL3a) of the plurality of third gate wires (GL3) is made of the same material as the gate electrode 142 of the transistor 140, and another part (GL3a) is made of the same material as the gate electrode 142 of the transistor 140. Since GL3b) is made of the same material as the conductive layer 150, the gate signal, data signal, and power signal can be stably supplied to each of the plurality of pixels (PX).

Referring to FIG. 4 , each of the plurality of first gate wires GL1 and each of the plurality of third gate wires GL3 may be electrically connected through each of the plurality of second contact holes CH2. For example, the third sub-gate wire GL3a and the first gate wire GL1 are electrically connected through the second contact hole CH2 formed in the first interlayer insulating layer 112 and the second interlayer insulating layer 113. It can be connected to . Additionally, the third sub-gate wire GL3b and the first gate wire GL1 may be electrically connected through the second contact hole CH2 formed in the second interlayer insulating layer 113.

Referring to FIGS. 4 and 5 , each of the plurality of second gate wires GL2 and each of the plurality of third gate wires GL3 may be electrically connected through a plurality of first gate contact portions C1. The plurality of first gate contact parts C1 may be made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140. And, among the plurality of third gate wires GL3, the wire GL3a formed of the same material as the gate electrode 142 of the transistor 140 is connected to the first interlayer insulating layer 112 and the second interlayer insulating layer 113. It is electrically connected to the plurality of first gate contact parts C1 through the formed contact hole. Also, among the plurality of third gate wires GL3, the wire GL3b formed of the same material as the conductive layer 150 passes through the contact hole formed in the second interlayer insulating layer 113 to form a plurality of first gate contact portions C1. ) is electrically connected to.

Also, among the plurality of third gate wires GL3, each of the wires GL3a, which is made of the same material as the gate electrode 142 of the transistor 140, and each of the plurality of second gate wires GL2 are connected to a plurality of first gate contacts. It can also be formed with a single wiring line without using the part C1. Also, among the plurality of third gate wires GL3, each of the wires GL3b made of the same material as the conductive layer 150 and each of the plurality of second gate wires GL2 are connected to each other through contact holes formed in the first interlayer insulating layer 112. You can also connect through . In this case, the resistance of the plurality of third gate wires GL3 and the plurality of second gate wires GL2 formed as one wire is one of the plurality of third gate wires GL3 connected using each of the plurality of contact holes. The resistance may be low compared to the resistance of each of the wires GL3b and the plurality of second gate wires GL2, which are made of the same material as the conductive layer 150. If the variation in resistance of each of the plurality of gate wires (GL) is large, the variation in the time when the gate signal is transmitted to each of the plurality of pixels (PX) may increase, and thus the driving stability of the display device 400 may deteriorate. there is.

Accordingly, the display device 400 according to another embodiment of the present invention connects the source electrode 143 and the drain electrode 144 of the transistor 140 through each of the plurality of first gate contact portions C1, which are made of the same material. By electrically connecting each of the plurality of second gate wires GL2 and each of the plurality of third gate wires GL3, each of the plurality of gate wires GL is connected through the same number of contact holes, so that the plurality of gate wires GL are connected through the same number of contact holes. The resistance deviation between the gate wirings (GL) can be minimized. For example, when each of the plurality of third gate wires GL3 and each of the plurality of second gate wires GL2 are electrically connected using each of the plurality of first gate contact parts C1, the plurality of gate wires ( GL) The variation of each resistance can be reduced. Accordingly, the deviation of the gate signal transmission speed across the plurality of gate wires GL can be minimized, and the driving stability of the display device 400 can be increased.

And, referring to FIG. 4 , the plurality of first gate contact units C1 may be located outside the plurality of power lines VDDL and the plurality of data lines DL. For example, the plurality of first gate contact units C1 and the plurality of second contact holes CH2 may be located outside the outermost power line VDDL among the plurality of power line lines VDDL, It may be located outside the data line DL, which is the outermost of the plurality of data lines DL.

In addition, the plurality of first contact holes (CH1) through which each of the plurality of data wires (DL) and each of the plurality of data link wires (DLL) contact each other is closest to the power supply wire 130 among the plurality of gate wires (GL). It is located between the gate wiring (GL) and the power supply wiring (130). For example, the plurality of first contact holes CH1 may be located above the wiring GL located at the top of the plurality of gate wirings GL, that is, the gate wiring GL closest to the power supply wiring 130. there is. And, it may be located lower than the power supply wiring 130.

Accordingly, in the display device 400 according to another embodiment of the present invention, the plurality of third gate wires GL3 and the plurality of data link wires DLL may be disposed in different areas. For example, the plurality of third gate wires GL3 include some wires GL3a made of the same material as the gate wire GL of the transistor 140 and other wires made of the same material as the conductive layer 150 ( GL3b). In addition, the plurality of date link wires include some wires (DLL1, DLL3, DLL5) made of the same material as the gate wire (GL) of the transistor 140 and other wires (DLL2, DLL2, DLL5) made of the same material as the conductive layer 150. DLL4). Accordingly, the plurality of third gate wires GL3 and the plurality of data link wires DLL may not be arranged together in the same area of the non-display area NA. Accordingly, the plurality of third gate wires GL3 and the plurality of data link wires DLL may be arranged in different areas.

Figure 6 is an enlarged plan view of a display device according to another embodiment of the present invention. Since the display device 600 shown in FIG. 6 has a different and substantially identical configuration of the plurality of gate wires GL compared to the display device 400 shown in FIGS. 4 and 5, duplicate descriptions will be omitted or briefly provided. I can explain.

Referring to FIG. 6 , the plurality of first gate wires GL1 may be made of the same material as the conductive layer 150 or the gate electrode 142 of the transistor 140. For example, the plurality of first gate wires GL1 may be made of the same material as the conductive layer 150 or the same material as the gate electrode 142 of the transistor 140.

In addition, each of the plurality of first gate wires GL1 may be contacted with each of the plurality of third gate wires GL3 using a plurality of second gate contact portions C2. The plurality of second gate contact parts C2 may be made of the same material as the source electrode 143 and the drain electrode 144 of the transistor 140. For example, when the plurality of first gate wires GL1 are made of the same material as the gate electrode 142 of the transistor 140, each of the plurality of first gate wires GL1 includes the first interlayer insulating layer 112 and It may be electrically connected to each of the plurality of second gate contact portions C2 through contact holes formed in the second interlayer insulating layer 113. In addition, when the plurality of first gate wires GL1 are made of the same material as the conductive layer 150, each of the plurality of first gate wires GL1 is connected to a plurality of wires through a contact hole formed in the second interlayer insulating layer 113. It may be electrically connected to each of the second gate contact parts C2.

In addition, each of the portions (GL3a) of the third gate wiring (GL3) made of the same material as the gate electrode 142 of the transistor 140 is formed on the first interlayer insulating layer 112 and the second interlayer insulating layer 113. It may be electrically connected to each of the plurality of second gate contact units C2 through a contact hole. In addition, each of the other portions (GL3b) of the third gate wiring (GL3) made of the same material as the conductive layer 150 is connected to a plurality of second gate contact portions (C2) through the contact holes formed in the second interlayer insulating layer 113. ) can be electrically connected to each.

The display device 600 according to another embodiment of the present invention connects each of the plurality of first gate wires GL1 and each of the plurality of third gate wires GL3 through the plurality of second gate contact parts C2. By connecting, the resistance variation in the plurality of gate wires GL can be reduced.

For example, when the plurality of first gate wires GL1 are made of the same material as the gate electrode 142 of the transistor 140, the plurality of third gate wires are made of the same material as the gate electrode 142 of the transistor 140. Each of the portions (GL3a) of (GL3) and each of the plurality of first gate wirings (GL1) may be formed with the same wiring. In addition, each of a portion (GL3b) of the plurality of third gate wires (GL3) made of the same material as the conductive layer 150 and each of the plurality of first gate wires (GL1) are formed through contact holes formed in the first interlayer insulating layer 112. It can be connected through.

In addition, when the plurality of first gate wires GL1 are made of the same material as the conductive layer 150, each of the other portions GL3b and the plurality of third gate wires GL3 made of the same material as the conductive layer 150 Each of the first gate wires GL1 may be formed with the same wire. Additionally, each of the portions GL3a of the plurality of third gate wires GL3 made of the same material as the gate electrode 142 of the transistor 140 may be connected through a contact hole formed in the first interlayer insulating layer 112 .

That is, for example, the first gate wire GL1 and the third gate wire GL3 include a part that is one wire and another part that is two wires connected through a contact hole.

Accordingly, the display device 600 according to another embodiment of the present invention electrically connects each of the plurality of first gate wires GL1 and each of the plurality of third gate wires GL3 using a plurality of third gate contact units. By connecting, the resistance variation of the plurality of gate wires GL can be reduced. Accordingly, the deviation in the transmission speed of the gate signal transmitted to each of the plurality of pixels (PX) can be minimized, and the driving stability of the display device 600 can be increased.

Figure 7 is an enlarged plan view of a display device according to another embodiment of the present invention. Since the display device 700 shown in FIG. 7 has a different and substantially identical structure of the power supply wiring 730 compared to the display device 100 shown in FIGS. 1 to 3, duplicate descriptions will be omitted or briefly described. can do.

Referring to FIG. 7 , the power supply wiring 730 extends to one end of the plurality of gate drivers 120 . Specifically, the power supply wiring 730 is formed to correspond to the display area AA, and may extend to correspond to a corner of the display area AA.

In the case of a general display device, the number of conductive layers is smaller than the number of wirings present in the non-display area, so the power supply wires cannot be arranged up to the non-display area corresponding to the unusual corner of the display area. Accordingly, the power supply wiring was placed in a non-display area excluding the special corner. Accordingly, the power voltage could be supplied only to pixels arranged in the display area excluding the unusual corner. Accordingly, in the case of pixels placed at unusual corners, the power voltage was supplied using a conductive layer different from the power supply wiring. Therefore, a high potential voltage could not be applied to the pixels placed at the unusual corners. Accordingly, the strength of the power voltage supplied to the plurality of pixels was uneven, reducing luminance uniformity.

Therefore, in the display device 700 according to another embodiment of the present invention, the power supply wire 730 is formed to extend to one end of the plurality of gate drivers 120, so that the plurality of power supply wires VDDL The drop in voltage supplied to the pixel (PX) can be reduced. For example, the power supply wire 730 is formed to extend to one end of the plurality of gate drivers 120, so that each of the plurality of power supply wires VDDL branching from the power supply wire 730 corresponds to a plurality of pixels PX. Can be connected to each. Accordingly, the display device 700 according to another embodiment of the present invention is formed with the power supply wiring 730 extending to one end of the plurality of gate drivers 120, thereby forming a plurality of pixels (P ) can reduce the voltage drop phenomenon of the voltage supplied to the voltage. Accordingly, each of the plurality of pixels PX can be supplied with a high potential voltage, and thus the luminance uniformity of the display device 700 can be improved.

Figure 8 is an enlarged plan view of a display device according to another embodiment of the present invention. Since the display device 800 shown in FIG. 8 has a different and substantially identical gate driver 820 and a plurality of gate wires GL compared to the display device 100 shown in FIGS. 1 to 3, Redundant explanations can be omitted or briefly explained.

Referring to FIG. 8, some of the plurality of stages 821, 822, 823, 824, and 825 included in the gate driver 820 are arranged to correspond to unusual corners of the display area AA. And, the gate signal is supplied to the gate wire (GL) disposed in the area corresponding to the unusual corner among the plurality of gate wires (GL). For example, the power supply wire 130 may be arranged to correspond to the display area AA, and there may be an area in the non-display area NA corresponding to the unusual corner where the power supply wire 130 is not arranged. there is. Accordingly, some of the plurality of stages 821, 822, 823, 824, and 825 may be arranged to correspond to unusual corners of the display area AA. And, the gate driver 820 includes a first stage 821 to a fifth stage 825. The first to third stages 821 to 823 are disposed in an area corresponding to an unusual corner of the display area AA. Additionally, the fourth stage 824 and the fifth stage 825 are disposed in areas that do not correspond to the unusual corners of the display area AA. Each of the first to third stages 821 to 823 is connected to a plurality of first gate wires GL1, and each of the first gate wires GL1 is connected to a plurality of second gate wires GL2. is connected to The first stage 821 to the third stage 823 transmit gate signals to each of the plurality of gate wires GL, and each of the plurality of gate wires GL is connected to the plurality of pixels PX disposed at the unusual corner. A gate signal can be transmitted. In addition, the fourth stage 824 and the fifth stage 825 arranged in the area that do not correspond to the unusual corner provide a gate signal to the pixel (PX) arranged in the area that does not correspond to the unusual corner through the gate wire (GL). can be supplied.

In the display device 800 according to another embodiment of the present invention, some of the plurality of stages 821, 822, 823, 824, and 825 correspond to unusual corners of the display area AA. By being arranged so as to do so, a stable gate signal can be supplied to the plurality of pixels (PX) arranged at the unusual corners of the display area (AA). For example, when some (821, 822, 823) of the plurality of stages (821, 822, 823, 824, 825) are arranged to correspond to the unusual corners of the display area (AA), a ratio that does not correspond to the unusual corners The length of the plurality of gate wires (GL) connected to some (821, 822, 823) of the plurality of stages (821, 822, 823, 824, and 825) may be reduced compared to the case where they are disposed in the display area (NA). . Additionally, the plurality of gate wires GL may be formed in a straight line. Accordingly, the gate signal supplied from each of the plurality of stages 821, 822, and 823 arranged to correspond to the unusual corner of the display area AA can be stably supplied to each of the plurality of pixels PX arranged at the unusual corner. there is.

And, referring to FIG. 8, a plurality of stages 821, 822, and 823 arranged to correspond to the unusual corners of the display area AA may be arranged in a step shape. Additionally, it may be disposed adjacent to the display area AA. Specifically, the plurality of stages 821, 822, and 823 arranged to correspond to the unusual corners of the display area AA may be arranged in a step shape along the unusual corners of the display area AA. It may be disposed adjacent to and corresponding to the shape of the unusual corner of the display area AA. For example, the plurality of stages 821, 822, and 823 may be adjacent to the display area AA and may not be arranged in a line to correspond to a special corner, but may be slightly staggered and arranged in a staircase shape. The display device 800 according to another embodiment of the present invention has a plurality of stages 821, 822, and 823 arranged in a staircase shape to correspond to unusual corners. Can be flexibly arranged in response to odd-shaped corners of various shapes. For example, when the corner of the display area AA has a partial shape of a circle as shown in FIG. 8, the plurality of stages 821, 822, and 823 may be arranged in steps corresponding to this. Accordingly, the corners of the non-display area NA may also be formed as unusual corners corresponding to the unusual corners of the display area AA.

And, referring to FIG. 8, the plurality of stages 821, 822, and 823 arranged to correspond to the unusual corners of the display area AA may have a small width in the horizontal direction and a large width in the vertical direction. Specifically, the plurality of stages 821, 822, and 823 arranged to correspond to the unusual corners of the display area AA, and the fourth stage 824 arranged to correspond to areas other than the unusual corners of the display area AA. and may be formed in a shape different from that of the fifth stage 825. For example, as shown in FIG. 8, the plurality of stages 821, 822, and 823 arranged to correspond to the unusual corners of the display area AA may have a small width in the horizontal direction and a large width in the vertical direction. there is. Accordingly, the display device 800 according to another embodiment of the present invention includes a plurality of stages 821, 822, and 823 with a small width in the horizontal direction and a large width in the vertical direction at the unusual corners of the display area AA. By arranging it to correspond to , a stage designed to correspond to an unusual corner of the display area AA can be arranged.

A display device according to embodiments of the present invention can be described as follows.

A display device according to an embodiment of the present invention includes a substrate including a display area having a special corner and a non-display area adjacent to the display area, the display area having a plurality of pixels each including a transistor, and the non-display area comprising: , a gate driver disposed on at least one side of the display area, a plurality of gate wires electrically connected to the gate driver to supply gate signals to a plurality of pixels, located in the non-display area and extending in the same direction as the plurality of gate wires. It may include a power supply wire and a plurality of power wires branched from the power supply wire and supplying a high potential voltage to a plurality of pixels, and the gate driver may be located in an area excluding the unusual corner.

According to another feature of the present invention, the width of the power supply wires in the direction in which the plurality of gate wires extend may be greater than or equal to the gap between the outermost power wires among the plurality of power wires.

According to another feature of the present invention, the power supply wiring may extend to one end of the plurality of gate drivers.

According to another feature of the present invention, a conductive layer between the source and drain electrodes of the transistor and the gate electrode of the transistor, a plurality of data wires parallel to the plurality of power wires, and a plurality of data wires for supplying data signals to a plurality of pixels. It is in the display area and further includes a plurality of data link wires that supply data signals to the plurality of data wires, and the power supply wire and the plurality of power wires may be made of the same material as the source electrode and drain electrode of the transistor.

According to another feature of the present invention, the plurality of data wires are made of the same material as the source electrode and drain electrode of the transistor, some of the plurality of data link wires are made of the same material as the gate electrode of the transistor, and other of the plurality of data link wires are made of the same material as the gate electrode of the transistor. Some are made of the same material as the conductive layer, and the contact hole through which each of the plurality of data wires and each of the plurality of data link wires make contact may be located between the power supply wire and the gate wire closest to the power supply wire among the plurality of gate wires. .

According to another feature of the present invention, the plurality of gate wires extend from the gate driver and are connected to a plurality of first gate wires made of the same material as the source and drain electrodes of the transistor and connected to the display area. extends to and includes a plurality of second gate wires made of the same material as the transistor gate electrode, and the contact hole through which each of the plurality of first gate wires and each of the plurality of second gate wires contacts a plurality of power wires and a plurality of data It can be located outside the wiring.

According to another feature of the present invention, the plurality of gate wires extend from the gate driver and include a plurality of first gate wires that are made of the same material as the conductive layer, the gate electrode of the transistor, or the source electrode and drain electrode of the transistor, and the display area. extends to connect a plurality of second gate wires and a plurality of first gate wires and a plurality of second gate wires made of the same material as the gate electrode of the transistor, some of which are made of the same material as the gate electrode of the transistor, and other parts of which are made of the same material as the gate electrode of the transistor. includes a plurality of third gate wires made of the same material as the conductive layer, and the display device further includes a plurality of first gate contact units for electrically connecting each of the plurality of second gate wires and each of the plurality of third gate wires. And, the first gate contact part may be located outside the plurality of power wires and the plurality of data wires.

According to another feature of the present invention, the plurality of first gate contact units are made of the same material as the source electrode and drain electrode of the transistor, and can contact the plurality of second gate wires and the plurality of third gate wires through the contact hole. there is.

According to another feature of the present invention, when the plurality of first gate wires are made of the same material as the conductive layer or the gate electrode of the transistor, the plurality of gate wires are made of the same material as the source electrode and drain electrode of the transistor, and form a contact hole. It may further include a plurality of second gate contact parts that contact the plurality of first gate wires and the plurality of second gate wires.

A display device according to another embodiment of the present invention includes a substrate including a display area with a special corner and a non-display area adjacent to the display area, the display area having a plurality of pixels each including a transistor, and the non-display area comprising: , a gate driver disposed on at least one side of the display area, a plurality of gate wires electrically connected to the gate driver to supply gate signals to a plurality of pixels, located in the non-display area and extending in the same direction as the plurality of gate wires. It includes a power supply wire and a plurality of power wires branched from the power supply wire and supplying a high potential voltage to a plurality of pixels, and the gate driver includes a plurality of stages for supplying gate signals to the plurality of gate wires. In addition, some of the plurality of stages are arranged to correspond to the special corner, and a gate signal can be supplied to the gate wire arranged in an area corresponding to the special corner among the plurality of gate wires.

According to another feature of the present invention, some of the plurality of stages may be arranged in a staircase shape.

According to another feature of the present invention, some of the plurality of stages may have a smaller width in the horizontal direction and a larger width in the vertical direction compared to other parts of the plurality of stages disposed to correspond to areas excluding the unusual corners.

According to another feature of the present invention, the deformed corner may have a round shape.

A display device according to another embodiment of the present invention includes a substrate having a special corner, a display area in which a plurality of pixels equipped with transistors are defined, and a non-display area adjacent to the display area, and a special corner on both sides of the display area. A gate driver formed in an area excluding a special corner to minimize the area of the non-display area corresponding to the non-display area, a power supply wire in the non-display area, and a plurality of power supply wires integral with the power supply wire, wherein the power supply wires are plural. It may be formed in an area corresponding to the entire display area to supply power voltage to the pixels.

According to another feature of the present invention, the width of the power supply wiring in the direction in which the plurality of gate wirings extend may be greater than or equal to the width of the display area.

According to another feature of the present invention, the power supply wiring may extend to one end of the gate driver to reduce a drop in power voltage.

According to another feature of the present invention, a conductive layer between the source and drain electrodes of the transistor and the gate electrode of the transistor is parallel to the plurality of power wires, a plurality of data wires for supplying data signals to a plurality of pixels, a plurality of data wires, It further includes a plurality of gate wires extending in a different direction from the data wires and a plurality of data link wires in a non-display area and supplying data signals to the plurality of data wires, wherein the power supply wire and the plurality of power wires are of the transistors. It may be the same material as the source electrode and drain electrode.

According to another feature of the present invention, the plurality of data wires are made of the same material as the source electrode and drain electrode of the transistor, some of the plurality of data link wires are made of the same material as the gate electrode of the transistor, and other parts are made of the same material as the conductive layer. material, and the plurality of gate wires extend from the gate driver, are connected to a plurality of first gate wires and a plurality of first gate wires made of the same material as the source electrode and drain electrode of the transistor, and extend to the display area, and the transistor gate It includes a plurality of second gate wires made of the same material as the electrode, a contact hole where each of the plurality of data wires and each of the plurality of data link wires make contact, and each of the plurality of first gate wires and each of the plurality of second gate wires make contact. The contact hole may be located so that the plurality of first gate wires are disposed in different areas from the plurality of data wires and the plurality of power wires.

According to another feature of the present invention, the plurality of data wires are made of the same material as the source electrode and drain electrode of the transistor, some of the plurality of data link wires are made of the same material as the gate electrode of the transistor, and other parts are made of the same material as the conductive layer. material, and the plurality of gate wires extend from the gate driver and extend to the conductive layer, the gate electrode of the transistor, or the plurality of first gate wires made of the same material as the source electrode and drain electrode of the transistor, and the display area, Connecting a plurality of second gate wires made of the same material as the gate electrode, a plurality of first gate wires and a plurality of second gate wires, some of which are made of the same material as the gate electrode of the transistor, and other parts made of the same material as the conductive layer. The display device includes a plurality of third gate wires, and the display device electrically connects each of the plurality of data wires and each of the plurality of data link wires to a contact hole and each of the plurality of second gate wires and each of the plurality of third gate wires. It may further include a plurality of first gate contact units, and the first gate contact unit may be positioned so that the plurality of data link wires and the plurality of third gate wires are arranged in different areas.

According to another feature of the present invention, the plurality of first gate contact portions are made of the same material as the source and drain electrodes of the transistor to minimize the resistance deviation in the plurality of gate wirings, and the plurality of second gate contact portions are formed through the contact hole. It may contact the wiring and a plurality of third gate wirings.

According to another feature of the present invention, when the plurality of first gate wires are made of the same material as the conductive layer or the gate electrode of the transistor, the plurality of gate wires are each of the plurality of first gate wires and the plurality of third gate wires. It further includes a plurality of second gate contact parts for electrically connecting, wherein the plurality of second gate contact parts are made of the same material as the source electrode and drain electrode of the transistor to minimize resistance deviation in the plurality of gate wirings. , It is possible to contact a plurality of second gate wires and a plurality of third gate wires through a contact hole.

Although embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit of the present invention. . Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

100, 400, 600, 700, 800: Display device
110: substrate
111: Gate insulating layer
112: first interlayer insulating layer
113: second interlayer insulating layer
120, 820: Gate driver
121, 821: Stage 1
122, 822: Second stage
130, 730: Power supply wiring
140: thin film transistor
141: active layer
142: Gate electrode
143: source electrode
144: drain electrode
150: conductive layer
823: Third stage
824: Stage 4
825: Stage 5

Claims (15)

A substrate comprising a display area having irregular corners and a non-display area around the display area;
a plurality of pixels in the display area including the unusual corner, each pixel including a transistor;
a gate driver disposed in the non-display area to supply a gate signal;
a first gate wire disposed in the non-display area and extending from the gate driver;
a second gate wire electrically connected to the first gate wire to transmit the gate signal to the transistor;
a power supply wire extending in the same direction as the second gate wire in the non-display area;
a plurality of power wires branched from the power supply wires and supplying high potential voltages to the plurality of pixels;
a plurality of data wires parallel to the plurality of power wires and supplying data signals to the plurality of pixels; and
A plurality of data link wires supplying the data signals to the plurality of data wires in the non-display area,
The first gate wiring and the power supply wiring are made of the same material as the source electrode and drain electrode of the transistor,
The display device wherein the plurality of data wires and the plurality of power wires are made of the same material as the source electrode and drain electrode of the transistor. According to claim 1,
The first gate wiring has two bends. According to claim 1,
The display device further includes a third gate wire disposed between the second gate wire and the gate driver. According to clause 3,
The third gate wiring has two bends. According to claim 1,
The display device wherein the gate driver is disposed in an area excluding the special corner. According to claim 1,
A display device wherein the gate driver is disposed at the unusual corner. According to clause 6,
The display device wherein the gate driver disposed at the special corner is arranged in a staircase shape along the special corner. According to clause 7,
The gate driver
A plurality of stages supplying the gate signal to the first gate wiring,
Among the plurality of stages, a stage arranged to correspond to an area of the unusual corner has a smaller horizontal width and a larger vertical width than a stage arranged to correspond to an area excluding the unusual corner. delete According to claim 1,
A display device, wherein some of the plurality of data link wires are made of the same material as the gate electrode of the transistor. According to claim 10,
Further comprising a contact hole through which each of the plurality of data wires and each of the plurality of data link wires make contact,
The contact hole is located between the power supply wire and a second gate wire closest to the power supply wire among the second gate wires. According to claim 10,
A contact hole through which the first gate wire and the second gate wire make contact is located outside the plurality of power wires and the plurality of data wires. According to clause 4,
The display device wherein the second gate wiring is made of the same material as the gate electrode of the transistor. According to claim 1,
The display device wherein the power supply wiring extends to one end of the gate driver. According to claim 1,
The display device further includes a conductive layer disposed between the source and drain electrodes of the transistor and the gate electrode of the transistor.