KR102661987B1 - Display device - Google Patents

Abstract

This specification discloses a display panel. A display panel according to various embodiments of the present specification includes a substrate having a display area and a non-display area located on the outside of the display area; gate wiring in the display area; a data line crossing the gate line; a plurality of pixel circuits configured by crossing the gate wire and the data wire; a power wire arranged in parallel with the data wire; A switching thin film transistor included in the pixel circuit; A driving thin film transistor included in the pixel circuit; a power inlet arranged in a first direction and disposed in an upper non-display area outside surrounding the display area; a data link wire connected to an end of the data wire; a pad portion provided with a data pad electrode connected to an end of the data link wire; and a ground wire disposed in the non-display area, extending from the pad portion and surrounding the display area, wherein the power wire extends from the display area to the non-display area and is arranged in the first direction.

Description

Display device {DISPLAY DEVICE}

This specification relates to a display device, and more specifically, to a display device that can achieve uniform power supply between power wirings by minimizing the voltage gap between power wirings.

The advent of the information age was accompanied by the development of display devices that display images. In recent years, the development of display devices has led to various forms such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light emitting displays (OLEDs). In particular, liquid crystal display devices and light-emitting display devices are attracting attention due to their advantages of mass production technology, ease of driving means, and high-definition implementation.

The display device includes a driver integrated circuit (IC) that provides a power supply voltage to drive a plurality of pixels. The driver IC provides power voltage to each pixel circuit through power wiring disposed in the display device.

At this time, the driver IC applies the power voltage to the common power terminal through the power inlet on the non-display area outside the display area, and the common power terminal applies the power voltage applied from the power inlet to a plurality of power wirings in parallel. authorize it as an enemy.

A display device according to the prior art forms a plurality of power wires connected to a pixel circuit on a display area and extending parallel to a first direction of the non-display area, and the common power terminal electrically connected to the plurality of power wires. can do. At this time, the common power terminal may be arranged in a second direction crossing the first direction, and the power wiring may be connected to the common power terminal through one side of the common power terminal.

Additionally, the power inlet may be disposed in a direction parallel to the first direction, and may be electrically connected to the common power terminal through the other side of the common power terminal, which is opposite to the one side of the common power terminal. A plurality of power inlets may be electrically connected to the common power terminal, and due to this structure, the power voltage applied to the common power terminal may flow through the plurality of power inlets.

However, the demand for implementing a bezel-less display by minimizing the non-display area has increased, and a display device that minimizes the non-display area by unifying the multiple power inlets has been designed.

In this display device, since the power supply voltage inflow into the common power terminal is due to a single power inlet, in distributing the power voltage from the common power terminal to multiple power wirings, the power supply voltage is distributed at a relatively long distance from the power inlet. The power wiring disposed may have a voltage drop compared to the power wiring disposed relatively close to the power inlet.

Accordingly, the power voltage provided to each pixel circuit is not constant, which may reduce the luminance uniformity of the display device, and a method for providing a constant power voltage to a plurality of pixel circuits of the display device is required.

The purpose of the present invention is to improve the luminance uniformity of a display device.

The tasks of this specification are not limited to the tasks mentioned above, and other tasks not mentioned will be clearly understood by those skilled in the art from the description below.

In order to achieve the above-described object, the present invention provides a substrate having a non-display area located on the outside of the display area; a common power terminal in a non-display area on the substrate; It may include a first resistance reduction layer and a second resistance reduction layer covering the common power terminal.

The first resistance reduction layer and the second resistance reduction layer may have various shapes on the common power terminal.

Specifically, the first resistance reduction layer and the second resistance reduction layer have a resistance increasing pattern disposed between the first resistance reduction layer and the second resistance reduction layer in a plan view, from the side to the center, and on the common power terminal. More may be included.

A display panel according to an embodiment of the present invention includes a substrate having a display area and a non-display area located on the outside of the display area; gate wiring in the display area; a data line crossing the gate line; a plurality of pixel circuits configured by crossing the gate wire and the data wire; a power wire arranged in parallel with the data wire; A switching thin film transistor included in the pixel circuit; A driving thin film transistor included in the pixel circuit; a power inlet arranged in a first direction and disposed in an upper non-display area outside surrounding the display area; a data link wire connected to an end of the data wire; a pad portion provided with a data pad electrode connected to an end of the data link wire; and a ground wire disposed in the non-display area, extending from the pad portion and surrounding the display area, wherein the power wire extends from the display area to the non-display area and is arranged in the first direction. You can.

A display panel according to an embodiment of the present invention includes a common power terminal connected to the power inlet and receiving a power voltage from an external circuit through the power inlet; and a first resistance reduction layer disposed on the common power terminal, the width of which increases from the center of one side to one side, and a second resistance reduction layer whose width increases from the center of one side to the other side. can do.

Additionally, the display panel may further include a resistance increase pattern disposed on the common power terminal between the first resistance reduction layer and the second resistance reduction layer.

Additionally, the common power terminal may be disposed in a non-display area located on the upper outer edge of the display area and a non-display area located on the lower outer edge of the display area.

Additionally, the pixel circuit further includes a first electrode and a second electrode, and the display panel includes a bank that at least partially overlaps an edge of the first electrode; And it may further include an encapsulation film on the second electrode.

Additionally, the display panel may further include a color filter disposed on the encapsulation film.

Additionally, the first resistance reduction layer and the second resistance reduction layer may be made of the same metal as the first electrode.

Additionally, the pad portion may include an area where a driving integrated circuit is mounted and an area where a flexible circuit board is mounted.

Additionally, the display panel according to an embodiment of the present invention can be applied to a light emitting display device and an organic light emitting display device.

Specific details of other embodiments are included in the detailed description and drawings.

Embodiments of the present specification can provide a display device including a pixel (P) circuit with improved luminance unevenness. Furthermore, embodiments of the present specification can provide a display device that is advantageous in securing electro-optical characteristics of a pixel (P) circuit.

The effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

Since the content of the invention described in the problem to be solved, the means for solving the problem, and the effect described above do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the content of the invention.

1 is a schematic configuration diagram of a display device to which embodiments of the present specification are applied.
FIG. 2 is a cross-sectional view showing the stacked structure of the thin film transistor region of FIG. 1.
Figure 3 is a schematic configuration diagram of a display device to which embodiments of the present specification are applied.
FIGS. 4A and 4B are enlarged plan views of the area including the power inlet, common power terminal, and part of the power wiring in the non-display area of FIG. 3.
Figure 5 is a diagram showing a cross section taken along line II' in Figure 4a.
FIGS. 6A and 6B are enlarged plan views of the area including the power inlet, common power terminal, and part of the power wiring in the non-display area of FIG. 3.
Figure 7 is a cross-sectional view taken along line II-II' in Figure 6a.
FIGS. 8A to 8D are enlarged plan views of the area including the power inlet, common power terminal, and part of the power wiring in the non-display area of FIG. 3.

The advantages and features of the present specification and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present specification are illustrative, and the present specification is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as '~after', 'after', '~next', 'before', etc., 'immediately' or 'directly' Non-consecutive cases may also be included unless ' is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

When describing the components of this specification, terms such as first and second may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the components are not limited by the term. When a component is described as being “connected,” “coupled,” or “connected” to another component, that component may be directly connected or connected to that other component, but there are no other components between each component. It should be understood that may be “interposed” or that each component may be “connected,” “combined,” or “connected” through other components.

Each feature of the various embodiments of the present invention can be combined or combined with each other partially or entirely, and various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

The size and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the size and thickness of the components shown.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings.

In this specification, various embodiments are shown and described based on an organic light emitting display device, but it should be noted that the display device 100 according to the present invention is not limited thereto.

Figure 1 is a schematic system configuration diagram of a display device 100 to which embodiments of the present invention are applied.

Referring to FIG. 1, the display device 100 has m data lines (DL1, ..., DLm, m: natural numbers) and n gate lines (GL1, ..., GLn, n: natural numbers). A panel 140, a data driver 120 that drives the m data lines (DL1, ..., DLm), and a gate driver (120) that sequentially drives the n gate lines (GL1, ..., GLn) 130), and a timing controller 110 that controls the data driver 120 and the gate driver 130.

First, the timing controller 110 operates the data driver 120 based on external timing signals such as vertical/horizontal synchronization signals (Vsync, Hsync), image data (data), and clock signal (CLK) input from the host system. A data control signal (DCS) for controlling and a gate control signal (GCS) for controlling the gate driver 130 are output. In addition, the timing controller 110 converts image data (data) input from the host system into a data signal format used by the data driver 120 and sends the converted image data (data') to the data driver 120. can be supplied.

The data driver 120 responds to the data control signal (DCS) and the converted image data (data') input from the timing controller 110, and converts the image data (data') into data that is a voltage value corresponding to a grayscale value. It is converted into a signal (analog pixel signal or data voltage) and supplied to the data lines (D1 to Dm).

In other words, the data driver 120 stores the input image data in memory under the control of the timing controller 110, and when a specific gate line is opened, the data driver 120 stores the image data in analog form. is converted into a data voltage (Vdata) and supplied to the m data lines (DL1, ..., DLm), thereby driving the m data lines (DL1, ..., DLm).

The data driver 120 may include a plurality of data driving integrated circuits (Data Driver IC, source driving integrated circuit), and these plurality of data driving integrated circuits use a tape automated bonding (TAB) method. Alternatively, it is connected to the bonding pad of the display panel 140 using the chip-on-glass (COG) method, or a chip-on-film (COF) type driving chip package is connected to the film-on-glass (FOG) method. It may be connected, may be formed directly on the display panel 140, or, depending on the case, may be formed by being integrated into the display panel 140.

In the non-display area of the display panel 140 of the display device 100, a pad structure is formed that is connected to a plurality of signal lines GL and DL arranged in the display area AA of the substrate 151. Here, the pad structure may include a plurality of metal layers and an insulating film located between each metal layer and having one or more contact holes connecting two adjacent metal layers among the plurality of metal layers.

Meanwhile, the gate driver 130 sends a scan signal (gate pulse or scan pulse, gate on signal) to the gate lines (G1 to Gn) in response to the gate control signal (GCS) input from the timing controller 110. Supplied sequentially.

Depending on the driving method, the gate driver 130 may be located on only one side of the display panel 140 as shown in FIG. 1, or may be divided into two and located on both sides of the display panel 140.

In addition, the gate driver 130 may include a plurality of gate driver integrated circuits (Gate Driver ICs), which use a tape automated bonding (TAB) method or a chip. It may be connected to the bonding pad of the display panel 140 using an on-glass (COG) method, or may be implemented as a gate in panel (GIP) type and formed directly on the display panel 140. Accordingly, it may be formed by being integrated into the display panel 140.

In this specification, the gate driver 130 is shown as being located only on one side of the display panel 140, but it should be noted that the display device 100 according to the present invention is not limited to this.

Meanwhile, each pixel P on the display panel 140 may be formed in an area defined by the data lines D1 to Dm and the gate lines G1 to Gn and arranged in a matrix form. For example, when the display panel 140 is an organic light emitting display panel, an organic light emitting diode including an anode, a cathode, an organic layer, two or more thin film transistors (TFTs), one or more capacitors, etc. circuit elements can be formed.

FIG. 2 is a diagram showing a cross-sectional structure of a display device 100 to which embodiments of the present invention are applied. Specifically, FIG. 2 shows an area including a thin film transistor (TFT) disposed in the pixel (P) circuit of FIG. 1.

Referring to FIG. 2, in the display device 100 according to an embodiment of the present invention, an auxiliary substrate 152 disposed on the substrate 151, and a buffer layer 153 disposed on the auxiliary substrate 152. ) and a thin film transistor (TFT) corresponding to each pixel (P) area, wherein the thin film transistor (TFT) includes a gate electrode 161, a semiconductor layer 162, a source electrode 163, and a drain electrode 164. Includes.

The substrate 151 may be a glass film substrate. Examples of the glass film substrate include substrates made of soda-lime glass, barium/strontium-containing glass, lead glass, aluminosilicate glass, borosilicate glass, barium borosilicate glass, or quartz.

The auxiliary substrate 152 may be disposed on the substrate 151. The auxiliary substrate 152 may be made of the same material as the substrate 151, and may also be made of polyimide, polyethersulfone, polyetherimide (PEI), and polyethylene terephthalate. It can be manufactured from PET) material. These plastic materials can be used as flexible substrates.

The buffer layer 153 may be disposed on the auxiliary substrate 152. The material forming the buffer layer 153 is not particularly limited as long as it can be formed efficiently and can appropriately secure interlayer adhesion and flatness. For example, metals such as Al, inorganic materials such as SiOx, SiOxNv, SiNx, AlOx, ZnSnOx, ITO, ZnO, IZO, ZnS, MgO or SnOx, polyimide, and caldo resin having a fluorene ring. , urethane, epoxide, polyester, polyamic acid, polyimide, polyethyleneimine, polyvinyl alcohol, polyamide, polythiol, poly((meth)acrylate) or V3D3 (trivinyltrimethylcyclotrisiloxane), HVDSO (hexamethyldisiloxane) or TVTSO (1 , 3,5-trivinyl-1,1,3,5,5-pentamethyltrisiloxane) can be formed using organic materials such as organic silicon.

The gate electrode 161 is formed on the buffer layer 153 along with the gate line GL. Additionally, the gate electrode 161 is branched from the gate line GL and is connected to the gate line GL.

The semiconductor layer 162 is formed on the gate insulating film 154 to overlap at least a portion of the gate electrode 161. Here, the semiconductor layer 162 may be formed of any one of oxide semiconductor, poly silicon (crystalline silicon), and amorphous silicon (a-Si: amorphous silicon).

An interlayer insulating layer (not shown, ILD: inter layer dielectric) may be located on the gate insulating film 154. The interlayer dielectric (ILD) may be made of silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof, but is not necessarily limited thereto.

Additionally, a passivation layer (not shown) may be located on the interlayer insulating layer. The passivation layer is provided on a thin film transistor (TFT). The passivation layer functions to protect the thin film transistor (TFT) and power wiring (PL). For example, the passivation layer may be silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), or a multilayer thereof, but is not limited thereto.

Like the data line DL, the source electrode 163 and the drain electrode 164 are formed on the gate insulating film 154 to be spaced apart from each other. Additionally, the source electrode 163 and the drain electrode 164 are disposed to overlap on both sides of the semiconductor layer 162.

Here, one of the source electrode 163 and the drain electrode 164 is branched from the data line DL and is connected to the data line DL. In addition, the other one of the source electrode 163 and the drain electrode 164, which is not connected to the data line DL, is at least partially exposed through the main contact hole penetrating the planarization layer 155 and forms the first electrode ( 171).

Additionally, when the semiconductor layer 162 is formed of an oxide semiconductor, the thin film transistor (TFT) may further include an etch stopper layer (not shown) formed on the semiconductor layer 162, where the source Electrode 163 and drain electrode 164 overlap on both sides of the etch stopper (not shown).

The first electrode 171 corresponds to at least a light emitting area of each pixel (P) area and is formed on the planarization layer 155 . In addition, the first electrode 171 is connected to the other one of the source electrode 163 and the drain electrode 164 that is not connected to the data line DL through the main contact hole penetrating the planarization layer 155. is connected to The first electrode 171 serves as an anode. Accordingly, the first electrode 171 may be made of a transparent conductive material with a relatively high work function. For example, the transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (Indium Zinc Oxide). : IZO) may be included.

In order to improve reflection efficiency, the first electrode 171 may further include a reflective film at the bottom made of a metal material with high reflection efficiency. For example, the metal material may be silver (Ag) or aluminum (Al). ) and their compounds.

The bank 172 corresponds to the outside of the light emitting area of each pixel (P) circuit and is formed on the planarization layer 155. The bank 132 defines an emission area of the display device 100 and can prevent light leakage from a non-emission area.

In addition, the bank 172 overlaps at least a portion of the edge of the first electrode 171, and the step area of the first electrode 171 is obscured by the bank 172, so that the first electrode 171 Deterioration of the organic layer 173 due to current flow concentrated in the step can be reduced.

The organic layer 173 may be formed on the entire surface of the display area AA, that is, on the entire surface of the planarization layer 155, corresponding to the entire plurality of pixel (P) circuits. Accordingly, the organic layer 173 may be formed to cover the first electrode 171 and the bank 172.

The organic layer 173 may be formed between the first electrode 171 and the second electrode 174. The organic layer 173 may emit light by combining holes supplied from the first electrode 171 and electrons supplied from the second electrode 174.

The organic layer 173 may be formed in an area corresponding to the display area AA, and the organic layer 173 may have a multi-layer structure made of organic materials having different components or compositions. For example, the organic layer 173 includes a hole injection layer (HIL), a hole transport layer (HTL, not shown), an emission layer (EML, not shown), and an electron transport layer. It may include an electron transporting layer (ETL) (not shown) and an electron injection layer (EIL).

The hole injection layer (HIL) may be located on the first electrode 171. The hole injection layer (HIL) may serve to facilitate hole injection, and may include HATCN and CuPc (cupper phthalocyanine), PEDOT (poly(3,4)-ethylenedioxythiophene), PANI (polyaniline), and NPD (N, It may be composed of one or more selected from the group consisting of N-dinaphthyl-N,N'-diphenylbenzidine), but is not limited thereto.

The hole transport layer (HTL) is located on the hole injection layer (HIL). The hole transport layer (HTL) serves to facilitate the transport of holes, and includes NPD (N,N-dinaphthyl-N,N'-diphenylbenzidine), TPD (N,N'-bis-(3-methylphenyl)-N ,N'-bis-(phenyl)-benzidine), s-TAD, and MTDATA (4,4',4"-Tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine). It may consist of one or more, but is not limited to this.

The light-emitting layer (EML) is located on the hole transport layer (HTL) and is formed between the hole transport layer (HTL) and the electron transport layer (ETL) to connect holes supplied from the first electrode 171 and the second electrode. White light is emitted by combining electrons supplied from (174).

The electron transport layer (ETL) is located on the light emitting layer (EML). The thickness of the electron transport layer (ETL) can be adjusted considering electron transport characteristics. The electron transport layer (ETL) may play a role in transporting and injecting electrons, and the electron injection layer (EIL) may be formed separately on the electron transport layer (ETL).

The electron transport layer (ETL) serves to facilitate the transport of electrons, and includes Alq3 (tris(8-hydroxyquinolino)aluminum), PBD, TAZ, spiro-PBD, BAlq, Liq (lithium quinolate), BMB-3T, and PF. -6P, TPBI, COT, and SAlq may be composed of any one or more selected from the group consisting of, but is not limited to this.

The electron injection layer (EIL) may use Alq3 (tris(8-hydroxyquinolino)aluminum), PBD, TAZ, spiro-PBD, BAlq, or SAlq, but is not limited thereto.

Here, the structure is not limited according to the embodiment of the present invention, and at least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) may be omitted. It may be possible.

Additionally, it is possible to configure the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) with two or more layers.

The second electrode 174 is formed on the entire surface of the organic layer 173, provides electrons to the light emitting layer (EML), and may serve as a cathode. The second electrode 174 is made of a transparent conductive material. For example, the transparent conductive material may include ITO or IZO.

In addition, the second electrode 174 may further include a thin metal film made of a metal material with a low work function on the side in contact with the organic layer 173. For example, the metal material may be magnesium (Mg) or silver (Ag). and their compounds.

Additionally, in the case of the display device 100, which is a top-emission organic light emitting display device, the second electrode 174 must be formed to be thin because it must have a low work function and satisfy translucency.

Accordingly, in the light emitting area of each pixel (P) area, the first electrode 171 and the second electrode 174 face each other, and the first electrode 171 and the second electrode 174 are located between the first electrode 171 and the second electrode 174. An organic light emitting device (ED) including the organic layer 173 is formed.

An encapsulation film 175 may be formed on the second electrode 174. The encapsulation film 175 prevents moisture and oxygen from penetrating into the organic light emitting device (ED). The encapsulation film 175 is made of an inorganic insulating material such as aluminum oxide (AlOx), silicon oxynitride (SiON), silicon nitride (SiNx), silicon oxide (SiO2), or benzocyclobutene or photo acryl. It may be formed as a single layer of an organic insulating material such as a laminated structure of an inorganic insulating material and an organic insulating material.

A sealing layer 156 is formed on the sealing film 175. The sealing layer 156 isolates the plurality of organic light emitting elements (ED) from the outside and blocks moisture or oxygen from penetrating into the plurality of organic light emitting elements (ED), thereby causing the plurality of organic light emitting elements (ED) to emit light due to moisture or oxygen. It plays a role in delaying the deterioration of the element (ED).

A color filter (CF, not shown) may be formed on the sealing layer 156. The color filter (CF) is formed by depositing red, green, and blue pigments in each of the red sub-pixel region, green sub-pixel region, and blue sub-pixel region and patterning them, and may include a black matrix (BM). . Additionally, when a white sub-pixel area is included, a separate color filter may not be formed in the white sub-pixel area.

FIG. 3 is a schematic plan view of the display device 100 according to embodiments of the present invention.

As shown, the display device 100 according to embodiments of the present invention is provided with a display area (AA) that displays an image and a non-display area (NA) surrounding the display area (AA).

In the display area (AA), the gate wire (GL) and the data wire (DL) intersect to define a plurality of pixel (P) circuits, and each pixel (P) circuit includes a switching thin film transistor for switching. TFT) and a driving thin film transistor (driving TFT) for driving the organic light emitting element (ED) are provided, and a power line (PL) is provided parallel to the data line (DL).

In addition, the non-display area (NA) includes a ground wire (GND), a reference power wire (not shown), a reference power supply terminal 187, a power wire (PL), and a common power supply for driving the organic light emitting device (ED). A terminal 186 and a power inlet 185 are provided.

The reference power line and the power line PL may extend from the display area AA to the non-display area NA and be arranged in a first direction, and in FIG. 3, the first direction appears as a vertical direction.

The reference power terminal 187 and the common power terminal 186 are arranged in a second direction crossing the first direction to form an upper non-display area (NA) and a lower non-display area (NA) on the outer side surrounding the display area (AA). It can be placed in two areas (NA). In Figure 3, the second direction appears as the horizontal direction. The reference power terminal 187 and the common power terminal 186 may be arranged in a direction other than the second direction and may be connected to other components at various angles.

In addition, the reference power terminal 187 and the common power terminal 186 are electrically connected to the ends of the reference power wire and the power wire PL, respectively, through one side. The reference power terminal 187 and the common power terminal 186 can apply voltage from the outside to the reference power wire and the power wire PL, respectively, through this connection.

The power inlet 185 may be arranged in the first direction and disposed in the outer upper non-display area NA surrounding the display area AA. Additionally, the end of the power inlet 185 is electrically connected to the other side of the common power terminal 186, which is opposite to the one side. The power inlet 185 can receive a power voltage from an external circuit through this connection and apply the voltage to the common power terminal 186. The power inlet 185 may be arranged in a direction other than the first direction, and may be connected to the other side of the common power terminal 186 at various angles.

In addition, the non-display area (NA) includes a gate link wire and a data link wire (DLL) connected to the ends of the gate and data wires (GL, DL) configured in the display area (AA), and these gate link wires and data link wires. It is connected to the end of the wiring (DLL) and consists of a pad portion (not shown) equipped with a gate and data pad electrode (not shown). At this time, the pad portion is provided with an area (ICA) where a driving IC is mounted and an area (FPCBA) where a flexible printed circuit board (FPCB) is mounted for electrical connection to an external driving circuit board.

FIGS. 4A and 4B show a power inlet 185 and a common power terminal 186 disposed in the outer upper non-display area (NA) surrounding the display area (AA) of FIG. 3 according to embodiments of the present invention. ) and a part of the power wiring (PL). In addition, FIG. 5 is a diagram showing a cross-section taken along line II' in FIG. 4A. This cross-sectional view can be applied equally to FIG. 4A as well as FIG. 4B, and can therefore be a diagram explaining the cross-section of FIG. 4B. . If the components of FIGS. 4A, 4B, and 5 have the same content as the components shown in FIGS. 1 to 3, their description will be omitted below.

4A, 4B, and 5, in the display device 100 according to embodiments of the present invention, a substrate 151, an auxiliary substrate 152 disposed on the substrate 151, and the auxiliary substrate 152 are provided. A buffer layer 153 disposed on the substrate 152, a gate insulating layer 154 disposed on the buffer layer 153, a common power terminal 186 disposed on the gate insulating layer 154, and the common power terminal ( 186), a first resistance reduction layer 181 and a second resistance reduction layer 182, a planarization layer 155 and the first resistance reduction layer 181 disposed on the common power terminal 186. , a second resistance reduction layer 182, and a sealing layer 156 disposed on the planarization layer 155.

As shown, in the upper non-display area (NA), a power line (PL) is connected to the pixel (P) area of the display area (AA) and extends into the non-display area (NA), and an end of the power line (PL) It includes a common power terminal 186 electrically connected to and a power inlet 185 electrically connected to the common power terminal 186.

At least one power line PL may be disposed and extend in a first direction. The first direction appears as a longitudinal direction in the drawing.

The common power terminal 186 is arranged in a second direction crossing the first direction, that is, perpendicular to the first direction, and is connected to at least one of the power wiring PL and one of the common power terminals 186. It is electrically connected through the side. The one side appears below the common power terminal 186 in FIG. 4A, but according to various embodiments of the present invention, the present invention is not limited thereto.

The power inlet 185 extends in the first direction and is electrically connected to the other side of the common power terminal 186 through an end. The other side is opposite to the one side on the common power terminal 186 and is shown above the common power terminal 186 in FIG. 4A, but the present invention is not limited to this according to various embodiments of the present invention.

*The power wiring (PL), common power terminal 186, and power inlet 185 may be arranged in various directions other than the first direction and the second direction, and each may be arranged at various angles with other components. can be connected

Additionally, the power inlet 185 is electrically connected to a driver IC (not shown) through the remaining end not connected to the common power terminal 186. Accordingly, the power voltage of the display device 100 is supplied to the pixel (P) circuit of the display area (AA) via the driving IC, power inlet 185, common power terminal 186, and power wiring (PL) in that order. supplied.

The location and number of the power inlets 185 may change along with the reduction of the non-display area (NA). In the drawing, the power inlet 185 is a single wire, and is electrically connected to the common power terminal 186 through the central part of the other side of the common power terminal 186, but is not limited to this and is not limited to a single wire, but multiple wires. It can be connected by wiring and can be connected at any location on the other side of the common power terminal 186 other than the central portion of the other side.

A first resistance reduction layer 181 and a second resistance reduction layer 182 covering the common power terminal 186 may be disposed on the common power terminal 186. The first resistance reduction layer 181 and the second resistance reduction layer 182 may be made of a transparent conductive material with a relatively high work function. For example, the transparent conductive material is Indium Tin Oxide (ITO). Alternatively, it may include indium zinc oxide (IZO).

The first resistance reduction layer 181 and the second resistance reduction layer 182 are provided with the common power terminal 186 disposed in the upper non-display area (NA) outside surrounding the display area (AA) in the plan view. It is placed in an area, but is not limited to this, and may be placed in an area where the common power terminal 186 is located in the lower non-display area (NA) on the outer side surrounding the display area (AA) in the plan view.

Referring to FIG. 4A, the first resistance reduction layer 181 and the second resistance reduction layer 182 cover the common power terminal 186 in a plan view and may have the shape of a right triangle. This right-angled triangle may be arranged with its hypotenuse facing the power inlet 185, so its base is disposed on one side of the common power terminal 186 to which the power wiring PL is connected, and the other base is It may be placed on the left/right side of the common power terminal 186. In the drawing, the base of the right triangle is disposed with a separation distance from one side and the left and right sides of the common power terminal 186, but is disposed on one side and the left and right sides of the common power terminal 186 without a separation distance. It can be.

Referring to FIGS. 4A and 4B , the first resistance reduction layer 181 and the second resistance reduction layer 182 cover the common power terminal 186 in a plan view and have a shape whose width decreases from the side to the center. You can have The width may be defined as the length between the one side and the other side of the common power terminal 186. In the drawing, the first resistance reduction layer 181 and the second resistance reduction layer 182 are arranged at a distance from one side and the left/right sides of the common power terminal 186, but the common power supply terminal 186 has no separation distance. It may be placed on one side and on the left/right side of the terminal 186. However, the shapes of the first resistance reduction layer 181 and the second resistance reduction layer 182 are not limited to this and may have various shapes.

The first resistance reduction layer 181 and the second resistance reduction layer 182 cover the common power terminal 186 and may be arranged to be spaced apart on the left and right sides of the power inlet 185. The power inlet 185 is electrically connected to the other side of the common power terminal 186, and this connection location is not only at the center of the other side of the common power terminal 186 but also at other locations on the other side. possible.

The first resistance reduction layer 181 and the second resistance reduction layer 182 may be made of the same material as the first electrode 171 disposed in the display area AA. Additionally, the first resistance reduction layer 181 and the second resistance reduction layer 182 may be formed through the same process as the process of forming the first electrode 171.

Referring to FIGS. 6A, 6B, and 7, a third resistance reduction layer 183 and a fourth resistance reduction layer 183 are formed on the first resistance reduction layer 181 and the second resistance reduction layer 182 in the non-display area NA, respectively. A resistance reduction layer 184 may be disposed. The third resistance reduction layer 183 and the fourth resistance reduction layer 184 may cover at least a portion of the first resistance reduction layer 181 and the second resistance reduction layer 182, respectively.

The third resistance reduction layer 183 and the fourth resistance reduction layer 184 may be arranged in a shape with the same characteristics as the first resistance reduction layer 181 and the second resistance reduction layer 182. That is, the third resistance reduced layer 183 and the fourth resistance reduced layer 184 cover at least a portion of the first resistance reduced layer 181 and the second resistance reduced layer 182, respectively, and the first resistance reduced layer 184 It may be arranged corresponding to the area and the third area.

The third resistance reduction layer 183 and the fourth resistance reduction layer 184 cover the first resistance reduction layer 181 and the second resistance reduction layer 182 disposed on the common power terminal 186. and can be arranged to be spaced apart on the left and right sides of the power inlet 185.

The third resistance reduction layer 183 and the fourth resistance reduction layer 184 may be made of a transparent conductive material with a relatively high work function. For example, the transparent conductive material is Indium Tin Oxide (ITO). Alternatively, it may include indium zinc oxide (IZO). Additionally, the third resistance reduction layer 183 and the fourth resistance reduction layer 184 may be made of the same material as the second electrode 174 disposed in the display area AA. Additionally, the third resistance reduction layer 183 and the fourth resistance reduction layer 184 may be formed through the same process as the process of forming the second electrode 174.

Referring to FIGS. 8A to 8D , a resistance increase pattern 190 may be disposed on the common power terminal 186 in the non-display area (NA). The resistance increase pattern 190 is on the common power terminal 186 and is disposed between the first resistance reduction layer 181 and the second resistance reduction layer 182 to ensure a voltage difference between the power lines PL. can be reduced. The resistance increase pattern 190 may be arranged in the form of an engraving on the common power terminal 186, and this engraving may be in the form of a portion of the common power terminal 186 being carved out or penetrating the common power terminal 186. It may be in one form. This form of the resistance increasing pattern 190 causes a decrease in the thickness and an increase in resistance of the common power terminal 186, and causes a voltage drop in the power voltage passing through the area where the resistance increasing pattern 190 is formed. At this time, the resistance increase pattern 190 is disposed on the common power terminal 186 relatively close to the power inlet 185, and the common power terminal 186 is relatively far from the power inlet 185. ), the voltage deviation inside the common power terminal 186 can be reduced, and thus the voltage deviation of the power voltage supplied to the power wiring PL can be reduced.

The resistance increasing pattern 190 may have various shapes, such as circular or oval, and may be arranged in various sizes.

Additionally, a plurality of resistance increase patterns 190 may be disposed on the common power terminal 186. Referring to FIGS. 8A and 8B , a plurality of resistance increase patterns 190 may be arranged in the horizontal direction of the common power terminal 186. Additionally, the resistance increase pattern 190 may be arranged in different sizes, and may be arranged to increase in size from the outer part to the center of the common power terminal 186 in a plan view. According to FIGS. 8A and 8B, the resistance increase patterns 190 are arranged in a line, but the present invention is not limited thereto.

Referring to FIGS. 8C and 8D, the resistance increase pattern 190 may be arranged as a plurality of rows on the common power terminal 186. A plurality of resistance increase patterns 190 may be arranged at regular or irregular intervals.

The common power terminal 186 may be disposed in the non-display area (NA) at the lower outer portion of the display area (AA). Unlike when the common power terminal 186 is disposed in the upper outer non-display area (NA) of the display area (AA), when the common power terminal 186 is disposed in the lower outer non-display area (NA), the power wire (PL) is connected to the common power line (PL). One side adjacent to the display area (AA) of the power terminal 186 is electrically connected to the common power terminal 186.

The first to fourth resistance reduction layers 181-184 may be disposed on the common power terminal 186 disposed in the non-display area (NA) at the lower outer portion of the display area (AA), It may be arranged in the shape of four to four resistance reduction layers (181-184). The common power terminal 186 disposed in the non-display area (NA) at the lower outer portion of the display area (AA) has a power wire (PL) connected to one side adjacent to the display area (AA) of the common power terminal 186. Therefore, compared to the shape of the first to fourth resistance reduction layers 181 to 184 disposed in the non-display area NA on the upper outer portion of the display area AA, the shapes are arranged upside down.

The first to fourth resistance reduction layers 181 - 184 and the resistance increase pattern 190 are electrically connected to the common power terminal 186 and affect the voltage flow of the common power terminal 186. The common power terminal 186 serves as a terminal for distributing the power voltage applied from the power inlet 185 to the power wiring PL, and the voltage applied to the power wiring PL is applied to the display area. It flows into the driving thin film transistor (driving TFT) on the pixel (P) area located at (AA). At this time, the voltage flowing into the driving thin film transistor (driving TFT) affects the gate-source voltage to adjust the luminance of the pixel (P). When a difference in voltage between the power lines (PL) occurs, the display device A difference in luminance occurs between pixels (P) within (100). The first to fourth resistance reduction layers 181-184 and the resistance increase pattern 190 are disposed on the common power terminal 186 through various shapes shown in the present invention, and the voltage difference between the power lines PL can be arranged to reduce . Ultimately, the first to fourth resistance reduction layers 181 - 184 and the resistance increase pattern 190 can minimize the difference in luminance between pixels P in the display device 100 through various shapes shown in the present invention.

Although embodiments of the present specification have been described in detail with reference to the attached drawings, the present specification is not necessarily limited to these embodiments, and various modifications may be made without departing from the technical spirit thereof. Accordingly, the embodiments disclosed in this specification are not intended to limit the technical idea of the present invention, but rather to explain it, and the scope of the technical idea of the present invention is not limited by these embodiments. Each feature of the various embodiments of the present invention can be partially or entirely combined or combined with each other, and can be technically linked and driven in various ways by those skilled in the art, and each embodiment can be performed independently of each other or together in a related relationship. It may be implemented. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

100: display device
181: first resistance reduction layer
182: second resistance reduction layer
183: Third resistance reduction layer
184: Fourth resistance reduction layer
185: Power inlet
186: Common power terminal
PL: power wiring
190: Resistance increase pattern

Claims (10)

A substrate having a display area and a non-display area located outside the display area;
a plurality of pixels configured by crossing a plurality of gate wires and a plurality of data wires in the display area and including a first electrode and a second electrode;
a bank that at least partially overlaps an edge of the first electrode;
an encapsulation film on the second electrode;
a power wire arranged in parallel with the data wire in the display area;
a power inlet extending in a first direction parallel to the arrangement direction of the data wires in an outer non-display area surrounding the display area and receiving a power voltage from an external circuit;
a common power terminal connected to the power inlet, extending in a second direction intersecting the first direction, and supplying the power voltage to the power wiring;
a reference power terminal disposed in parallel with the common power terminal in the non-display area between the common power terminal and the display area;
a data link wire connected to an end of the data wire;
a pad portion provided with a data pad electrode connected to an end of the data link wire in the non-display area; and
a ground wire disposed in the non-display area and extending from the pad portion to surround the display area;
The power wiring extends from the display area to the non-display area and is arranged in the first direction. According to claim 1,
It is disposed on the common power terminal, and further includes a first resistance reduction layer whose width becomes wider as it goes from the center of one side to one side, and a second resistance reduction layer whose width becomes wider as it goes from the center of one side to the other side. , organic light emitting display device. According to clause 2,
The organic light emitting display device further includes a resistance increase pattern disposed on the common power terminal between the first resistance reduction layer and the second resistance reduction layer. According to clause 2,
The common power terminal includes a first common power terminal disposed in a non-display area located on the upper outer edge of the display area and a second common power terminal disposed in a non-display area located on the lower outer edge of the display area. Organic light emitting display device. delete According to claim 1,
An organic light emitting display device further comprising a color filter disposed on the encapsulation film. According to clause 2,
The first resistance reduced layer and the second resistance reduced layer are made of the same metal as the first electrode. According to claim 1,
The pad portion includes an area on which a driving integrated circuit is mounted and an area on which a flexible circuit board is mounted. According to claim 1,
Further comprising a gate link wire connected to an end of the gate wire,
The pad portion further includes a gate pad electrode connected to an end of the gate link wire, and an insulating film disposed between the gate pad electrode and the data pad electrode. delete