KR102659827B1 - Display apparatus and method of operating the same - Google Patents

Abstract

The display device includes a display panel, a timing control circuit, and a power management integrated circuit. The display panel includes a plurality of pixels. The timing control circuit controls the operation of the display panel and stores a plurality of defect patterns to indicate on the display panel that a plurality of defect phenomena have occurred when the display panel is driven. The power management integrated circuit supplies a first power supply voltage to the timing control circuit, monitors whether a plurality of defect phenomena occur, and indicates that the first defect phenomenon has occurred when a first defect phenomenon is sensed among the plurality of defect phenomena. The first defect phenomenon data is stored and the display panel is shut down. When the first defect phenomenon is sensed, the timing control circuit controls the display panel to display a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns before the power management integrated circuit shuts down the display panel. do.

Description

Display device and method of operating the same {DISPLAY APPARATUS AND METHOD OF OPERATING THE SAME}

The present invention relates to a display device, and more specifically, to a display device capable of effectively analyzing and detecting defects and a method of driving the display device.

Recently, flat panel displays (FPD), which are easily large-area, thin, and lightweight, have been widely used as display devices. These flat displays include liquid crystal displays (LCD) and plasma display panels ( Plasma display panel (PDP), organic light emitting display (OLED), etc. are being used.

The display device as described above includes a display panel that displays an image and a timing control circuit that controls the operation of the display panel, and a power management integrated circuit (PMIC) that supplies power to the timing control circuit. It can be included. Meanwhile, defects may occur for various reasons in the display device as described above, and the display device may be implemented to record the cause of the defect in case analysis of the defect phenomenon is needed in the future.

One object of the present invention is to provide a display device that can effectively perform defect analysis and detection.

Another object of the present invention is to provide a method of driving the display device.

To achieve the above object, a display device according to embodiments of the present invention includes a display panel, a timing control circuit, and a power management integrated circuit (PMIC). The display panel includes a plurality of pixels. The timing control circuit controls the operation of the display panel and stores a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred when the display panel is driven. The power management integrated circuit supplies a first power voltage to the timing control circuit, monitors whether the plurality of defect phenomena occur, and detects a first defect phenomenon among the plurality of defect phenomena. In this case, first defect phenomenon data indicating that the first defect phenomenon has occurred is stored and the display panel is shut down. When the first defect phenomenon is sensed, the timing control circuit selects a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns before the power management integrated circuit shuts down the display panel. Control the display panel to display.

In one embodiment, the timing control circuit may include a storage unit, a defective pattern display control unit, and an image processing unit. The storage unit may store the plurality of defective patterns. When the first defect phenomenon is sensed, the defect pattern display control unit reads the first defect phenomenon data indicating that the first defect phenomenon has occurred from the power management integrated circuit, and based on the first defect phenomenon data, Thus, the first defect pattern corresponding to the first defect phenomenon can be read from the storage unit. The image processing unit may generate image data corresponding to the first defective pattern.

In one embodiment, the power management integrated circuit may include a power supply unit, a sensing unit, and a storage unit. The power supply unit may generate the first power voltage based on an external power voltage. The sensing unit may monitor whether the plurality of defective phenomena occur. The storage unit may store the first defect phenomenon data when the first defect phenomenon is sensed.

In one embodiment, the timing control circuit may include a first failure detection pin, and the power management integrated circuit may include a second failure detection pin. The timing control circuit may check whether the first defect phenomenon occurs using the first and second defect detection pins.

In one embodiment, the power management integrated circuit may transition the voltage level of the second defect detection pin from the first level to the second level when the first defect phenomenon is sensed. The timing control circuit determines that the voltage level of the second defect detection pin has transitioned from the first level to the second level through the first defect detection pin and receives the first defect phenomenon data from the power management integrated circuit. can be read.

In one embodiment, the display device may further include a second power management integrated circuit that generates a gate clock signal and includes a third defect detection pin. To synchronize the operation of shutting down the display panel, the second defect detection pin and the third defect detection pin may be electrically connected to each other.

In one embodiment, the timing control circuit may check whether the first failure phenomenon occurs by periodically checking whether the power management integrated circuit stores the first failure phenomenon data.

In one embodiment, the timing control circuit reads the first failure phenomenon data from the power management integrated circuit when the power management integrated circuit senses the first failure phenomenon and stores the first failure phenomenon data. You can.

In one embodiment, the display panel may not be shut down immediately after the first defect phenomenon is sensed. The timing control circuit may read the first failure phenomenon data from the power management integrated circuit for a first time immediately after the first failure phenomenon is sensed. The display panel may display the first defective pattern for a second time after the first time and be shut down after the second time.

In one embodiment, the power management integrated circuit may shut down the display panel by blocking the first power voltage supplied to the timing control circuit.

In one embodiment, the display device further includes a gate driving circuit connected to a plurality of gate lines of the display panel, generating a plurality of gate signals based on a gate clock signal and applying them to the plurality of gate lines. can do. The power management integrated circuit may supply the gate clock signal to the gate driving circuit.

In one embodiment, the power management integrated circuit may shut down the display panel by blocking the gate clock signal supplied to the gate driving circuit.

In one embodiment, the display device is connected to a plurality of data lines of the display panel, generates a plurality of data voltages based on image data provided from the timing control circuit, and applies the plurality of data voltages to the plurality of data lines. It may further include a data driving circuit. The power management integrated circuit may supply a second power voltage to the data driving circuit.

In one embodiment, the power management integrated circuit may shut down the display panel by blocking the second power voltage supplied to the data driving circuit.

In one embodiment, the plurality of defect phenomena may include at least one of defective over current protection, defective zero current detection, defective temperature, and defective communication.

In order to achieve the other object, in a method of driving a display device according to embodiments of the present invention, a display panel including a plurality of pixels, an operation of the display panel is controlled, and a plurality of pixels are displayed when the display panel is driven. A timing control circuit that stores a plurality of defective patterns for displaying on the display panel that defective phenomena have occurred is turned on. A power management integrated circuit (PMIC) is used to monitor whether the plurality of defects occur. When a first defect phenomenon is sensed among the plurality of defect phenomena, a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns is displayed on the display panel. After displaying the first defective pattern on the display panel, the display panel is shut down.

In one embodiment, the timing control circuit may include a first failure detection pin, and the power management integrated circuit may include a second failure detection pin. The timing control circuit may check whether the first defect phenomenon occurs using the first and second defect detection pins.

In one embodiment, in displaying the first defect pattern on the display panel, when the first defect phenomenon is sensed, first defect phenomenon data indicating that the first defect phenomenon has occurred in the power management integrated circuit is provided. You can save it. When the first defect phenomenon is sensed, the voltage level of the second defect detection pin may be transitioned from the first level to the second level. It is possible to confirm that the voltage level of the second defect detection pin has transitioned from the first level to the second level through the first defect detection pin and to read the first defect phenomenon data from the power management integrated circuit. . The first defect pattern corresponding to the first defect phenomenon may be read based on the first defect phenomenon data. Image data corresponding to the first defective pattern may be generated and provided to the display panel.

In one embodiment, the timing control circuit may check whether the first failure phenomenon occurs by periodically checking whether the power management integrated circuit stores first failure phenomenon data indicating that the first failure phenomenon has occurred.

In one embodiment, when displaying the first defect pattern on the display panel, when the first defect phenomenon is sensed, the first defect phenomenon data may be stored in the power management integrated circuit. When the first defect phenomenon is sensed and the first defect phenomenon data is stored in the power management integrated circuit, the first defect phenomenon data may be read from the power management integrated circuit. The first defect pattern corresponding to the first defect phenomenon may be read based on the first defect phenomenon data. Image data corresponding to the first defective pattern may be generated and provided to the display panel.

According to the display device and its driving method according to the embodiments of the present invention as described above, a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred are stored in advance, and a monitoring operation is performed when driving. Thus, when at least one of a plurality of defect phenomena is sensed, a corresponding defect pattern can be displayed before shutting down the display panel. Accordingly, users and engineers can identify the defect type without additional work. Specifically, in the case of customer process defects and reliability defects, the defect analysis schedule can be shortened and recovery costs can be minimized. In the case of defects in the company's manufacturing process, the defect type can be minimized. It can be easy to identify and calculate the defect rate. Therefore, defect analysis and detection can be performed accurately and efficiently without additional cost.

1 is a block diagram showing a display device according to embodiments of the present invention.
Figure 2 is a diagram for explaining the operation of a display device according to embodiments of the present invention.
FIG. 3 is a block diagram illustrating an example of a timing control circuit included in a display device according to embodiments of the present invention.
FIG. 4 is a diagram for explaining the operation of the timing control circuit of FIG. 3.
FIG. 5 is a block diagram illustrating an example of a power management integrated circuit included in a display device according to embodiments of the present invention.
FIG. 6 is a block diagram illustrating an example of a timing control circuit and a power management integrated circuit included in a display device according to embodiments of the present invention.
Figure 7 is a timing diagram for explaining the operation of a display device according to embodiments of the present invention.
FIG. 8 is a block diagram illustrating another example of a timing control circuit and a power management integrated circuit included in a display device according to embodiments of the present invention.
Figure 9 is a block diagram showing a display device according to embodiments of the present invention.
FIG. 10 is a block diagram illustrating another example of a timing control circuit and a power management integrated circuit included in a display device according to embodiments of the present invention.
11 is a flowchart showing a method of driving a display device according to embodiments of the present invention.
12 and 13 are flowcharts showing examples of steps for displaying defective patterns in a method of driving a display device according to embodiments of the present invention.

Regarding the embodiments of the present invention disclosed in the text, specific structural and functional descriptions are merely illustrative for the purpose of explaining the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms. It should not be construed as limited to the embodiments described in.

Since the present invention can be subject to various changes and can have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific disclosed form, and should be understood to include all changes, equivalents, and substitutes included in the spirit and technical scope of the present invention.

Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The above terms may be used for the purpose of distinguishing one component from another component. For example, a first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component without departing from the scope of the present invention.

When a component is said to be "connected" or "connected" to another component, it is understood that it may be directly connected to or connected to the other component, but that other components may exist in between. It should be. On the other hand, when it is mentioned that a component is “directly connected” or “directly connected” to another component, it should be understood that there are no other components in between. Other expressions that describe the relationship between components, such as "between" and "immediately between" or "neighboring" and "directly adjacent to" should be interpreted similarly.

The terms used in this application are only used to describe specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as “comprise” or “have” are intended to designate the existence of a described feature, number, step, operation, component, part, or combination thereof, but are not intended to indicate the presence of one or more other features or numbers. It should be understood that this does not exclude in advance the possibility of the existence or addition of steps, operations, components, parts, or combinations thereof.

In the present invention, each layer (film), region, electrode, pattern or structure is formed “on”, “on top” or “under” the object, substrate, and each layer (film), region, electrode or pattern. When referred to as being, it means that each layer (film), region, electrode, pattern, or structure is formed directly on or below the substrate, each layer (film), region, or pattern, or is located under another layer (film). , other regions, other electrodes, other patterns, or other structures may be additionally formed on the object or substrate.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the technical field to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and unless clearly defined in the present application, should not be interpreted as having an ideal or excessively formal meaning. .

Meanwhile, if an embodiment can be implemented differently, functions or operations specified within a specific block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed substantially simultaneously, or the blocks may be performed in reverse depending on the functions or operations involved.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions for the same components are omitted.

1 is a block diagram showing a display device according to embodiments of the present invention. Figure 2 is a diagram for explaining the operation of a display device according to embodiments of the present invention.

Referring to FIGS. 1 and 2 , the display device 10 includes a display panel 100, a timing control circuit 200, and a power management integrated circuit (PMIC) 500. The display device 10 may further include a gate driving circuit 300 and a data driving circuit 400.

The display panel 100 is driven (i.e., displays an image) based on output image data (DAT). The display panel 100 is connected to a plurality of gate lines GL and a plurality of data lines DL. The plurality of gate lines GL may extend in the first direction DR1, and the plurality of data lines DL may extend in a second direction that intersects (for example, is perpendicular to) the first direction DR1. It can be extended to (DR2).

The display panel 100 includes a plurality of pixels (PX) arranged in a matrix form. Each of the plurality of pixels PX may be electrically connected to one of the plurality of gate lines GL and one of the plurality of data lines DL. Although not shown in detail, the display panel 100 may be divided into a display area including a plurality of pixels PX and a peripheral area surrounding the display area.

In one embodiment, the display panel 100 is a liquid crystal display panel, and each of the plurality of pixels PX may be a pixel for a liquid crystal display panel including liquid crystal and a driving transistor. In another embodiment, the display panel 100 is an organic light emitting display panel, and each of the plurality of pixels PX may be a pixel for an organic light emitting display panel including an organic light emitting diode and a driving transistor. . In another embodiment, the display panel 100 may be a micro LED (light emitting diode) display panel, an inorganic light emitting display panel, or a quantum dot light emitting display panel. However, the present invention is not limited to this, and the display panel 100 and the plurality of pixels (PX) may be implemented in various ways.

In one embodiment, the plurality of pixels PX may include a plurality of red pixels that output red light, a plurality of green pixels that output green light, and a plurality of blue pixels that output blue light. In another embodiment, the plurality of pixels PX include a plurality of yellow pixels that output yellow light, a plurality of cyan pixels that output cyan light, and a plurality of magenta pixels that output magenta light. may include. In another embodiment, the plurality of pixels PX may further include a plurality of white pixels that output white light or may include pixels that output light of other colors.

The timing control circuit 200 controls the operations of the display panel 100, the gate driving circuit 300, the data driving circuit 400, and the power management integrated circuit 500. The timing control circuit 200 receives input image data (IDAT) and input control signal (ICONT) from an external device (eg, a host device or a graphics processing device). The input image data IDAT may include pixel data for a plurality of pixels PX. The input control signal (ICONT) may include a master clock signal, a data enable signal, a vertical synchronization signal, and a horizontal synchronization signal.

The timing control circuit 200 generates output image data (DAT) based on input image data (IDAT). For example, the timing control circuit 200 performs image quality correction, spot correction, color correction (ACC), and/or dynamic capacitance compensation (DCC) for input image data (IDAT). Output image data (DAT) can be generated by performing this operation.

The timing control circuit 200 includes a first control signal for controlling the power management integrated circuit 500 and the gate driving circuit 300 based on the input control signal (ICONT), and a first control signal for controlling the data driving circuit 400. Generates a second control signal (DCONT). The first control signal may include a vertical start control signal (STV), a gate clock control signal (CPV), etc. The second control signal DCONT may include a horizontal start signal, a data clock signal, a polarity control signal, and a data load signal.

The power management integrated circuit 500 generates the first power voltage OV1 and the second power voltage OV2 based on the external power voltage VEXT. The first power voltage OV1 is supplied to the timing control circuit 200 and used to drive the timing control circuit 200, and the second power voltage OV2 is supplied to the data driving circuit 400 to drive the data driving circuit ( 400) can be used to drive.

The power management integrated circuit 500 generates a vertical start pulse (STVP) and a gate clock signal (CKV) based on an external power supply voltage (VEXT), a vertical start control signal (STV), and a gate clock control signal (CPV). The vertical start pulse (STVP) and the gate clock signal (CKV) may be supplied to the gate driving circuit 300 and used to drive the gate driving circuit 300. Although FIG. 1 shows one gate clock control signal (CPV) and one gate clock signal (CKV), depending on the embodiment, a plurality of gate clock signals may be generated based on a plurality of gate clock control signals. Additionally, an inverted gate clock signal having a phase opposite to that of the gate clock signal CKV may also be generated.

The gate driving circuit 300 is connected to the display panel 100 through a plurality of gate lines GL and generates a plurality of gate signals GS based on the vertical start pulse (STVP) and the gate clock signal CKV. creates . The gate driving circuit 300 may sequentially provide/apply a plurality of gate signals GS to a plurality of gate lines GL.

The data driving circuit 400 is connected to the display panel 100 through a plurality of data lines DL, and is connected to a plurality of analog-type output image data DAT based on the second control signal DCONT and digital output image data DAT. Generates data voltages (DV) of The data driving circuit 400 sequentially applies a plurality of data voltages DV to a plurality of lines (e.g., a plurality of horizontal lines) of the display panel 100 through a plurality of data lines DL. Can be provided/authorized.

In one embodiment, the gate driving circuit 300 may be an amorphous silicon gate (ASG) unit integrated in the peripheral area of the display panel 100. In another embodiment, the gate driving circuit 300 may be disposed at any location outside the display panel 100.

In one embodiment, the timing control circuit 200 and the power management integrated circuit 500 may be attached on a printed circuit board (PCB), and the data drive circuit 400 may be attached on a flexible circuit board (PCB). FPCB) can be attached. For example, the flexible circuit board may electrically connect the circuit board and the display panel 100. For example, the circuit board 250 and the flexible circuit board may be electrically connected by an anisotropic conductive film (ACF), and the flexible circuit board and the display panel 100 may be electrically connected to each other.

Depending on the embodiment, the data driving circuit 400 may be mounted on the display panel 100 or connected to the display panel 100 in the form of a tape carrier package (TCP). Depending on the embodiment, the data driver 500 may be integrated into the display panel 100.

In the display device 10 according to embodiments of the present invention, the power management integrated circuit 500 may be implemented by applying sensing circuit technology. For example, the power management integrated circuit 500 senses various parameters such as voltage, current, temperature, time, and data patterns, and as a result of the detection, a specific phenomenon (e.g., abnormality and/or defect phenomenon) is detected. In the case of action, depending on the phenomenon expressed, compensation operation (e.g., voltage variation), supplementary operation (e.g., data update), protection operation (e.g., display device 10 and/or display It may be implemented to perform panel 100 shutdown (shut down), etc.

As described above, in order to shut down the display panel 100 when at least one of a plurality of defective phenomena occurs by applying the detection circuit technology, the power management integrated circuit 500 monitors whether the plurality of defective phenomena occur. (monitoring), and when at least one defect phenomenon is sensed among the plurality of defect phenomena, defect phenomenon data (FD) indicating that the sensed defect phenomenon has occurred is stored and the display panel 100 is shut down. The specific structure and operation of the power management integrated circuit 500 will be described later with reference to FIG. 5 and the like.

In one embodiment, the plurality of defects are not errors related to the electrical/physical connection of components included in the display device 10, but are driving errors that occur when driving the display panel 100, that is, errors in the display device 100. It may indicate errors related to the operation of driving circuits (e.g., timing control circuit 200, gate driving circuit 300, data driving circuit 400, and power management integrated circuit 500).

In one embodiment, the power management integrated circuit 500 may shut down the display panel 100 by blocking the first power voltage OV1 supplied to the timing control circuit 200. In another embodiment, the power management integrated circuit 500 may shut down the display panel 100 by blocking the gate clock signal CKV supplied to the gate driving circuit 300. In another embodiment, the power management integrated circuit 500 may shut down the display panel 100 by blocking the second power voltage OV2 supplied to the data driving circuit 400. Depending on the embodiment, the power management integrated circuit 500 shuts down the display panel 100 by simultaneously blocking two or more of the first power voltage (OV1), the second power voltage (OV2), and the gate clock signal (CKV). You can also do it.

Additionally, in the display device 10 according to embodiments of the present invention, in shutting down the display panel 100 when at least one of the plurality of defect phenomena occurs by applying the detection circuit technology, the defect phenomenon occurs. It can be implemented to display a defective pattern to confirm that the display panel 100 has been shut down before shutting down the display panel 100. For example, as shown in FIG. 2, when no defects occur after the display device 10 is powered on, the display device 10 and the display panel 100 operate normally. The image is displayed normally, and if a specific defect occurs during operation, a fault pattern corresponding to the specific defect is displayed for a predetermined time so that the user can first confirm that the specific defect has occurred. (fault pattern), the display panel 100 may be shut down after the predetermined time has elapsed.

As described above, in order to display the defect pattern before at least one of the plurality of defect phenomena occurs and the display panel 100 is shut down, the timing control circuit 200 operates when the display panel 100 is driven. A plurality of defect patterns are stored to display on the display panel 100 that the plurality of defect phenomena have occurred, and when the specific defect phenomenon occurs and is sensed by the power management integrated circuit 500, the specific defect phenomenon is detected. indicates that the occurrence has occurred, reads the defect phenomenon data (FD) stored in the power management integrated circuit 500, reads a defect pattern corresponding to the defect phenomenon data (FD), and generates defect image data (FDAT) corresponding to the read defect pattern. is generated and provided to the data driving circuit 400 and the display panel 100. The specific structure and operation of the timing control circuit 200 will be described later with reference to FIG. 3 and the like.

FIG. 3 is a block diagram illustrating an example of a timing control circuit included in a display device according to embodiments of the present invention. FIG. 4 is a diagram for explaining the operation of the timing control circuit of FIG. 3.

Referring to FIGS. 3 and 4 , the timing control circuit 200 may include a storage unit 210, a defective pattern display control unit 220, and an image processing unit 230. The timing control circuit 200 may further include a control signal generator 240.

The storage unit 210 may store a plurality of defect patterns FP to indicate that the plurality of defect phenomena have occurred. For example, the storage unit 210 may include a buffer, register, or memory. For example, the memory may include Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory, Phase Change Random Access Memory (PRAM), Resistance Random Access Memory (RRAM), Nano Floating Gate Memory (NFGM), Non-volatile memory such as Polymer Random Access Memory (PoRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), and/or volatile memory such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. may include.

In one embodiment, the plurality of defect phenomena may include at least one of defective over current protection, defective zero current detection, defective temperature, and defective communication. For example, the overcurrent protection failure may occur due to a line short, the zero current detection failure may occur when current leaks into a part where current should not flow, and the temperature failure may occur in the display device ( 10) This may occur when the temperature of the internal and/or specific chip exceeds a predetermined range, and the communication failure occurs between the timing control circuit 200 and other components (e.g., the power management integrated circuit 500). It may be caused by an I2C (Inter-Integrated Circuit) communication error.

In one embodiment, when the plurality of defect phenomena include the overcurrent protection defect, the zero current detection defect, the temperature defect, and the communication defect, the plurality of defect patterns FP as shown in FIG. 4 are The first failure pattern (FP1) indicates that an overcurrent protection failure (FOCP) has occurred, the second failure pattern (FP2) indicates that a zero current detection failure (FZCD) has occurred, and the second failure pattern (FP2) indicates that a temperature failure (FTEMP) has occurred. It may include a third failure pattern (FP3) to indicate that a communication failure (FI2C) has occurred, and a fourth failure pattern (FP4) to indicate that a communication failure (FI2C) has occurred. However, the present invention is not limited to this, and the plurality of defect phenomena may further include various defect phenomena that may occur when the display panel 100 is driven, and accordingly, the plurality of defect patterns FP The number may also change.

In one embodiment, the plurality of defective patterns FP may be identical to any display pattern previously stored for driving the display panel 100. In another embodiment, the plurality of defect patterns FP may be dedicated patterns for displaying only the plurality of defect phenomena. For example, the first failure pattern (FP1) corresponding to an overcurrent protection failure (FOCP) may be a pattern that displays a white screen, and the third failure pattern (FP3) corresponding to a temperature failure (FTEMP) may be a pattern that displays a blue screen. It may be a display pattern, but the present invention is not limited thereto.

When a specific defect phenomenon is sensed by the power management integrated circuit 500, the defect pattern display control unit 220 reads defect phenomenon data (FD) indicating that the specific defect phenomenon has occurred from the power management integrated circuit 500. And, based on the defect phenomenon data FD, a specific defect pattern corresponding to the specific defect phenomenon can be read from the storage unit. In FIG. 3, it is illustrated that the specific defect phenomenon is an overcurrent protection defect (FOCP) and the defect pattern display control unit 220 reads the first defect pattern FP1 corresponding to the overcurrent protection defect (FOCP). However, the present invention It may not be limited to this.

The image processing unit 230 generates output image data (DAT) based on input image data (IDAT) and defective image data (FDAT) based on the specific defective pattern (eg, first defective pattern (FP1)). ) can be created. Output image data (DAT) and defective image data (FDAT) are provided to the display panel 100 through the data driving circuit 400, and the display panel 100 displays the image normally based on the output image data (DAT). (normal display in FIG. 2), and the specific defect pattern can be displayed based on defective image data (FDAT) (fault pattern in FIG. 2).

In one embodiment, the image processor 230 may selectively perform image quality correction, spot correction, color characteristic compensation, and/or active capacitance compensation on the input image data IDAT.

The control signal generator 240 may generate a vertical start control signal (STV), a gate clock control signal (CPV), and a second control signal (DCONT) based on the input control signal (ICONT).

FIG. 5 is a block diagram illustrating an example of a power management integrated circuit included in a display device according to embodiments of the present invention.

Referring to FIG. 5 , the power management integrated circuit 500 may include a power supply unit 510, a sensing unit 530, and a storage unit 540. The power management integrated circuit 500 may further include a clock supply unit 520.

The power supply unit 510 may generate the first power voltage OV1 and the second power voltage OV2 based on the external power voltage VEXT. For example, the power supply unit 510 may include a voltage regulator such as a switching regulator, a linear regulator, etc.

The clock supply unit 520 may generate a vertical start pulse (STVP) and a gate clock signal (CKV) based on the external power voltage (VEXT), the vertical start control signal (STV), and the gate clock control signal (CPV). For example, the clock supply unit 520 may include a start pulse generation circuit and a level shifter.

The sensing unit 530 may monitor whether the plurality of defective phenomena occur. For example, the sensing unit 530 receives the first power voltage (OV1), the second power voltage (OV2), the vertical start pulse (STVP), the gate clock signal (CKV), and detects a voltage abnormality and/or a current abnormality. It may be implemented by sensing whether this occurs, and including a voltage meter and/or a current meter for this purpose. In another example, the sensing unit 530 may receive a temperature signal (TEMP) to sense whether a temperature abnormality occurs, and may be implemented to include a temperature sensor. In another example, the sensing unit 530 may be implemented to include a timer for measuring time, a pattern detector for detecting a specific data pattern, etc.

The sensing unit 530 may generate a sensing signal (SEN) indicating the result of a monitoring operation and/or a sensing operation. For example, when the plurality of defect phenomena are not sensed, the sensing signal SEN has a first logic level, and when at least one of the plurality of defect phenomena is sensed, the sensing signal SEN has a second logic level. Can have logical levels.

When at least one of the plurality of defect phenomena, that is, a specific defect phenomenon, is sensed by the sensing unit 530, the storage unit 540 may store defect phenomenon data (FD) indicating that the specific defect phenomenon has occurred. there is. The defect phenomenon data FD stored in the storage unit 540 may be output at the request of the timing control circuit 200. For example, similar to the storage unit 210 of FIG. 3, the storage unit 540 may include a buffer, a register, or a memory, such as EEPROM, flash memory, PRAM, RRAM, NFGM, PoRAM, and MRAM. , may include non-volatile memory such as FRAM and/or volatile memory such as DRAM, SRAM, etc.

FIG. 6 is a block diagram illustrating an example of a timing control circuit and a power management integrated circuit included in a display device according to embodiments of the present invention.

Referring to FIG. 6 , the timing control circuit 200a may include a first failure detection pin (FPIN1), and the power management integrated circuit 500a may include a second failure detection pin (FPIN2).

The first and second defect detection pins FPIN1 and FPIN2 may be electrically connected to each other, and are not included in the existing timing control circuit and power management integrated circuit, but are included in the timing control circuit 200a and the power management integrated circuit 500a. It may be a newly added pin. For example, a pin may mean a contact pad or a contact pin, but may not be limited thereto.

The timing control circuit 200a and the power management integrated circuit 500a are the timing control circuit 200 and the power management integrated circuit 500 of FIG. 1, respectively, and the timing control circuit 200 of FIG. 3 and the power management integrated circuit 500 of FIG. 5, respectively. It may have substantially the same structure as the management integrated circuit 500. For example, the first defect detection pin (FPIN1) may be connected to the defect pattern display control unit 220 of FIG. 3, and the second defect detection pin (FPIN2) may be connected to the sensing unit 530 of FIG. 5.

In the embodiment of FIG. 6 , the timing control circuit 200a may check whether a specific defect phenomenon occurs using the first and second defect detection pins FPIN1 and FPIN2.

Specifically, when the specific defect phenomenon is sensed by the sensing unit 530, the power management integrated circuit 500a sets the voltage level of the second defect detection pin FPIN2 to the first level (for example, high ( high level) to a second level (e.g., low level), and the timing control circuit 200a controls the second defect detection pin FPIN2 through the first defect detection pin FPIN1. It can be confirmed that the voltage level has transitioned from the first level to the second level (① in FIG. 6).

After confirming that the voltage level of the second defect detection pin (FPIN2) has transitioned from the first level to the second level through the first defect detection pin (FPIN1), the timing control circuit 200a performs a power management integration. The defect phenomenon data FD stored in the storage unit 540 corresponding to the specific defect phenomenon can be read from the circuit 500a (② in FIG. 6). For example, the timing control circuit 200a transmits one read request (RREQ) to the power management integrated circuit 500a, and the power management integrated circuit 500a responds to the read request (RREQ) by sending a timing control circuit ( Defect phenomenon data (FD) may be transmitted to 200a). For example, communication between timing control circuit 200a and power management integrated circuit 500a may be I2C communication.

Figure 7 is a timing diagram for explaining the operation of a display device according to embodiments of the present invention.

In Figure 7, F/S represents a fault status, I/F represents an interface (e.g., I2C communication) between the timing control circuit and the power management integrated circuit, and D/O represents Shows the display operation of the display panel 100.

Referring to FIG. 7, a specific defect phenomenon is sensed at a first time point (t1), and accordingly, the defect state (F/S) is a normal state (OK) before the first time point (t1) and the defect state (F/S) is a normal state (OK) before the first time point (t1). Afterwards, it may be in a defective state (NG). For example, the level of the sensing signal (SEN) of FIG. 5 and/or the voltage level of the second defect detection pin (FPIN2) of FIG. 6 may correspond to the defect state (F/S) of FIG. 7.

The display panel 100 may not be shut down immediately after the specific defect phenomenon is sensed (that is, immediately after the first time point t1). The timing control circuit 200 indicates that the specific defect phenomenon has occurred from the power management integrated circuit 500 during a first time T1 immediately after the specific defect phenomenon is sensed, and the defect phenomenon stored in the power management integrated circuit 500 Data (FD) can be read. Accordingly, the display panel 100 can normally display an image during the first time T1, just as before the specific defect phenomenon is sensed.

The timing control circuit 200 generates defective image data (FDAT) corresponding to the read defective phenomenon data (FD), and the display panel 100 generates defective image data (FDAT) after a first time (T1) based on the defective image data (FDAT). A defect pattern corresponding to the specific defect phenomenon may be displayed for a second time T2 and may be shut down after the second time T2. Accordingly, between the time when the specific defect phenomenon is sensed (i.e., the first time t1) and the time when the display panel 100 is shut down, an amount equal to the sum of the first time T1 and the second time T2 is applied. Delay may occur.

In one embodiment, the second time T2 may be equal to one frame section in which the display panel 100 displays one frame image or may be an integer multiple of one frame section. The first time T1 may be shorter than the second time T2.

FIG. 8 is a block diagram illustrating another example of a timing control circuit and a power management integrated circuit included in a display device according to embodiments of the present invention. Hereinafter, descriptions overlapping with FIG. 6 will be omitted.

Referring to FIG. 8 , unlike the embodiment of FIG. 6 , the timing control circuit 200b and the power management integrated circuit 500b of FIG. 8 may not include a defect detection pin. The timing control circuit 200b and the power management integrated circuit 500b are the timing control circuit 200 and the power management integrated circuit 500 of FIG. 1, respectively, and the timing control circuit 200 of FIG. 3 and the power management integrated circuit 500 of FIG. 5, respectively. It may have substantially the same structure as the management integrated circuit 500.

In the embodiment of FIG. 8 , the timing control circuit 200b may periodically check whether the power management integrated circuit 500b stores defect phenomenon data FD to determine whether a specific defect phenomenon occurs.

Specifically, the timing control circuit 200b transmits a read request (PRREQ) repeatedly (e.g., at predetermined periods) to the power management integrated circuit 500b, so that the power management integrated circuit 500b receives defect phenomenon data. You can periodically check whether (FD) is saved (① in FIG. 8).

When the power management integrated circuit 500b senses the specific defect phenomenon and stores the defect phenomenon data (FD), the power management integrated circuit 500b responds to the read request (PRREQ) of the timing control circuit 200b. Defect phenomenon data (FD) may be transmitted to the timing control circuit 200b.

Figure 9 is a block diagram showing a display device according to embodiments of the present invention. Hereinafter, descriptions overlapping with FIG. 1 will be omitted.

Referring to FIG. 9 , the display device 10a includes a display panel 100, a timing control circuit 200, a first power management integrated circuit 502, and a second power management integrated circuit 504. The display device 10a may further include a gate driving circuit 300 and a data driving circuit 400.

Except for including two power management integrated circuits 502 and 504, the display device 10a of FIG. 9 may be substantially the same as the display device 10 of FIG. 1. The power management integrated circuits 502 and 504 may be implemented by dividing the power management integrated circuit 500 of FIG. 1 into two parts.

The first power management integrated circuit 502 generates a first power supply voltage (OV1) and a second power supply voltage (OV2) based on the external power supply voltage (VEXT). The second power management integrated circuit 504 generates a vertical start pulse (STVP) and a gate clock signal (CKV) based on the external power supply voltage (VEXT), the vertical start control signal (STV), and the gate clock control signal (CPV). do. The first power management integrated circuit 502 may include the power supply 510 of FIG. 5 and the second power management integrated circuit 504 may include the clock supply 520 of FIG. 5 .

In addition, the first and second power management integrated circuits 502 and 502 monitor whether the plurality of defect phenomena occur, and when at least one defect phenomenon is sensed among the plurality of defect phenomena, the sensed defect phenomenon is detected. Bad phenomenon data (FD) indicating that a phenomenon has occurred is stored and the display panel 100 is shut down. The first and second power management integrated circuits 502 and 504 each include a portion of the sensing unit 530 of FIG. 5 and may each include the storage unit 540 of FIG. 5 . Depending on the embodiment, the sensing unit 530 and the storage unit 540 of FIG. 5 may be implemented to be included in only one of the first and second power management integrated circuits 502 and 502.

FIG. 10 is a block diagram illustrating another example of a timing control circuit and a power management integrated circuit included in a display device according to embodiments of the present invention. Hereinafter, descriptions overlapping with FIG. 6 will be omitted.

Referring to FIG. 10, the timing control circuit 200a includes a first failure detection pin (FPIN1), the first power management integrated circuit 502a includes a second failure detection pin (FPIN2), and the second power management integrated circuit 502a includes a second failure detection pin (FPIN2). The management integrated circuit 504a may include a third failure detection pin (FPIN3). The first, second, and third defect detection pins FPIN1, FPIN2, and FPIN3 may be electrically connected to each other.

The timing control circuit 200a is the timing control circuit 200 of FIG. 9 and may have substantially the same structure as the timing control circuit 200 of FIG. 3. The first and second power management integrated circuits 502a and 504a are the first and second power management integrated circuits 502 and 504 of FIG. 9, respectively, and are substantially similar to the power management integrated circuit 500 of FIG. 5, respectively. can have the same structure. For example, the second and third defect detection pins FPIN2 and FPIN3 may each be connected to a portion of the sensing unit 530 of FIG. 5 .

In the embodiment of FIG. 10 , the timing control circuit 200a may check whether a specific defect phenomenon occurs using the first, second, and third defect detection pins FPIN1, FPIN2, and FPIN3.

Specifically, when the specific defect phenomenon is sensed by the sensing unit 530, one of the first and second power management integrated circuits 502a and 504a detects the second and third defect detection pins FPIN2 and FPIN3. ) transitions one of the voltage levels from the first level to the second level, and at this time, the second and third defect detection pins (FPIN2, FPIN3) are electrically connected to each other, so the second and third defect detection pins (FPIN2) , FPIN3), when the voltage level of one of them transitions, the voltage levels of both the second and third defect detection pins FPIN2 and FPIN3 may transition. The timing control circuit 200a may confirm that the voltage level of the second and third defect detection pins FPIN2 and FPIN3 has transitioned from the first level to the second level through the first defect detection pin FPIN1. There is (① in Figure 10).

After the timing control circuit 200a confirms that the voltage level of the second and third defect detection pins FPIN2 and FPIN3 has transitioned from the first level to the second level through the first defect detection pin FPIN1, the timing control circuit 200a In this way, the defect phenomenon data FD stored in the storage unit 540 and corresponding to the specific defect phenomenon can be read from one of the first and second power management integrated circuits 502a and 504a (② in FIG. 10 ).

In the embodiment of FIG. 10 , the second defect detection pin FPIN2 and the third defect detection pin FPIN3 may be electrically connected to each other to synchronize the operation of shutting down the display panel 100. As described above, the first and second power management integrated circuits 502a and 504a perform different functions, for example, the first power management integrated circuit 502a generates power supply voltages OV1 and OV2. And the second power management integrated circuit 504a is implemented to generate the gate clock signal CKV, so that the power supply voltages OV1 and OV2 and the gate clock signal supplied from the two power management integrated circuits 502a and 504a By electrically connecting the second defect detection pin (FPIN2) and the third defect detection pin (FPIN3) to simultaneously block (CKV), the operation of shutting down the display panel 100 can be synchronized.

11 is a flowchart showing a method of driving a display device according to embodiments of the present invention.

Referring to FIGS. 1 and 11 , in the method of driving a display device according to embodiments of the present invention, the display device 10 is powered on (step S100). Specifically, the power management integrated circuit 500 generates/supplies the first power voltage (OV1), the second power voltage (OV2), and the gate clock signal (CKV), thereby forming the display panel 100 and the timing control circuit 200. ), the gate driving circuit 300 and the data driving circuit 400 can be turned on.

The power management integrated circuit 500 is used to monitor whether a plurality of defective phenomena occur (step S200). As described above, the plurality of defects are not errors related to the electrical/physical connection of components included in the display device 10, but are driving errors that occur when driving the display panel 100, that is, driving the display device. It can indicate errors related to the operation of the circuit.

When a specific defect phenomenon is sensed among the plurality of defect phenomena (step S300: Yes), it is stored in the timing control circuit 200 and displayed on the display panel 100 that the plurality of defect phenomena have occurred. Among the plurality of defective patterns, a specific defective pattern corresponding to the specific defective phenomenon is displayed on the display panel 100 (step S400), and after displaying the specific defective pattern on the display panel 100, the display panel ( 100) is shut down (step S500).

12 and 13 are flowcharts showing examples of steps for displaying defective patterns in a method of driving a display device according to embodiments of the present invention.

Referring to FIGS. 1, 6, 11, and 12, in displaying the specific defect pattern on the display panel 100 (step S400), the timing control circuit 200a includes a first defect detection pin (FPIN1), The power management integrated circuit 500a includes a second defect detection pin (FPIN2), and the timing control circuit 200a uses the first and second defect detection pins (FPIN1 and FPIN2) to determine whether the specific defect phenomenon occurs. You can check it.

Specifically, when the specific defect phenomenon is sensed, defect phenomenon data (FD) indicating that the specific defect phenomenon has occurred is stored in the power management integrated circuit 500a (step S610), and the power management integrated circuit 500a The voltage level of the second defect detection pin FPIN2 may be transitioned from the first level to the second level (step S620).

In addition, the timing control circuit 200a confirms that the voltage level of the second defect detection pin (FPIN2) has transitioned from the first level to the second level through the first defect detection pin (FPIN1) and performs power management integration. Reading defect phenomenon data FD from the circuit 500a (step S630), reading the specific defect pattern corresponding to the specific defect phenomenon based on the read defect phenomenon data FD (step S640), Defective image data (FDAT) corresponding to a specific defective pattern may be generated and provided to the data driving circuit 400 and the display panel 100 (step S650).

Meanwhile, although not shown, even when the power management integrated circuit is separated into two as described above with reference to FIGS. 9 and 10, the specific defect pattern may be displayed similar to that described above with reference to FIG. 12.

1, 8, 11, and 13, in displaying the specific defect pattern on the display panel 100 (step S400), the timing control circuit 200b and the power management integrated circuit 500b use a defect detection pin. It is not included, and the timing control circuit 200b may periodically check whether the power management integrated circuit 500b stores defect phenomenon data FD to determine whether the specific defect phenomenon occurs.

Specifically, when the specific defect phenomenon is sensed, defect phenomenon data (FD) indicating that the specific defect phenomenon has occurred is stored in the power management integrated circuit 500b (step S710). Step S710 may be substantially the same as step S610 of FIG. 12.

When the power management integrated circuit 500b senses the specific defect phenomenon and stores defect phenomenon data (FD), the timing control circuit 200b manages power during a periodic check operation for the power management integrated circuit 500b. Defect phenomenon data FD can be read from the integrated circuit 500b (step S720).

The timing control circuit 200b reads the specific defect pattern corresponding to the specific defect phenomenon based on the read defect phenomenon data (FD) (step S730), and generates defect image data (FDAT) corresponding to the specific defect pattern. may be generated and provided to the data driving circuit 400 and the display panel 100 (step S740). Steps S730 and S740 may be substantially the same as steps S640 and S650 of FIG. 12, respectively.

The present invention can be applied to display devices and various devices and systems including the same. Therefore, the present invention is applicable to a personal computer (PC), a workstation, a laptop, a cellular phone, a smart phone, an MP3 player, a personal digital assistant (PDA), a portable multimedia player (PMP), Digital TV, digital camera, portable game console, navigation device, wearable device, IoT (Internet of Things) device, IoE (Internet of Everything) device, e-book ), VR (Virtual Reality) devices, AR (Augmented Reality) devices, drones, etc. can be usefully used in electronic systems.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that you can.

Claims (20)

A display panel including a plurality of pixels;
a timing control circuit that controls the operation of the display panel and stores a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred when the display panel is driven; and
A first power voltage is supplied to the timing control circuit, monitoring whether the plurality of defect phenomena occurs, and when a first defect phenomenon is sensed among the plurality of defect phenomena, the first defect phenomenon is detected. A power management integrated circuit (PMIC) that stores first defect phenomenon data indicating that a phenomenon has occurred and shuts down the display panel,
When the first defect phenomenon is sensed, the timing control circuit selects a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns before the power management integrated circuit shuts down the display panel. Controls the display panel to display,
A display device wherein the plurality of defect phenomena include at least one of defective overcurrent protection, defective zero current detection, defective temperature, and defective communication. A display panel including a plurality of pixels;
a timing control circuit that controls the operation of the display panel and stores a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred when the display panel is driven; and
A first power voltage is supplied to the timing control circuit, monitoring whether the plurality of defect phenomena occurs, and when a first defect phenomenon is sensed among the plurality of defect phenomena, the first defect phenomenon is detected. A power management integrated circuit (PMIC) that stores first defect phenomenon data indicating that a phenomenon has occurred and shuts down the display panel,
When the first defect phenomenon is sensed, the timing control circuit selects a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns before the power management integrated circuit shuts down the display panel. Controls the display panel to display,
The timing control circuit is,
a storage unit storing the plurality of defective patterns;
When the first defect phenomenon is sensed, the first defect phenomenon data indicating that the first defect phenomenon has occurred is read from the power management integrated circuit, and the first defect phenomenon data is read from the storage unit based on the first defect phenomenon data. a defective pattern display control unit that reads the first defective pattern corresponding to a first defective phenomenon; and
A display device comprising an image processing unit that generates image data corresponding to the first defective pattern. 3. The power management integrated circuit of claim 2, wherein:
a power supply unit that generates the first power voltage based on an external power voltage;
A sensing unit that monitors whether the plurality of defective phenomena occur; and
A display device comprising a storage unit that stores the first defect phenomenon data when the first defect phenomenon is sensed. A display panel including a plurality of pixels;
a timing control circuit that controls the operation of the display panel and stores a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred when the display panel is driven; and
A first power voltage is supplied to the timing control circuit, monitoring whether the plurality of defect phenomena occurs, and when a first defect phenomenon is sensed among the plurality of defect phenomena, the first defect phenomenon is detected. A power management integrated circuit (PMIC) that stores first defect phenomenon data indicating that a phenomenon has occurred and shuts down the display panel,
When the first defect phenomenon is sensed, the timing control circuit selects a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns before the power management integrated circuit shuts down the display panel. Controls the display panel to display,
the timing control circuit includes a first failure detection pin, the power management integrated circuit includes a second failure detection pin,
The timing control circuit determines whether the first defect phenomenon occurs using the first and second defect detection pins. According to claim 4,
The power management integrated circuit transitions the voltage level of the second defect detection pin from the first level to the second level when the first defect phenomenon is sensed,
The timing control circuit determines that the voltage level of the second defect detection pin has transitioned from the first level to the second level through the first defect detection pin and receives the first defect phenomenon data from the power management integrated circuit. A display device characterized in that it reads. According to claim 4,
further comprising a second power management integrated circuit that generates a gate clock signal and includes a third failure detection pin;
A display device wherein the second defect detection pin and the third defect detection pin are electrically connected to each other to synchronize the operation of shutting down the display panel. A display panel including a plurality of pixels;
a timing control circuit that controls the operation of the display panel and stores a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred when the display panel is driven; and
A first power voltage is supplied to the timing control circuit, monitoring whether the plurality of defect phenomena occurs, and when a first defect phenomenon is sensed among the plurality of defect phenomena, the first defect phenomenon is detected. A power management integrated circuit (PMIC) that stores first defect phenomenon data indicating that a phenomenon has occurred and shuts down the display panel,
When the first defect phenomenon is sensed, the timing control circuit selects a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns before the power management integrated circuit shuts down the display panel. Controls the display panel to display,
The timing control circuit is configured to periodically check whether the power management integrated circuit stores the first defect phenomenon data to determine whether the first defect phenomenon occurs. According to claim 7,
The timing control circuit is characterized in that it reads the first failure phenomenon data from the power management integrated circuit when the power management integrated circuit senses the first failure phenomenon and stores the first failure phenomenon data. display device. A display panel including a plurality of pixels;
a timing control circuit that controls the operation of the display panel and stores a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred when the display panel is driven; and
A first power voltage is supplied to the timing control circuit, monitoring whether the plurality of defect phenomena occurs, and when a first defect phenomenon is sensed among the plurality of defect phenomena, the first defect phenomenon is detected. A power management integrated circuit (PMIC) that stores first defect phenomenon data indicating that a phenomenon has occurred and shuts down the display panel,
When the first defect phenomenon is sensed, the timing control circuit selects a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns before the power management integrated circuit shuts down the display panel. Controls the display panel to display,
The display panel is not shut down immediately after the first defect phenomenon is sensed,
The timing control circuit reads the first failure phenomenon data from the power management integrated circuit for a first time immediately after the first failure phenomenon is sensed,
The display panel is configured to display the first defective pattern for a second time after the first time and to be shut down after the second time. According to claim 1,
The display device wherein the power management integrated circuit shuts down the display panel by blocking the first power voltage supplied to the timing control circuit. A display panel including a plurality of pixels;
a timing control circuit that controls the operation of the display panel and stores a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred when the display panel is driven; and
A first power voltage is supplied to the timing control circuit, monitoring whether the plurality of defect phenomena occurs, and when a first defect phenomenon is sensed among the plurality of defect phenomena, the first defect phenomenon is detected. A power management integrated circuit (PMIC) that stores first defect phenomenon data indicating that a phenomenon has occurred and shuts down the display panel,
When the first defect phenomenon is sensed, the timing control circuit selects a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns before the power management integrated circuit shuts down the display panel. Controls the display panel to display,
It further includes a gate driving circuit connected to a plurality of gate lines of the display panel, generating a plurality of gate signals based on a gate clock signal and applying them to the plurality of gate lines,
The display device, wherein the power management integrated circuit supplies the gate clock signal to the gate driving circuit. According to claim 11,
The display device wherein the power management integrated circuit shuts down the display panel by blocking the gate clock signal supplied to the gate driving circuit. According to claim 1,
It further includes a data driving circuit connected to a plurality of data lines of the display panel, generating a plurality of data voltages based on image data provided from the timing control circuit and applying them to the plurality of data lines,
The display device, wherein the power management integrated circuit supplies a second power voltage to the data driving circuit. According to claim 13,
The display device wherein the power management integrated circuit shuts down the display panel by blocking the second power voltage supplied to the data driving circuit. delete A display panel including a plurality of pixels, and a timing control circuit that controls the operation of the display panel and stores a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred when the display panel is driven. Step of powering on (power on);
Monitoring whether the plurality of defects occur using a Power Management Integrated Circuit (PMIC);
When a first defect phenomenon is sensed among the plurality of defect phenomena, displaying a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns on the display panel; and
After displaying the first defective pattern on the display panel, shutting down the display panel,
A method of driving a display device, wherein the plurality of defect phenomena include at least one of defective overcurrent protection, defective zero current detection, defective temperature, and defective communication. A display panel including a plurality of pixels, and a timing control circuit that controls the operation of the display panel and stores a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred when the display panel is driven. Step of powering on (power on);
Monitoring whether the plurality of defects occur using a Power Management Integrated Circuit (PMIC);
When a first defect phenomenon is sensed among the plurality of defect phenomena, displaying a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns on the display panel; and
After displaying the first defective pattern on the display panel, shutting down the display panel,
the timing control circuit includes a first failure detection pin, the power management integrated circuit includes a second failure detection pin,
The timing control circuit determines whether the first defect phenomenon occurs using the first and second defect detection pins. The method of claim 17, wherein displaying the first defective pattern on the display panel comprises:
storing first defect phenomenon data indicating that the first defect phenomenon has occurred in the power management integrated circuit when the first defect phenomenon is sensed;
Transitioning the voltage level of the second defect detection pin from a first level to a second level when the first defect phenomenon is sensed;
Confirming that the voltage level of the second defect detection pin has transitioned from the first level to the second level through the first defect detection pin and reading the first defect phenomenon data from the power management integrated circuit. ;
reading the first defect pattern corresponding to the first defect phenomenon based on the first defect phenomenon data; and
A method of driving a display device, comprising generating image data corresponding to the first defective pattern and providing the image data to the display panel. A display panel including a plurality of pixels, and a timing control circuit that controls the operation of the display panel and stores a plurality of defect patterns for displaying on the display panel that a plurality of defect phenomena have occurred when the display panel is driven. Step of powering on (power on);
Monitoring whether the plurality of defects occur using a Power Management Integrated Circuit (PMIC);
When a first defect phenomenon is sensed among the plurality of defect phenomena, displaying a first defect pattern corresponding to the first defect phenomenon among the plurality of defect patterns on the display panel; and
After displaying the first defective pattern on the display panel, shutting down the display panel,
The timing control circuit is configured to periodically check whether the power management integrated circuit stores first defect phenomenon data indicating that the first defect phenomenon has occurred to determine whether the first defect phenomenon occurs. method. The method of claim 19, wherein displaying the first defective pattern on the display panel comprises:
storing the first failure phenomenon data in the power management integrated circuit when the first failure phenomenon is sensed;
sensing the first defect phenomenon and reading the first defect phenomenon data from the power management integrated circuit when the first defect phenomenon data is stored in the power management integrated circuit;
reading the first defect pattern corresponding to the first defect phenomenon based on the first defect phenomenon data; and
A method of driving a display device, comprising generating image data corresponding to the first defective pattern and providing the image data to the display panel.