KR102657230B1 - Solar cell and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a P-type semiconductor substrate whose front surface is textured; a tunnel oxide film located on the rear side of the P-type semiconductor substrate; a polysilicon layer located behind the tunnel oxide layer; an emitter layer located inside the polysilicon film and containing N-type impurities; a lower passivation film located behind the emitter layer; a lower electrode located on the rear surface of the lower passivation film and penetrating the lower passivation film and making contact with the emitter layer; an upper passivation film located on the front surface of the P-type semiconductor substrate; a front surface full layer located between the upper passivation film and the P-type semiconductor substrate and containing P-type impurities; and an upper electrode located on the front surface of the upper passivation film and penetrating the upper passivation film and contacting the entire surface layer of the front surface. It relates to a solar cell including a semiconductor substrate, where the emitter is located on the back side of the semiconductor substrate and a surface electric field layer is formed on the front side, thereby minimizing the voltage loss of the light receiver due to high concentration doping or the current loss of the light receiver due to low concentration doping. , it is possible to improve the open-circuit voltage and current characteristics and charging rate of solar cells.

Description

Solar cell and manufacturing method thereof {SOLAR CELL AND MANUFACTURING METHOD THEREOF}

The present invention relates to solar cells and methods of manufacturing solar cells.

Recently, as the depletion of existing energy resources such as oil and coal is expected, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as next-generation batteries that directly convert solar energy into electrical energy using semiconductor devices.

A solar cell is a device that converts light energy into electrical energy using the photovoltaic effect. Depending on its constituent materials, it is divided into silicon solar cells, thin film solar cells, dye-sensitized solar cells, and organic polymer solar cells. In such solar cells, it is very important to increase the conversion efficiency (Efficiency), which is related to the rate of converting incident sunlight into electrical energy.

The purpose of the present invention is to provide a highly efficient solar cell and a method for manufacturing the same.

In order to achieve the object of the present invention as described above and realize the characteristic effects of the present invention described later, the characteristic configuration of the present invention is as follows.

According to one embodiment of the present invention, a P-type semiconductor substrate whose front surface is textured; a tunnel oxide film located on the rear side of the P-type semiconductor substrate; a polysilicon layer located behind the tunnel oxide layer; an emitter layer located inside the polysilicon film and containing N-type impurities; a lower passivation film located behind the emitter layer; a lower electrode located on the rear surface of the lower passivation film and penetrating the lower passivation film and making contact with the emitter layer; an upper passivation film located on the front surface of the P-type semiconductor substrate; a front surface full layer located between the upper passivation film and the P-type semiconductor substrate and containing P-type impurities; and an upper electrode located on the front surface of the upper passivation film and penetrating the upper passivation film and contacting the entire surface layer of the front surface. A solar cell including a is provided.

Additionally, according to one embodiment of the present invention, forming a tunnel oxide film on the entire surface of a P-type semiconductor substrate whose front surface is textured; forming a polysilicon film on the backside of the tunnel oxide film formed on the backside of the P-type semiconductor substrate; forming an emitter layer containing N-type impurities on the polysilicon film; removing the tunnel oxide film on the front and side surfaces of the P-type semiconductor substrate; forming an entire surface layer containing P-type impurities on the entire surface of the P-type semiconductor substrate; forming an upper passivation film on the entire front surface layer and forming a lower passivation film on the rear surface of the emitter layer; and forming a metal pattern for forming an electrode on the front surface of the upper passivation film and the rear surface of the lower passivation film, respectively, and then penetrating the upper passivation film by firing to form an upper electrode and a lower passivation film that are in contact with the entire surface layer of the front surface. forming a lower electrode that penetrates and contacts the emitter layer; A solar cell manufacturing method comprising a is provided.

The solar cell according to the present invention places the emitter on the rear side of the semiconductor substrate and forms a surface electric layer on the front side, thereby minimizing the voltage loss of the light receiver due to high concentration doping or the current loss of the light receiver due to low concentration doping, and solar cells. It is possible to improve the open-circuit voltage and current characteristics of the battery and the fill factor (FF).

The following drawings attached for use in explaining embodiments of the present invention are only some of the embodiments of the present invention, and to those skilled in the art (hereinafter referred to as "ordinary skilled in the art"), the invention Other drawings can be obtained based on these drawings without further work being done.
1 schematically shows a solar cell according to an embodiment of the present invention;
2A to 2G schematically show a method of manufacturing a solar cell according to an embodiment of the present invention;
3 to 7 schematically show solar cells according to other embodiments of the present invention.

The detailed description of the present invention described below refers to the accompanying drawings, which show by way of example specific embodiments in which the present invention may be practiced to make clear the objectives, technical solutions and advantages of the present invention. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

Additionally, throughout the description and claims of the present invention, the word 'comprise' and variations thereof are not intended to exclude other technical features, attachments, components or steps. Other objects, advantages and features of the invention will appear to those skilled in the art, partly from this description and partly from practice of the invention. The examples and drawings below are provided by way of example and are not intended to limit the invention.

In addition, in order to clearly express various layers and regions in the drawing, the thickness is enlarged. When a part of a layer, membrane, region, plate, etc. is said to be "on" another part, this includes not only being "directly above" the other part, but also parts in between. Conversely, when a part is said to be “right on top” of another part, it means that there is no other part in between. Also, when a part is said to be formed “wholly” on top of another part, it means not only that it is formed on the entire surface of the other part, but also that some of the edges are not formed.

Moreover, the present invention encompasses all possible combinations of the embodiments shown herein. It should be understood that the various embodiments of the present invention are different from one another but are not necessarily mutually exclusive. For example, specific shapes, structures and characteristics described herein with respect to one embodiment may be implemented in other embodiments without departing from the spirit and scope of the invention. Additionally, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. Accordingly, the detailed description that follows is not intended to be taken in a limiting sense, and the scope of the invention is limited only by the appended claims, together with all equivalents to what those claims assert, if properly described. Similar reference numbers in the drawings refer to identical or similar functions across various aspects.

In addition, hereinafter, the front side may be one side of the semiconductor substrate on which direct light is incident, and the back side may be the opposite side of the semiconductor substrate on which direct light is not incident or on which reflected light rather than direct light may be incident.

Hereinafter, in order to enable those skilled in the art to easily practice the present invention, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

Figure 1 schematically shows a solar cell according to an embodiment of the present invention. The solar cell includes a P-type semiconductor substrate 10, a tunnel oxide film 11, a polysilicon film 20, an emitter layer 21, It may include a lower passivation film 50, a lower electrode 62, an upper passivation film 40, a front surface full-layer 30, and an upper electrode 61.

The P-type semiconductor substrate 10 may be a crystalline silicon substrate containing P-type impurities such as boron, gallium, indium, etc. For example, the P-type semiconductor substrate 10 may be a mono-silicon substrate or a poly-silicon substrate doped with P-type impurities.

At this time, the front surface of the P-type semiconductor substrate 10 may have a textured surface, through which the reflectivity of sunlight incident on the front surface can be minimized.

Additionally, the tunnel oxide film 11 may be located on the rear side of the P-type semiconductor substrate 10 and may allow carriers generated in the P-type semiconductor substrate 10 to pass through. At this time, the tunnel oxide film 11 may have a thickness of 1 nm to 2 nm.

In addition, the polysilicon film 20 may be located on the rear side of the tunnel oxide film 11, and the emitter layer 21 may be located inside the polysilicon film 20, and N such as phosphorus, arsenic, antimony, etc. It may contain type impurities. Through this, the P-type semiconductor substrate 10 and the emitter layer 21 form a P-N junction with the tunnel oxide film 11 interposed therebetween.

At this time, the polysilicon film 20 may have a thickness of 100 nm to 200 nm, and the emitter layer 21 may have a thickness of 10 ohm/sq. corresponding to the N-type impurities contained therein. It may have a sheet resistance of 20 ohm/sq. Additionally, the emitter layer 21 may contain a high concentration of N-type impurities.

In addition, the lower passivation film 50 may be located on the back of the emitter layer 21, and the lower electrode 62 may be located on the back of the lower passivation film 50, and penetrate the lower passivation film 50 to emit an emitter. It may be in contact with the base layer 21.

At this time, the lower passivation film 50 may have a single film structure including at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film, or a stacked structure including two or more films. For example, the lower passivation film 50 may be a stacked structure of a silicon nitride film 51 located on the back of the emitter layer 21 and an aluminum oxide film 52 located on the back of the silicon nitride film 51.

Additionally, the lower electrode 62 is used to transport carriers collected from the emitter layer 21, for example electrons, and may be a conductive metal containing silver or a mixture of silver and aluminum. Additionally, the lower electrode 62 may include at least one finger electrode, and may include at least one bus bar connected to at least one finger electrode.

Additionally, the upper passivation film 40 may be located on the front surface of the P-type semiconductor substrate 10 .

At this time, the upper passivation film 40 may have a single film structure including at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film, or a stacked structure including two or more films. As an example, the upper passivation film 40 may be a stacked structure of an aluminum oxide film 41 located on the front surface of the P-type semiconductor substrate 10 and a silicon nitride film 42 located on the front surface of the aluminum oxide film 41.

In addition, the front surface electric layer 30 may be located between the upper passivation film 40 and the P-type semiconductor substrate 10. In this case, the front surface electric layer 30 may contain P-type impurities, 20 ohm/sq. It may have a sheet resistance of from 30 ohm/sq. As an example, the front surface electric layer 30 includes a high concentration P-type impurity layer, and is located at a position corresponding to the upper electrode, that is, below the area where the upper electrode will be located. It can only be located in the lower front area. That is, the front surface full layer 30 may be selectively formed in the inner region of the front lower part of the P-type semiconductor substrate 10. Additionally, the front surface full layer 30 may have a line shape or a dot shape corresponding to the upper electrode to be formed. Therefore, impurity doping at the front of the solar cell can be minimized, thereby increasing the open-circuit voltage of the solar cell, and the charging rate can be increased by reducing contact resistance, thereby improving the efficiency of the solar cell.

In addition, the upper electrode 61 is located on the front surface of the upper passivation film 40, and may penetrate the upper passivation film 40 and contact the front surface electric field layer 30.

At this time, the upper electrode 61 is used to transport carriers collected from the front surface electric field layer 30, for example, holes, and may be a conductive metal containing silver or a mixture of silver and aluminum. Additionally, the upper electrode 61 may include at least one finger electrode, and may include at least one bus bar connected to at least one finger electrode.

Accordingly, the solar cell according to an embodiment of the present invention in FIG. 1 can obtain a high open-circuit voltage by placing an emitter layer of a tunnel structure on the back side, and a front surface electric field layer is formed on the front side, where the upper electrode is formed. By forming a selective front surface full-layer by injecting high-concentration impurities only in selective areas, the semiconductor substrate itself is located in the front light-receiving area, thereby eliminating loss in the light-receiving area due to impurity doping, thereby increasing the current value of the solar cell. there is.

A method of manufacturing a solar cell according to an embodiment of the present invention having such a structure will be described with reference to FIGS. 2A to 2G as follows.

First, referring to FIG. 2A, surface defects of the P-type semiconductor substrate 10 are removed through etching, and then the entire surface is textured.

Then, after cleaning the P-type semiconductor substrate 10, a tunnel oxide film 11 is formed on the entire surface of the P-type semiconductor substrate 10, that is, the entire surface. At this time, the tunnel oxide film 11 is formed by oxidizing the P-type semiconductor substrate 10, and is formed on the surface of the P-type semiconductor substrate 10 by high-temperature heat treatment of the P-type semiconductor substrate 10 in a gas atmosphere containing oxygen. The tunnel oxide film 11 can be formed. Additionally, the tunnel oxide film 11 may be formed to have a thickness of 1 nm to 2 nm. Alternatively, the tunnel oxide film may be deposited on the entire surface of the semiconductor substrate by CVD (chemical vapor deposition).

Next, referring to FIG. 2b, a polysilicon film 20 is deposited on the rear surface of the P-type semiconductor substrate 10, that is, on the rear surface of the tunnel oxide film 11 located on the rear surface of the P-type semiconductor substrate 10. .

At this time, the polysilicon film 20 may be deposited to a thickness of 100 nm to 200 nm at a temperature of 550°C to 650°C. Additionally, the polysilicon film 20 may be deposited by low pressure chemical vapor deposition (LPCVD), or may be formed through crystallization after forming an amorphous silicon film by plasma enhanced chemical vapor deposition (PECVD).

Next, referring to FIG. 2C, the polysilicon film 20 is doped with an N-type impurity to form an emitter layer.

As an example, N-type impurities are diffused into the polysilicon film 20 through the POCl3 process. At this time, the N-type impurities diffuse into the area of the P-type semiconductor substrate 10 where the polysilicon film 20 is not formed, but the tunnel oxide film 11 acts as a diffusion barrier so that the N-type impurities do not spread to the P-type semiconductor substrate ( 10) It can be prevented from spreading.

As another example, in the deposition process of the polysilicon film 20, N-type impurities may be doped using an in-situ process, or only the polysilicon film 20 may be doped with N-type impurities using an ion implantation process. Additionally, a thin film or paste containing N-type impurities may be formed on the rear surface of the polysilicon film 20 and then heat treated to allow the N-type impurities to diffuse into the polysilicon film 20.

Next, referring to FIG. 2D, the emitter layer 21 is formed by etching the entire surface of the P-type semiconductor substrate 10 to remove the exposed tunnel oxide film. At this time, the emitter layer 21 is 10 ohm/sq. The polysilicon 20 may be doped with N-type impurities to have a sheet resistance of 20 ohm/sq.

Next, referring to FIG. 2E, a front surface electric field layer is formed on the front surface of the P-type semiconductor substrate 10. For example, a local area on the front surface of the P-type semiconductor substrate 10 is doped with P-type impurities to form a front surface layer. A surface electric field layer 30 is formed. At this time, the front surface electric field layer 30 may be formed by doping P-type impurities at a high concentration. That is, a high-concentration P-type impurity layer can be formed only in the lower front area of the P-type semiconductor substrate, which corresponds to the lower area of the upper electrode, which is the area where the upper electrode is to be formed. At this time, the front surface overall layer 30 is 20 ohm/sq. It can be formed to have a sheet resistance of 30 ohm/sq., and doping with P-type impurities can be performed by laser doping, ion implantation, paste, etc.

For example, after forming a hydrogenated amorphous silicon film doped with BSG, BPSG or P-type impurities on the entire front area of the P-type semiconductor substrate 10 or forming a paste doped with P-type impurities, high-concentration P is applied by a laser. It is possible to allow type impurities to diffuse only to a local area from the local front surface of the P-type semiconductor substrate 10. In other words, as the laser moves, high concentration P-type impurities can be diffused only in the local area where the laser is applied. At this time, the front surface electric field layer 30 formed in response to the movement of the laser may be formed in a line shape or a dot shape. That is, the entire surface layer has a line shape by continuously moving the laser in a straight line corresponding to the line shape, or the entire surface layer has a dot shape by irradiating the laser at regular intervals when moving the laser in a straight line. You can do it.

As another example, a hydrogenated amorphous silicon film doped with BSG, BPSG, or P-type impurities is formed only in a local area on the front surface of the P-type semiconductor substrate 10, or a paste doped with a high concentration of P-type impurities is formed, and then laser treatment is performed. Through heat treatment, high concentration P-type impurities may be diffused from a local area on the front surface of the P-type semiconductor substrate 10 to an internal area. At this time, a thin film or paste doped with P-type impurities may be formed on the entire surface of the P-type semiconductor substrate 10 in a straight line or dot shape, so that the front surface electric field layer formed is in a line shape or dot shape.

In addition, a high concentration of P-type impurities may be doped only into a local area on the front surface of the P-type semiconductor substrate 10 through the ion implantation process.

Next, referring to FIG. 2F, an upper passivation film 40 and a lower passivation film 50 are formed on the front and back surfaces of the P-type semiconductor substrate 10, respectively.

At this time, the upper passivation film 40 and the lower passivation film 50 may each have a single film structure including at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film, or a stacked structure including two or more films. .

As an example, the upper passivation film 40 can be formed as a stacked structure of an aluminum oxide film 41 located on the front surface of the P-type semiconductor substrate 10 and a silicon nitride film 42 located on the front surface of the aluminum oxide film 41. The lower passivation film 50 may be formed of a silicon nitride film 51 located on the back of the emitter layer 21 and an aluminum oxide film or silicon oxide film located on the back of the silicon nitride film 51. At this time, the silicon nitride film can be formed to have a thickness of 75 nm to 85 nm, and the aluminum oxide film can be formed to have a thickness of 5 nm to 10 nm.

Next, referring to FIG. 2g, after forming metal patterns for forming electrodes on the front and back of the P-type semiconductor substrate 10, respectively, the upper passivation film 40 is penetrated by firing to form an entire surface layer. An upper electrode 61 in contact with 30 and a lower electrode 62 in contact with the emitter layer 21 can be formed through the lower passivation film 50 . At this time, the metal for forming the electrode is a conductive metal and may include silver or a mixture of silver and aluminum, and may be formed through screen printing. In addition, the upper electrode 61 and the lower electrode 62 can each be formed to include at least one finger electrode. At this time, at least one bus bar connected to at least one finger electrode may be formed.

Figure 3 schematically shows a solar cell according to another embodiment of the present invention.

Referring to FIG. 3, the solar cell includes a P-type semiconductor substrate 10, a tunnel oxide film 11, a polysilicon film 20, an emitter layer 21, a lower passivation film 50, a lower electrode 62, and an upper It may include a passivation film 40, a front surface full-layer 30, and an upper electrode 61.

In FIG. 3, the description of the same components as the solar cell described with reference to FIG. 1 will be omitted, and the description will focus on other components.

Unlike the embodiment of FIG. 1 in which the emitter layer is formed over the entire polysilicon film, in the embodiment of FIG. 3 the emitter layer 21 is formed locally on the polysilicon film 20.

That is, in the solar cell in FIG. 3, the emitter layer 21 is located only in the inner region of the polysilicon film 20 corresponding to the upper region of the lower electrode 62. That is, the N-type impurity is doped only into the inner region of the polysilicon film 20 corresponding to the upper region of the lower electrode 62. At this time, the N-type impurity may be doped at a high concentration, and the emitter layer 21 may be doped at a high concentration of 10 ohm/sq. It can have a sheet resistance of from 20 ohm/sq.

In order to form the emitter layer 21 only in the local area of the polysilicon film 20, N-type impurities are doped only in the local area of the polysilicon film 20 by an ion implantation process, or the polysilicon film ( After forming a thin film or paste containing N-type impurities only in the local area of 20), the N-type impurity can be doped only into the local area of the polysilicon film 20 by laser treatment or heat treatment.

In addition, after forming a thin film or paste containing N-type impurities on the entire back surface of the polysilicon film 20, only a local area can be laser treated so that only the laser-treated local area is doped with N-type impurities.

Accordingly, the solar cell according to an embodiment of the present invention shown in FIG. 3 places an emitter layer in a tunnel structure on the rear surface, but forms the emitter layer by high-concentration impurity doping only in a selective area where the lower electrode is formed, thereby forming an emitter layer on the rear surface. A high open-circuit voltage can be obtained by increasing the passivation characteristics of the front surface, and a front surface electric layer is formed on the front surface by injecting a high concentration of impurities only in the selective area where the upper electrode is formed. Since the semiconductor substrate itself is located in the region, loss of light receiving part due to impurity doping can be eliminated, thereby increasing the current value of the solar cell.

Figure 4 schematically shows a solar cell according to another embodiment of the present invention.

Referring to FIG. 4, the solar cell includes a P-type semiconductor substrate 10, a tunnel oxide film 11, a polysilicon film 20, an emitter layer 21, a lower passivation film 50, a lower electrode 62, and an upper It may include a passivation film 40, a front surface full-layer 30, and an upper electrode 61.

In FIG. 4, the description of the same components as the solar cell described with reference to FIG. 1 will be omitted, and the description will focus on other components.

In the embodiment of FIG. 1, the emitter layer is formed on the entire polysilicon film, but in the embodiment of FIG. 4, the emitter layer 21 is formed on the polysilicon film 20, but is formed on the entire area of the polysilicon film 20. A low-concentration N-type impurity region 22 is formed, and an emitter layer 21, which is an N-type impurity region, is formed in a selective region. At this time, N-type impurities for forming the emitter layer 21 may be doped at a high concentration.

That is, the solar cell in FIG. 4 has a low-concentration N-type impurity layer 22 located entirely inside the polysilicon film and a high-concentration N-type impurity layer located only inside a selective region of the polysilicon film corresponding to the upper region of the lower electrode. This is to form the emitter layer 21.

At this time, the low concentration N-type impurity layer 22 is 120 ohm/sq. It has a sheet resistance of 150 ohm/sq., and the N-type impurity layer 21 has a sheet resistance of 10 ohm/sq. It can be formed to have a sheet resistance of from 20 ohm/sq.

In order to form a low-concentration region and a selective high-concentration region of the N-type impurity in the polysilicon film 20, low-concentration N-type impurity is doped through the entire surface of the polysilicon film 20 to form a low-concentration N-type impurity layer 22. forms. Additionally, only a local region of the polysilicon film doped with a low concentration of N-type impurities corresponding to the lower electrode may be doped with the N-type impurity, for example, doped with a high concentration.

At this time, in order to form a high-concentration N-type impurity region, only local areas of the polysilicon film 20 are doped with high-concentration N-type impurities through an ion implantation process, or high-concentration N-type impurities are doped only in local areas of the polysilicon film 20. After forming the thin film or paste containing this, high concentration N-type impurities can be doped only into local areas of the polysilicon film 20 by laser treatment or heat treatment.

In addition, after forming a thin film or paste containing N-type impurities on the entire back surface of the polysilicon film 20, only a local area can be laser treated so that only the laser-treated local area is doped with N-type impurities.

Accordingly, in the solar cell according to an embodiment of the present invention shown in FIG. 4, an emitter layer with a tunnel structure is positioned on the rear portion, but only a selective region where the lower electrode is formed is doped with a high concentration of impurities, and other regions are doped with a low concentration of impurities. By doping this, not only can a high open-circuit voltage be obtained, but the filling rate of the solar cell can be improved by improving the contact characteristics with the lower metal electrode, and a front surface electric field layer is formed on the front part, but at the position where the upper electrode is formed. By forming a selective front surface full-layer by injecting high-concentration impurities only in selective areas, the semiconductor substrate itself is located in the front light-receiving area, thereby eliminating loss in the light-receiving area due to impurity doping, thereby increasing the current value of the solar cell.

Figure 5 schematically shows a solar cell according to another embodiment of the present invention.

Referring to FIG. 5, the solar cell includes a P-type semiconductor substrate 10, a tunnel oxide film 11, a polysilicon film 20, an emitter layer 21, a lower passivation film 50, a lower electrode 62, and an upper It may include a passivation film 40, a front surface full-layer 30, and an upper electrode 61.

In FIG. 5 , the description of the same components as the solar cell described with reference to FIG. 1 will be omitted, and the description will focus on other components.

In the embodiment of FIG. 1, the front surface electric field layer is formed locally on the front surface of the P-type semiconductor substrate, but in the embodiment of FIG. 5, the front surface electric field layer 31 is formed on the entire upper surface of the P-type semiconductor substrate 10. will be.

That is, the solar cell in FIG. 5 has an epitaxial layer doped with P-type impurities located on the entire front surface of the P-type semiconductor substrate 10 to form the front surface electric field layer 31. At this time, the epitaxial layer containing P-type impurities can be formed by a CVD process. Additionally, the epitaxial layer containing P-type impurities may have a thickness of 10 nm to 100 nm, and 10 ohm/sq. It can have a sheet resistance of from 20 ohm/sq.

In addition, by forming the front surface electric layer 31 using an epitaxial layer containing high concentration of P-type impurities on the upper surface of the P-type semiconductor substrate 10, the open-circuit voltage, current value, and filling factor of the solar cell can be improved.

Therefore, the solar cell according to an embodiment of the present invention shown in FIG. 5 can obtain a high open-circuit voltage by placing an emitter layer in a tunnel structure on the back side, and forms a front surface electric field layer on the front side, but the entire front surface of the semiconductor substrate. By forming a P-type epitaxial layer, which is the same material as the semiconductor substrate, to form an entire surface layer, not only can the heterogeneity with the semiconductor substrate be reduced, but it can also reduce the loss of the light receiver and reduce the recombination rate within the semiconductor substrate, thereby improving the solar cell The open circuit voltage value can be increased.

Figure 6 schematically shows a solar cell according to another embodiment of the present invention.

Referring to FIG. 6, the solar cell includes a P-type semiconductor substrate 10, a tunnel oxide film 11, a polysilicon film 20, an emitter layer 21, a lower passivation film 50, a lower electrode 62, and an upper It may include a passivation film 40, a front surface full-layer 30, and an upper electrode 61.

6 shows that, as in FIG. 3, the emitter layer 21 is formed only in a local area of the polysilicon film 10, and as in FIG. 5, the front surface electric layer 31 is formed on the front surface of the P-type semiconductor substrate 10. It is formed with a P-type impurity epitaxial layer, which can be understood from the description of FIGS. 3 and 5, so detailed description is omitted.

Therefore, the solar cell according to an embodiment of the present invention shown in FIG. 6 places an emitter layer in a tunnel structure on the back side, but forms the emitter layer by high-concentration impurity doping only in a selective area where the lower electrode is formed, thereby forming an emitter layer on the back side. A high open-circuit voltage can be obtained by increasing the passivation characteristics, and a front surface electric field layer is formed on the front part, but a P-type epitaxial layer made of the same material as the semiconductor substrate is formed on the entire front surface of the semiconductor substrate to form a front surface electric field layer. Not only can it reduce heterogeneity with the semiconductor substrate, it can also reduce the loss of the light receiver and reduce the recombination rate within the semiconductor substrate, thereby increasing the open-circuit voltage value of the solar cell.

Figure 7 schematically shows a solar cell according to another embodiment of the present invention.

Referring to FIG. 7, the solar cell includes a P-type semiconductor substrate 10, a tunnel oxide film 11, a polysilicon film 20, an emitter layer 21, a lower passivation film 50, a lower electrode 62, and an upper It may include a passivation film 40, a front surface full-layer 30, and an upper electrode 61.

7 shows that the emitter layer 21 is formed by high-concentration N-type impurities only in a local area of the polysilicon film 10 in which the entire area is doped with low-concentration N-type impurities, as shown in FIG. 4, and the front surface as in FIG. 5. The electric layer 31 is formed of a P-type impurity epitaxial layer located on the front surface of the P-type semiconductor substrate 10, and can be understood from the description of FIGS. 4 and 5, so detailed description will be omitted.

Therefore, in the solar cell according to an embodiment of the present invention shown in FIG. 7, an emitter layer with a tunnel structure is positioned on the rear portion, but only a selective region where the lower electrode is formed is doped with a high concentration of impurities, and other regions are doped with a low concentration of impurities. By doping this, not only can a high open-circuit voltage be obtained, but the filling rate of the solar cell can be improved by improving the contact characteristics with the lower metal electrode. A front surface electric field layer is formed on the front surface, and a semiconductor layer is formed on the entire front surface of the semiconductor substrate. By forming a P-type epitaxial layer, which is the same material as the substrate, to form an entire surface layer, not only can the heterogeneity with the semiconductor substrate be reduced, but it can also reduce the loss of the light receiver and reduce the recombination rate within the semiconductor substrate, thereby reducing the open-circuit voltage of the solar cell. The value can rise.

In the above, the present invention has been described with specific details such as specific components and limited embodiments and drawings, but this is only provided to facilitate a more general understanding of the present invention, and the present invention is not limited to the above embodiments. , a person skilled in the art to which the present invention pertains can make various modifications and variations from this description.

Therefore, the spirit of the present invention should not be limited to the above-described embodiments, and the scope of the patent claims described below as well as all modifications equivalent to or equivalent to the scope of the claims fall within the scope of the spirit of the present invention. They will say they do it.

10: P-type semiconductor substrate, 11: tunnel oxide film,
20: polysilicon film, 21: emitter layer,
22: low concentration N-type impurity layer, 30, 31: front surface full layer,
40: upper passivation film, 50: lower passivation film,
61: upper electrode, 62: lower electrode

Claims (20)

P-type semiconductor substrate with textured front surface;
a tunnel oxide film located on the rear side of the P-type semiconductor substrate;
a polysilicon layer located behind the tunnel oxide layer;
an emitter layer located inside the polysilicon film and containing N-type impurities;
a lower passivation film located behind the emitter layer;
a lower electrode located on the rear surface of the lower passivation film and penetrating the lower passivation film and making contact with the emitter layer;
an upper passivation film located on the front surface of the P-type semiconductor substrate;
a front surface full layer located between the upper passivation film and the P-type semiconductor substrate and containing P-type impurities; and
an upper electrode located on the front surface of the upper passivation film and penetrating the upper passivation film and making contact with the front surface layer;
Including,
The emitter layer is located only in the inner region of the polysilicon film corresponding to the upper region of the lower electrode,
The front surface entire layer includes a highly concentrated P-type impurity layer located only in a lower region of the upper surface of the P-type semiconductor substrate corresponding to a lower region of the upper electrode,
The emitter layer is 10 ohm/sq. It has a sheet resistance of 20 ohm/sq., and the total layer of the front surface is 20 ohm/sq. A solar cell characterized in that it has a sheet resistance of 30 ohm/sq. delete delete According to paragraph 1,
a low-concentration N-type impurity layer located entirely inside the polysilicon film;
A solar cell further comprising: According to paragraph 4,
The low concentration N-type impurity layer is 120 ohm/sq. It has a sheet resistance of 150 ohm/sq., and the N-type impurity layer has a sheet resistance of 10 ohm/sq. A solar cell characterized by having a sheet resistance of 20 ohm/sq. delete delete According to paragraph 1,
A solar cell, characterized in that the front surface electric layer has a line or dot shape corresponding to the upper electrode. delete Forming a tunnel oxide film on the entire surface of a P-type semiconductor substrate whose front surface is textured;
forming a polysilicon film on the backside of the tunnel oxide film formed on the backside of the P-type semiconductor substrate;
forming an emitter layer containing N-type impurities on the polysilicon film;
removing the tunnel oxide film on the front and side surfaces of the P-type semiconductor substrate;
forming an entire surface layer containing P-type impurities on the entire surface of the P-type semiconductor substrate;
forming an upper passivation film on the entire front surface layer and forming a lower passivation film on the rear surface of the emitter layer; and
After forming a metal pattern for forming an electrode on the front surface of the upper passivation film and the rear surface of the lower passivation film, respectively, the upper passivation film is penetrated by firing, and the upper electrode and the lower passivation film are in contact with the entire surface layer of the front surface. forming a lower electrode in contact with the emitter layer;
Including,
The step of forming the emitter layer is,
After forming a paste containing N-type impurities on the rear surface of the polysilicon film, the N-type impurities contained in the paste are diffused into the polysilicon film and doped with N-type impurities into the polysilicon film,
The step of forming the emitter layer is,
Formed by doping N-type impurities in a local region of the polysilicon film corresponding to the lower electrode,
The step of forming the front surface full layer is,
Doping P-type impurities at a high concentration in a local area on the front surface of the P-type semiconductor substrate corresponding to the upper electrode,
The emitter layer is 10 ohm/sq. Formed to have a sheet resistance of 20 ohm/sq.,
The front surface total layer is 20 ohm/sq. A method of manufacturing a solar cell, characterized in that it is formed to have a sheet resistance of 30 ohm/sq. delete delete delete According to clause 10,
The step of forming the emitter layer is,
After doping the entire region of the polysilicon film with the N-type impurity at a low concentration, doping the N-type impurity into a local region of the polysilicon film doped with the N-type impurity at a low concentration corresponding to the lower electrode. Solar cell manufacturing method. According to clause 14,
The area of the polysilicon film doped with the N-type impurity at a low concentration is 120 ohm/sq. to have a sheet resistance of 150 ohm/sq., and the area of the polysilicon film doped with the N-type impurity is 10 ohm/sq. A method of manufacturing a solar cell, characterized in that it has a sheet resistance of 20 ohm/sq. delete delete According to clause 10,
The step of forming the front surface full layer is,
A solar cell manufacturing method comprising forming a hydrogenated amorphous silicon film doped with BSG, BPSG or P-type impurities on the entire surface of the P-type semiconductor substrate, and then performing doping by laser irradiation or heat treatment. According to clause 10,
The step of forming the front surface full layer is,
A solar cell manufacturing method comprising forming a paste doped with P-type impurities on the entire surface of the P-type semiconductor substrate and then performing doping by laser irradiation or heat treatment. delete

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