KR102635184B1 - Semiconductor package - Google Patents

Abstract

The present disclosure includes a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposite to the first surface; a first heat dissipation member disposed on a second side of the semiconductor chip; a second heat dissipation member disposed on the second surface of the semiconductor chip and covering at least a portion of a side surface of the first heat dissipation member; An encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the first surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pad. It relates to a semiconductor package including.

Description

Semiconductor package {SEMICONDUCTOR PACKAGE}

This disclosure relates to semiconductor packages.

In the case of a high-level package, for example, a semiconductor package including an application processor (AP), the lifespan of the package may be shortened due to deterioration due to high heat generated from the AP chip.

One of the several purposes of the present disclosure is to provide a semiconductor package that can effectively improve heat dissipation effect.

One of several solutions proposed through this disclosure is to arrange a plurality of heat dissipation members on the back surface of the semiconductor chip to effectively dissipate heat.

For example, a semiconductor package according to one example includes a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposite to the first surface; a first heat dissipation member disposed on a second side of the semiconductor chip; a second heat dissipation member disposed on the second surface of the semiconductor chip and covering at least a portion of a side surface of the first heat dissipation member; An encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the first surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pad. It may include.

As one of the many effects of the present disclosure, a semiconductor package that can effectively improve heat dissipation effect can be provided.

1 is a block diagram schematically showing an example of an electronic device system.
Figure 2 is a perspective view schematically showing an example of an electronic device.
3A and 3B are cross-sectional views schematically showing before and after packaging a fan-in semiconductor package.
Figure 4 is a cross-sectional view schematically showing the packaging process of a fan-in semiconductor package.
Figure 5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device.
Figure 6 is a cross-sectional view schematically showing the case where the fan-in semiconductor package is embedded in a printed circuit board and finally mounted on the main board of an electronic device.
Figure 7 is a cross-sectional view schematically showing a fan-out semiconductor package.
Figure 8 is a cross-sectional view schematically showing a case where a fan-out semiconductor package is mounted on the main board of an electronic device.
Figure 9 is a cross-sectional view schematically showing an example of a semiconductor package.
FIG. 10 is a plan view showing a schematic top view of the semiconductor package of FIG. 9.
FIGS. 11A and 11B are process diagrams schematically showing an example of manufacturing the semiconductor package of FIG. 9.
Figure 12 is a cross-sectional view schematically showing another example of a semiconductor package.
Figure 13 is a cross-sectional view schematically showing another example of a semiconductor package.

Hereinafter, the present disclosure will be described with reference to the attached drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clearer explanation.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawing, the electronic device 1000 accommodates the main board 1010. The motherboard 1010 is physically and/or electrically connected to chip set-related components 1020, network-related components 1030, and other components 1040. These are combined with other components described later to form various signal lines 1090.

Chip set-related components 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as central processors (eg, CPU), graphics processors (eg, GPU), digital signal processors, cryptographic processors, microprocessors, and microcontrollers; Logic chips such as analog-digital converters and ASICs (application-specific ICs) are included, but are not limited to these, and of course other types of chip-related components may also be included. Additionally, of course, these components 1020 can be combined with each other.

Network-related parts (1030) include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM. , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated as such, but are not limited to, and many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, of course, the network-related components 1030 can be combined with the chip set-related components 1020.

Other parts (1040) include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (Electro Magnetic Interference) filter, MLCC (Multi-Layer Ceramic Condenser), etc. , but is not limited to this, and may include passive parts used for various other purposes. In addition, of course, the other components 1040 can be combined with the chip set-related components 1020 and/or the network-related components 1030.

Depending on the type of electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and/or electrically connected to the main board 1010. Examples of other components include a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), and a compass ( (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage device (e.g., hard disk drive) (not shown), compact disk (CD) (not shown), and DVD (digital versatile disk) (not shown), etc. However, it is not limited thereto, and of course, other parts used for various purposes may be included depending on the type of electronic device 1000.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( It may be a computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited to this, and of course, it can be any other electronic device that processes data.

Figure 2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, semiconductor packages are applied to various electronic devices as described above for various purposes. For example, a printed circuit board 1110 such as a motherboard is accommodated inside the body 1101 of the smart phone 1100, and various components 1120 are physically and/or electrically installed on the printed circuit board 1110. It is connected to. Additionally, other components, such as the camera 1130, which may or may not be physically and/or electrically connected to the printed circuit board 1110, are accommodated within the body 1101. Some of the components 1120 may be chip set-related components, for example, the semiconductor package 1121, but are not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, and of course, it may be other electronic devices as described above.

semiconductor package

In general, a semiconductor chip integrates numerous microscopic electrical circuits, but it cannot function as a finished semiconductor product by itself, and there is a possibility that it may be damaged by external physical or chemical shock. Therefore, rather than using the semiconductor chip itself, the semiconductor chip is packaged and used in electronic devices as a package.

The reason why semiconductor packaging is necessary is because, from the perspective of electrical connection, there is a difference in circuit width between the semiconductor chip and the main board of electronic devices. Specifically, in the case of semiconductor chips, the size of the connection pads and the spacing between the connection pads are very small, whereas in the case of motherboards used in electronic devices, the size of the component mounting pads and the spacing between the component mounting pads are much larger than the scale of the semiconductor chip. . Therefore, it is difficult to directly mount a semiconductor chip on such a motherboard, and packaging technology that can buffer the difference in circuit width between them is required.

Semiconductor packages manufactured using this packaging technology can be divided into fan-in semiconductor packages and fan-out semiconductor packages depending on their structure and use.

Below, we will look at the fan-in semiconductor package and fan-out semiconductor package in more detail with reference to the drawings.

(Fan-in semiconductor package)

3A and 3B are cross-sectional views schematically showing before and after packaging a fan-in semiconductor package.

Figure 4 is a cross-sectional view schematically showing the packaging process of a fan-in semiconductor package.

Referring to the drawing, the semiconductor chip 2220 includes a body 2221 containing silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc., and aluminum (Al) formed on one surface of the body 2221. A connection pad 2222 containing a metal material, and a passivation film 2223 such as an oxide or nitride film formed on one surface of the body 2221 and covering at least a portion of the connection pad 2222, for example, It may be an integrated circuit (IC) in a bare state. At this time, because the connection pad 2222 is very small, it is difficult for an integrated circuit (IC) to be mounted on a mid-level printed circuit board (PCB) as well as a main board of an electronic device.

Accordingly, in order to rewire the connection pad 2222, a connection structure 2240 is formed on the semiconductor chip 2220 according to the size of the semiconductor chip 2220. The connection structure 2240 forms an insulating layer 2241 with an insulating material such as photosensitive insulating resin (PID: Photo Image-able Dielectric) on the semiconductor chip 2220, and forms a via hole 2243h that opens the connection pad 2222. ) can be formed by forming the wiring pattern 2242 and the via 2243. After that, a passivation layer 2250 is formed to protect the connection structure 2240, an opening 2251 is formed, and then an underbump metal 2260 and the like are formed. That is, through a series of processes, for example, a fan-in semiconductor package 2200 including a semiconductor chip 2220, a connection structure 2240, a passivation layer 2250, and an underbump metal 2260 is manufactured. do.

As such, the fan-in semiconductor package is a package type in which the connection pads of the semiconductor chip, such as I/O (Input/Output) terminals, are all placed inside the device. The fan-in semiconductor package has good electrical characteristics and can be produced inexpensively. there is. Accordingly, many devices used in smartphones are manufactured in the form of fan-in semiconductor packages, and specifically, development is being carried out to realize small size and fast signal transmission.

However, fan-in semiconductor packages have many space limitations as all I/O terminals must be placed inside the semiconductor chip. Therefore, it is difficult to apply this structure to semiconductor chips with a large number of I/O terminals or to semiconductor chips of small size. Additionally, due to this vulnerability, the fan-in semiconductor package cannot be directly mounted and used on the main board of an electronic device. Even if the size and spacing of the I/O terminals of a semiconductor chip are expanded through a rewiring process, the size and spacing are not large enough to be directly mounted on the main board of an electronic device.

Figure 5 is a cross-sectional view schematically showing a case where a fan-in semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device.

Figure 6 is a cross-sectional view schematically showing the case where the fan-in semiconductor package is embedded in a printed circuit board and finally mounted on the main board of an electronic device.

Referring to the drawing, in the fan-in semiconductor package 2200, the connection pads 2222 of the semiconductor chip 2220, that is, the I/O terminals, are rewired again through the printed circuit board 2301, and finally, Can be mounted on the main board 2500 of an electronic device with the fan-in semiconductor package 2200 mounted on the printed circuit board 2301. At this time, the solder ball 2270, etc. may be fixed with an underfill resin 2280, etc., and the outside may be covered with a molding material 2290, etc. Alternatively, the fan-in semiconductor package 2200 may be embedded within a separate printed circuit board 2302, and the connection pads of the semiconductor chip 2220 may be connected by the printed circuit board 2302 in an embedded state. (2222), that is, the I/O terminals can be rewired once again and finally mounted on the main board 2500 of the electronic device.

As such, since it is difficult to use the fan-in semiconductor package by directly mounting it on the main board of an electronic device, it is mounted on a separate printed circuit board and then goes through a packaging process and is then mounted on the main board of the electronic device, or as a printed circuit board. It is used by being embedded within a circuit board and mounted on the main board of an electronic device.

(Fan-out semiconductor package)

Figure 7 is a cross-sectional view schematically showing a fan-out semiconductor package.

Referring to the drawing, in the fan-out semiconductor package 2100, for example, the outside of the semiconductor chip 2120 is protected with an encapsulant 2130, and the connection pad 2122 of the semiconductor chip 2120 is a connection structure. By 2140, the wiring is rewired to the outside of the semiconductor chip 2120. At this time, a passivation layer 2150 may be further formed on the connection structure 2140, and an underbump metal 2160 may be further formed in the opening of the passivation layer 2150. A solder ball 2170 may be further formed on the underbump metal 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121 and a connection pad 2122. The connection structure 2140 may include an insulating layer 2141, a wiring layer 2142 formed on the insulating layer 2241, and a via 2143 that electrically connects the connection pad 2122 and the wiring layer 2142. .

In this way, the fan-out semiconductor package is a type in which I/O terminals are rewired and arranged to the outside of the semiconductor chip through a connection structure formed on the semiconductor chip. As described above, the fan-in semiconductor package requires all I/O terminals of the semiconductor chip to be placed inside the semiconductor chip, and as the device size decreases, the ball size and pitch must be reduced, so a standardized ball layout cannot be used. On the other hand, the fan-out semiconductor package is a type in which the I/O terminals are rewired and arranged to the outside of the semiconductor chip through the connection structure formed on the semiconductor chip, so even if the size of the semiconductor chip becomes smaller, a standardized ball layout is maintained. It can be used as is, and as described later, it can be mounted on the main board of an electronic device without a separate printed circuit board.

Figure 8 is a cross-sectional view schematically showing a case where a fan-out semiconductor package is mounted on the main board of an electronic device.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on the main board 2500 of an electronic device through a solder ball 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 is a connection structure that can rewire the connection pad 2122 on the semiconductor chip 2120 to a fan-out area that exceeds the size of the semiconductor chip 2120. Since it forms (2140), a standardized ball layout can be used as is, and as a result, it can be mounted on the main board 2500 of an electronic device without a separate printed circuit board.

In this way, since the fan-out semiconductor package can be mounted on the main board of an electronic device without a separate printed circuit board, it can be implemented with a thinner thickness than the fan-in semiconductor package using a printed circuit board, enabling miniaturization and thinning. do. Additionally, it has excellent thermal and electrical properties, making it particularly suitable for mobile products. In addition, it can be implemented more compactly than the typical POP (Package on Package) type that uses a printed circuit board (PCB), and problems caused by bending can be solved.

Meanwhile, the fan-out semiconductor package refers to a package technology for mounting a semiconductor chip on the motherboard of an electronic device, etc., and for protecting the semiconductor chip from external shock. It is different from this in scale, purpose, etc. It is a different concept from a printed circuit board (PCB), such as a printed circuit board in which a fan-in semiconductor package is built.

Hereinafter, a semiconductor package that can effectively improve heat dissipation effect will be described with reference to the drawings.

Figure 9 is a cross-sectional view schematically showing an example of a semiconductor package.

FIG. 10 is a plan view showing a schematic top view of the semiconductor package of FIG. 9.

Referring to the drawings, a semiconductor package 100A according to an example has a through portion 110H and is disposed on a frame 110 including one or more wiring layers 112a and 112b, the through portion 110H, and a connection pad 120P. A semiconductor chip 120 having a first surface and a second surface opposite to the first surface, a first heat dissipation member 125 disposed on the second surface of the semiconductor chip 120, and a semiconductor chip 120. The second heat dissipation member 127 is disposed on the second surface and covers at least a portion of the side surface of the first heat dissipation member 125, and the encapsulant 130 covers at least a portion of each of the frame 110 and the semiconductor chip 120. ), one or more redistribution layers 142a, 142b disposed on the lower surface of the frame 110 and the first side of the semiconductor chip 120 and electrically connected to one or more wiring layers 112a, 112b and the connection pad 120P. A connection structure 140 including a passivation layer 150 disposed on the lower side of the connection structure 140, an underbump metal 160 disposed on the opening of the passivation layer 150, and an underbump metal 160. It includes an electrical connection metal 170 that is electrically connected to one or more redistribution layers 142a and 142b.

In the semiconductor package 100A according to one example, first and second heat dissipation members 125 and 127 are disposed on the second surface corresponding to the back surface of the semiconductor chip 120. Accordingly, heat generated from the semiconductor chip 120 can be effectively dissipated to the outside through the first and second heat dissipation members 125 and 127 disposed on the second surface, and the heat dissipation effect can be improved. In particular, the second heat dissipation member 127 is arranged in parallel with the first heat dissipation member 125 on the back surface of the semiconductor chip 120 and covers at least a portion of the side surface of the first heat dissipation member 125. Therefore, it is possible to have high thermal conductivity in the plane direction (x-y direction), which is the direction in which the back surface of the semiconductor chip 120 extends, through the first heat dissipation member 125, and also through the second heat dissipation member 127. It can have high thermal conductivity both in the plane direction (x-y direction) and in the perpendicular direction (z direction). As a result, the heat dissipation effect of the semiconductor package 100A according to one example can be maximized.

Meanwhile, the first heat dissipation member 125 may be a solid heat dissipation material. For example, the first heat dissipation member 125 may include graphite. Graphite may be, for example, pyrolytic graphite produced in the form of a sheet after pyrolyzing raw materials such as polyimide at high temperature to carbonize and graphitize, but is not limited thereto. Here, “pyrolytic graphite” refers to materials such as thermal pyrolytic graphite (TPG), highly oriented pyrolytic graphite (HOPG), compression annealed thermal pyrolytic graphite (CAPG), etc. It can be included. The first heat dissipation member 125 may contain 90 wt% or more of pyrolytic graphite. Additionally, the first heat dissipation member 125 contains less than 5 wt% of additives for lowering thermal contact resistance, such as carbide forming additives such as zirconium (Zr), chromium (Cr), and boron (B). may include less than 5 wt% of additives to increase thermal conductivity in the vertical direction (z direction), such as carbon nanotubes (CNTs), boron nitride, and combinations thereof. there is.

Meanwhile, the second heat dissipation member 127 may include conductive particles and binder resin. The conductive particles may be, for example, metal particles such as gold (Au), silver (Ag), platinum (Pt), or aluminum (Al). The metal particles may be nanometal particles, if necessary. The binder resin may be, for example, a known insulating resin such as epoxy resin or phenol resin. As a non-limiting example, the second heat dissipation member 126 may be formed from silver paste (Ag Paste) containing silver particles and epoxy resin.

Meanwhile, at least a portion of the upper surfaces of the first and second heat dissipation members 125 and 127 may be exposed from the encapsulant 130, respectively. For example, the encapsulant 130 covers at least a portion of the side surface of the second heat dissipation member 127, the upper surface of the first heat dissipation member 125, the upper surface of the second heat dissipation member 127, and the encapsulant 130. ) can be coplanar with each other. Here, coplanar means substantially existing on the same plane, and is a concept that includes some errors due to the process. In this case, the heat dissipation effect by the first and second heat dissipation members 125 and 127 may be improved.

Meanwhile, the area of the semiconductor chip 120 on a plane may be larger than the area of the first heat dissipation member 125. That is, when the first heat dissipation member 125 is disposed on the back surface of the semiconductor chip 120, a portion of the back surface of the semiconductor chip 120 may be exposed from the first heat dissipation member 125, and the corresponding area may be exposed to the second heat dissipation member 125. It may be covered with a heat dissipation member 127. By having this area size relationship, as described above, the second heat dissipation member 127 is aligned with the first heat dissipation member 125 on the back surface of the semiconductor chip 120 and is at least on the side of the first heat dissipation member 125. It can be placed to cover part of the area.

Meanwhile, a metal layer 115 may be disposed on the wall of the penetrating portion 110H of the frame 110. The metal layer 115 may be formed to continuously surround the side surface of the semiconductor chip 120 and cover the entire wall. Heat generated in the semiconductor chip 120 can be transferred to the frame 110 through the metal layer 115 and then more easily dissipated up and down through the frame 110. The metal layer 115 may also have an electromagnetic wave shielding effect.

Hereinafter, each configuration of the semiconductor package 100A according to an example will be described in more detail with reference to the attached drawings.

The frame 110 may further improve the rigidity of the semiconductor package 100A according to an example depending on the specific material of the insulating layer 111. In addition, it may play a role such as ensuring thickness uniformity of the sealing material 130. The frame 110 has a penetrating portion 110H that penetrates the insulating layer 111. A semiconductor chip 120 is disposed in the penetrating portion 110H, and additional passive components may be disposed as needed. The penetrating portion 110H may have a wall that continuously surrounds the side surface of the semiconductor chip 120, but is not limited to this. If necessary, the frame 110 may be composed of multiple units. If necessary, an electrical connection member capable of providing another type of upper and lower electrical connection path, such as a metal post, may be introduced into the frame 110. If necessary, the frame 110 itself may be omitted.

The frame 110 includes an insulating layer 111, a first wiring layer 112a disposed on the lower surface of the insulating layer 111, a second wiring layer 112b disposed on the upper surface of the insulating layer 111, and an insulating layer ( 111) and may include a wiring via 113 that electrically connects the first and second wiring layers 112a and 112b, and a metal layer 115 disposed on the wall of the penetrating portion 110H.

The material of the insulating layer 111 is not particularly limited. For example, an insulating material may be used, in which case the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler, for example, ABF (Ajinomoto Build-ABF). up Film), etc. may be used. Alternatively, a material in which the core material such as glass fiber (glass fiber, glass cloth, glass fabric) is impregnated with the above-described resin along with an inorganic filler, for example, prepreg, etc. may be used. In this case, the insulating layer 111 may be introduced through a copper clad laminate (CCL).

The first and second wiring layers 112a and 112b, together with the wiring via 113, may provide an upper and lower electrical connection path within the package 100A. Additionally, it may play a role in rewiring the connection pad 120P. The first and second wiring layers 112a and 112b are copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). ), or metal materials such as alloys thereof. The first and second wiring layers 112a and 112b can perform various functions depending on the design of the corresponding layer. For example, it may include a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, etc. Here, the signal (S) pattern includes various signals, for example, data signals, etc., excluding the ground (GND) pattern, power (PWR) pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. Additionally, each may include various types of via pads. The first and second wiring layers 112a and 112b may be formed using a known plating process and may include a seed layer and a plating layer, respectively.

The thickness of each of the first and second wiring layers 112a and 112b may be thicker than the thickness of each of the second redistribution layers 142b. Specifically, the frame 110 may have a thickness equal to or greater than that of the semiconductor chip 120, and to maintain rigidity, the material of the insulating layer 111 is selected from prepreg, etc., and the first and second wiring layers ( The thickness of 112a, 112b) may also be relatively thick. On the other hand, the connection structure 140 requires a fine circuit and high-density design, and therefore the material of the insulating layer 141 is selected as a photosensitive insulating material (PID), and the thickness of the second redistribution layer 142b formed therefrom is selected. may also be relatively thin.

The wiring via 113 electrically connects the first and second wiring layers 112a and 112b formed in different layers, and as a result, forms an electrical path within the frame 110. Materials forming the wiring via 113 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), Alternatively, metal materials such as alloys thereof can be used. The wiring via 113 may include a signal via, a power via, a ground via, etc., and the power via and the ground via may be the same via. The wiring vias 113 may be field-type vias filled with a metal material, or may be conformal-type vias in which a metal material is formed along the wall of the via hole. Additionally, it may have an hourglass shape. The wiring via 113 may be formed through a plating process together with the first and second wiring layers 112a and 112b, and may be composed of a seed layer and a conductor layer.

The metal layer 115 is disposed on the wall of the penetrating portion 110H, and may be extended to the upper and lower surfaces of the insulating layer 111 as needed. Materials forming the metal layer 115 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or Metal materials such as alloys thereof can be used. The metal layer 115 may be electrically connected to the ground patterns of the first and second wiring layers 112a and 112b and/or the ground patterns of the first and second redistribution layers 142a and 142b. That is, the metal layer 115 can be used as a ground pattern. The metal layer 115 may also be formed through a plating process. Therefore, it may be composed of a seed layer and a conductor layer.

The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of elements are integrated into one chip. At this time, the integrated circuit constituting the semiconductor chip 120 may be, for example, an application processor chip including a central processor, a graphics processor, a digital signal processor, an encryption processor, a microprocessor, and/or a microcontroller, etc. It is not limited. The semiconductor chip 120 may be a bare integrated circuit in which no separate bumps or wiring layers are formed. However, it is not limited to this, and if necessary, it may be a packaged type integrated circuit in which an insulating layer and a redistribution layer are formed on the active surface.

Integrated circuits can be formed based on active wafers. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material forming the body of the semiconductor chip 120. Various circuits may be formed in the body. The connection pad 120P is used to electrically connect the semiconductor chip 120 to other components, and metal materials such as copper (Cu) and aluminum (Al) can be used as forming materials without particular restrictions. A passivation film that opens the connection pad 120P may be formed on the body. The passivation film may be an oxide film, a nitride film, or a double layer of an oxide film and a nitride film. Additional insulating films, etc. may be disposed at other necessary positions. Meanwhile, the side of the semiconductor chip 120 where the connection pad 120P is placed becomes the active side, and the back side opposite to it becomes the inactive side. However, in some cases, a connection pad is placed on the back side, so both sides may be active sides.

The first heat dissipation member 125 may be a solid heat dissipation material. For example, the first heat dissipation member 125 may include graphite. Graphite may be, for example, pyrolytic graphite produced in the form of a sheet after pyrolyzing raw materials such as polyimide at high temperature to carbonize and graphitize, but is not limited thereto. Here, “pyrolytic graphite” refers to materials such as thermal pyrolytic graphite (TPG), highly oriented pyrolytic graphite (HOPG), compression annealed thermal pyrolytic graphite (CAPG), etc. It can be included. The first heat dissipation member 125 may contain 90 wt% or more of pyrolytic graphite. Additionally, the first heat dissipation member 125 contains less than 5 wt% of additives for lowering thermal contact resistance, such as carbide forming additives such as zirconium (Zr), chromium (Cr), and boron (B). may include less than 5 wt% of additives to increase thermal conductivity in the vertical direction (z direction), such as carbon nanotubes (CNTs), boron nitride, and combinations thereof. there is.

The second heat dissipation member 127 may include conductive particles and binder resin. The conductive particles may be, for example, metal particles such as gold (Au), silver (Ag), platinum (Pt), or aluminum (Al). The metal particles may be nanometal particles, if necessary. The binder resin may be, for example, a known insulating resin such as epoxy resin or phenol resin. As a non-limiting example, the second heat dissipation member 126 may be formed from silver paste (Ag Paste) containing silver particles and epoxy resin.

The encapsulant 130 covers at least a portion of each of the frame 110 and the semiconductor chip 120, and fills at least a portion of the penetrating portion 110H. The encapsulant 130 includes an insulating material, and the insulating material includes a non-photosensitive insulating material, more specifically, a non-photosensitive insulating material including an inorganic filler and an insulating resin, such as a thermosetting resin such as an epoxy resin, and a polyimide. Thermoplastic resins, or resins containing reinforcing materials such as inorganic fillers, specifically non-photosensitive insulating materials such as ABF or EMC, can be used. If necessary, a material in which an insulating resin such as a thermosetting resin or thermoplastic resin is impregnated with an inorganic filler and/or a core material such as glass fiber may be used. Through this, voiding and undulation problems can be improved, and warpage control can also be made easier. If necessary, PIE (Photo Image-able Encapsulant) can be used.

The connection structure 140 can rewire the connection pad 120P of the semiconductor chip 120. Through the connection structure 140, the connection pads 120P of tens or hundreds of semiconductor chips 120 with various functions can each be rewired, and through the electrical connection metal 170, they can be physically and/or externally exposed according to their functions through the electrical connection metal 170. Alternatively, they may be electrically connected. The connection structure 140 penetrates the first rewiring layer 142a disposed on the lower surface of the encapsulant 130 and the encapsulant 130, and electrically connects the first rewiring layer 142a with the connection pad 120P. The 1-1 connection via (143a1), the 1-2 connection via (143a2) that penetrates the encapsulant 130 and electrically connects the first redistribution layer (142a) to the first wiring layer (112a), and the encapsulant ( an insulating layer 141 disposed on the lower surface of the 130 and covering at least a portion of the first redistribution layer 142a, a second redistribution layer 142b disposed on the lower surface of the insulating layer 141, and the insulating layer 141. It includes a connection via 143 that penetrates and electrically connects the first and second redistribution layers 142a and 142b.

An insulating material may be used as the material of the insulating layer 141. In this case, a photosensitive insulating material (PID) may be used as the insulating material. In this case, it is possible to introduce a fine pitch through a photo via, thereby forming a fine circuit and It is advantageous for high-density design, and tens to millions of connection pads 120P of the semiconductor chip 120 can be rewired very effectively. If the insulating layer 141 has multiple layers, the boundaries may be distinct or the boundaries may be unclear.

The first and second rewiring layers 142a and 142b may be electrically connected to the electrical connection metal 170 by rewiring the connection pad 120P of the semiconductor chip 120. Materials forming the first and second redistribution layers 142a and 142b include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead (Pb). ), titanium (Ti), or alloys thereof may be used. The first and second redistribution layers 142a and 142b can perform various functions depending on the design. For example, it may include a ground pattern, power pattern, signal pattern, etc. The ground pattern and power pattern may be the same pattern. Additionally, it may include various types of via pads, electrical connection metal pads, etc. The first and second redistribution layers 142a and 142b may be formed through a plating process and may be composed of a seed layer and a conductor layer.

The 1-1 and 1-2 connection vias 143a1 and 143a2 electrically connect the first redistribution layer 142a to the connection pad 120P and the first wiring layer 112a, respectively. The 1-1 and 1-2 connection vias 143a1 and 143a2 are similarly formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead ( It may include metal materials such as Pb), titanium (Ti), or alloys thereof. The 1-1 and 1-2 connection vias 143a1 and 143a2 may include a signal via, a power via, a ground via, etc., and the power via and the ground via may be the same via. The 1-1 and 1-2 connection vias 143a1 and 143a2 may be field-type vias filled with a metal material, or may be conformal-type vias in which a metal material is formed along the wall of the via hole. The 1-1 and 1-2 connection vias 143a1 and 143a2 may also be formed through a plating process and may be composed of a seed layer and a conductor layer. The 1-1 and 1-2 connection vias 143a1 and 143a2 may have different heights. For example, the height of the 1-1 connection via 143a1 may be higher than the height of the 1-2 connection via 143a2. For example, the upper surface of the frame 110 is arranged to be coplanar with the upper surface of the encapsulant 130 and the upper surfaces of the first and second heat dissipation members 125 and 127, and the opposite side thereof may have a step, such as Under the condition of having a step, the opposite side thereof is covered with the encapsulant 130, and the heights of the 1-1 and 1-2 connection vias 143a1 and 143a2 formed thereon may also be different.

The second connection via 143b electrically connects the first and second redistribution layers 142a and 142b to each other. The second connection via 143b is also made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or these. It may contain metal substances such as alloys. The second connection via 143b may also include a signal via, a power via, a ground via, etc., and the power via and the ground via may be the same via. The second connection via 143b may also be a field-type via filled with a metal material, or a conformal-type via in which a metal material is formed along the wall of the via hole. The second connection via 143b may also be formed through a plating process and may be composed of a seed layer and a conductor layer.

The passivation layer 150 is an additional component to protect the connection structure 140 from external physical and chemical damage. The passivation layer 150 may include a thermosetting resin. For example, the passivation layer 150 may be ABF, but is not limited thereto. The passivation layer 150 has an opening that opens at least a portion of the second redistribution layer 142b. There may be tens to tens of thousands of openings, or there may be more or fewer openings. Each opening may be composed of a plurality of holes. If necessary, a surface-mounted component such as a capacitor may be disposed on the lower surface of the passivation layer 150 and electrically connected to the second redistribution layer 142b and, as a result, may be electrically connected to the semiconductor chip 120.

The underbump metal 160 is also an additional component and improves the connection reliability of the electrical connection metal 170, and as a result, the board level reliability of the semiconductor package 100A according to an example can be improved. There may be tens to millions of underbump metals 160, and the number may be more or less. Each underbump metal 160 may be formed in an opening of the passivation layer 150 and electrically connected to the open second redistribution layer 142b. The underbump metal 160 may be formed using a metal using a known metallization method, but is not limited thereto.

The electrical connection metal 170 is also an additional component, and is configured to physically and/or electrically connect the semiconductor package 100A according to one example to the outside. For example, the semiconductor package 100A according to one example may be mounted on the main board of an electronic device through the electrical connection metal 170. The electrical connection metal 170 is disposed on the lower side of the passivation layer 150 and may be electrically connected to the underbump metal 160, respectively. Each of the electrical connection metals 170 may be made of a low melting point metal, for example, tin (Sn) or an alloy containing tin (Sn). More specifically, it may be formed of solder, etc., but this is only an example and the material is not particularly limited thereto.

The electrical connection metal 170 may be a land, ball, pin, etc. The electrical connection metal 170 may be formed as a multi-layer or a single layer. When formed in multiple layers, it may include copper pillars and solder, and when formed as a single layer, it may include tin-silver solder or copper, but this is only an example and is not limited thereto. . The number, spacing, arrangement form, etc. of the electrical connection metals 170 are not particularly limited, and can be sufficiently modified according to design details by a person skilled in the art. For example, the number of electrical connection metals 170 may be tens to millions depending on the number of connection pads 120P, and may be more or less.

At least one of the electrical connection metals 170 is disposed in the fan-out area. The fan-out area refers to an area outside the area where the semiconductor chip 120 is placed. Fan-out packages have superior reliability compared to fan-in packages, enable the implementation of multiple I/O terminals, and facilitate 3D interconnection. In addition, compared to BGA (Ball Grid Array) packages and LGA (Land Grid Array) packages, the package thickness can be manufactured thinner and its price competitiveness is excellent.

FIGS. 11A and 11B are process diagrams schematically showing an example of manufacturing the semiconductor package of FIG. 9. Meanwhile, the process drawings in FIGS. 11A and 11B are shown upside down compared to the structural drawing in FIG. 10 for convenience of explanation.

Referring to FIG. 11A, first, the prepared frame 110 is attached to the tape 200, and the first heat dissipation member 125 is attached to the exposed portion through the penetration portion 110H of the tape 200. Afterwards, the second heat dissipation member 127 is placed on the first heat dissipation member 125. The second heat dissipation member 127 may be in a paste form as described above. Next, the back side of the semiconductor chip 120 is attached to the first and second heat dissipation members 125 and 127. In this process, the second heat dissipation member 127 may be arranged to cover the side surface of the first heat dissipation member 125. The back surface of the semiconductor chip 120 and the first heat dissipation member 125 may be directly connected. Some conductive particles of the second heat dissipation member 127 may exist between the back surface of the semiconductor chip 120 and the first heat dissipation member 125. Next, the frame 110 and the semiconductor chip 120 are covered using the encapsulant 130. The encapsulant 130 can be formed by laminating an insulating film such as ABF on the tape 200.

Referring to FIG. 11B, next, using a laser via or the like, 1-1 and 1-1 penetrate the encapsulant 130 and expose at least a portion of each of the connection pad 120P and the first wiring layer 112a. -2 Via holes (143a1h, 143a2h) are formed. Next, the first redistribution layer 142a and the 1-1 and 1-2 connection vias 143a1 and 143a2 are formed through a plating process. After that, the insulating layer 141 is stacked, a via hole is formed through a photo via, and then a second rewiring layer 142b and a second connection via 143b are formed through a plating process. If necessary, the semiconductor package 100A according to the above-described example can be manufactured by forming the passivation layer 150, the underbump metal 160, and the electrical connection metal 170.

Figure 12 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, the semiconductor package 100B according to another example has a frame 110 of a different shape from the semiconductor package 100A according to the above-described example. Specifically, in another example, the frame 110 is disposed on the first insulating layer 111a, the first wiring layer 112a buried in the upper side of the first insulating layer 111a, and the lower surface of the first insulating layer 111a. The second wiring layer 112b is disposed on the lower surface of the first insulating layer 111a, and the second insulating layer 111b burying the second wiring layer 112b is disposed on the lower surface of the second insulating layer 111b. a third wiring layer (112c), a first wiring via (113a) that penetrates the first insulating layer (111a) and electrically connects the first and second wiring layers (112a, 112b), and a second insulating layer (111b) It includes a second wiring via (113b) that passes through and electrically connects the second and third wiring layers (112b, 112c). Since the frame 110 includes the first to third wiring layers 112a, 112b, and 112c, the design of the connection structure 140 can be simplified. The first to third wiring layers 112a, 112b, and 112c may be electrically connected to the connection pad 120P according to its function.

The first wiring layer 112a may be recessed into the first insulating layer 111a. That is, the top surface of the first insulating layer 111a may have a level difference from the top surface of the first wiring layer 112a. The recess area may have substantially equal upper and lower widths. The width of the top and bottom of the recess area may be substantially the same as the width of the exposed top surface of the first wiring layer 112a. The thickness of each of the first to third wiring layers 112a, 112b, and 112c may be thicker than the thickness of the second redistribution layer 142b. When forming a hole for the first wiring via 113a, some pads of the first wiring layer 112a may serve as a stopper, and the wiring vias of the first wiring via 113a are each on the upper surface. It may be advantageous in the process to have a tapered shape whose width is smaller than the width of the lower surface. That is, the size of the wiring vias of the first wiring via 113a may become smaller as they go from the second wiring layer 112b to the first wiring layer 112a. In this case, the wiring via of the first wiring via 113a may be integrated with the pad pattern of the second wiring layer 112b. Likewise, when forming a hole for the second wiring via 113b, some pads of the second wiring layer 112b can serve as stoppers, and the wiring vias of the second wiring via 113b each have a width of the upper surface. It may be advantageous in the process to have a tapered shape smaller than the width of the lower surface. That is, the size of the wiring vias of the second wiring via 113b may become smaller as they go from the third wiring layer 112c to the second wiring layer 112b. In this case, the wiring via of the second wiring via 113b may be integrated with the pad pattern of the third wiring layer 112c.

Other contents are substantially the same as those described in the semiconductor package 100A according to the example, and detailed descriptions will be omitted.

Figure 13 is a cross-sectional view schematically showing another example of a semiconductor package.

Referring to the drawings, the semiconductor package 100C according to another example has a frame 110 of a different shape from the semiconductor package 100A according to the above-described example. Specifically, the frame 110 includes a first insulating layer 111a, a first wiring layer 112a, a second wiring layer 112b, and a first insulating layer 111a disposed on both sides of the first insulating layer 111a, respectively. A second insulating layer 111b and a third insulating layer 111c are disposed on both sides and cover the first and second wiring layers 112a and 112b, respectively, and a first wiring layer 112a of the second insulating layer 111b. A third wiring layer 112c disposed on the opposite side of the buried side, a fourth wiring layer 112d disposed on the opposite side of the side where the second wiring layer 112b of the third insulating layer 111c is buried, and a first wiring layer 112d. A first wiring via (113a) that penetrates the insulating layer (111a) and electrically connects the first and second wiring layers (112a, 112b), and a first wiring via (113a) that penetrates the second insulating layer (111b) and electrically connects the first and third wiring layers (112a). , 113c), and a third wiring via 113c that penetrates the third insulating layer 111c and electrically connects the second and fourth wiring layers 112b and 112d. Includes. Since the frame 110 has a greater number of wiring layers 112a, 112b, 112c, and 112d, the connection structure 140 can be further simplified. The first to fourth wiring layers 112a, 112b, 112c, and 112d may be electrically connected to the connection pad 120P according to its function.

The first insulating layer 111a may be thicker than the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a can be relatively thick to maintain rigidity, and the second insulating layer 111b and third insulating layer 111c are used to form a larger number of wiring layers 112c and 112d. It may have been introduced. From a similar perspective, the first wiring via (113a) penetrating the first insulating layer (111a) is larger than the second and third wiring vias (113b, 113c) penetrating the second and third build-up layers (111b, 111c). The height and average diameter can be large. Additionally, the first wiring via 113a may have an hourglass or cylindrical shape, while the second and third wiring vias 113b and 113c may have a tapered shape in opposite directions. The thickness of each of the first to fourth wiring layers 112a, 112b, 112c, and 112d may be thicker than the thickness of the second redistribution layer 142b.

Other contents are substantially the same as those described in the semiconductor package 100A according to one example and the semiconductor package 100B according to another example, and detailed descriptions will be omitted.

In the present disclosure, lower, lower, bottom, etc. are used for convenience to mean a downward direction based on the cross section of the drawing, and upper, upper, upper, etc. are used to mean the opposite direction. However, this direction is defined for convenience of explanation, and the scope of the patent claims is not particularly limited by the description of this direction, and the concept of top/bottom can change at any time.

In the present disclosure, the meaning of connected is a concept that includes not only directly connected, but also indirectly connected through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept that includes both cases where it is physically connected and cases where it is not connected. Additionally, expressions such as first, second, etc. are used to distinguish one component from another component and do not limit the order and/or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component without departing from the scope of rights.

The expression 'example' used in the present disclosure does not mean identical embodiments, but is provided to emphasize and explain different unique features. However, the examples presented above do not exclude being implemented in combination with features of other examples. For example, even if a matter explained in a specific example is not explained in another example, it can be understood as an explanation related to the other example, as long as there is no explanation contrary to or contradictory to the matter in the other example.

The terminology used in this disclosure is used to describe examples only and is not intended to limit the disclosure. At this time, singular expressions include plural expressions, unless the context clearly indicates otherwise.

Claims (10)

a semiconductor chip having a first surface on which a connection pad is disposed and a second surface opposite to the first surface;
a first heat dissipation member disposed on a second side of the semiconductor chip;
a second heat dissipation member disposed on the second surface of the semiconductor chip and covering at least a portion of a side surface of the first heat dissipation member;
An encapsulant covering at least a portion of the semiconductor chip; and
a connection structure disposed on a first surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pad; Including,
The first heat dissipation member includes at least one of zirconium, chromium, boron, carbon nanotubes, boron nitride, or a combination thereof,
The second heat dissipation member includes conductive particles,
A semiconductor package in which the conductive particles are partially present between the first heat dissipation member and the semiconductor chip.
According to claim 1,
The first heat dissipation member further includes graphite,
Semiconductor package.
According to claim 2,
The second heat dissipation member further includes a binder resin,
Semiconductor package.
According to claim 1,
The first heat dissipation member and the second heat dissipation member each have at least a portion of the upper surface exposed from the encapsulant,
Semiconductor package.
According to claim 4,
The encapsulant covers at least a portion of the side surface of the second heat dissipation member,
The upper surface of the first heat dissipation member, the upper surface of the second heat dissipation member, and the upper surface of the encapsulant are coplanar with each other,
Semiconductor package.
According to claim 1,
On a plane, the area of the semiconductor chip is larger than the area of the first heat dissipation member,
Semiconductor package.
According to claim 1,
a frame having a through portion where the semiconductor chip is disposed; It further includes,
The sealant fills at least a portion of the penetration portion,
Semiconductor package.
According to claim 7,
a metal layer disposed on an inner wall of the penetration portion; Containing more,
Semiconductor package.
According to claim 7,
The frame includes one or more wiring layers,
Semiconductor package.
According to clause 9,
The connection structure includes a first rewiring layer disposed on the lower surface of the encapsulant, a 1-1 connection via that penetrates the encapsulant and electrically connects the first rewiring layer and the connection pad, and a 1-1 connection via that penetrates the encapsulant and electrically connects the A 1-2 connection via electrically connecting the first redistribution layer and the lowest wiring layer among the wiring layers, an insulating layer disposed on a lower surface of the encapsulant and covering at least a portion of the first redistribution layer, and disposed on a lower surface of the insulating layer. a second redistribution layer, and a second connection via that penetrates the insulating layer and electrically connects the first and second redistribution layers to each other,
The first and second connection vias have different heights,
Semiconductor package.

Images