KR102634963B1 - Vertical semiconductor devices and methods of forming the same - Google Patents

Abstract

The semiconductor device manufacturing method forms an upper laminate including a first upper insulating layer, a first upper sacrificial layer, a second upper insulating layer, a second upper sacrificial layer, and an upper buffer layer on a base insulating layer. First vertical holes penetrating the upper laminate are formed, and first recesses and second recesses are formed. Gate dielectric layer patterns and channel layer patterns are formed to cover the side surfaces of the first and second recesses. A body insulating layer is formed, and second vertical holes are formed. Bit line pillars are formed to fill the second vertical holes, and a first trench is formed. The first upper sacrificial layer exposed in the first trench is removed to form third recesses, and word lines are formed to fill the third recesses. The second upper sacrificial layer and the upper buffer layer exposed in the first trench are removed to form fourth and fifth recesses, and plate lines are formed to fill the fourth and fifth recesses. .

Description

Vertical semiconductor devices and methods of forming the same}

This application relates to semiconductor devices, and in particular, to vertical semiconductor devices and methods of manufacturing them.

There is a continuing need to increase the performance of semiconductor devices and the degree of integration of semiconductor devices. Placing unit cells of semiconductor devices on a two-dimensional plane is reaching its limit in continuously increasing the degree of integration of semiconductor devices. Attempts are being made to develop technologies that greatly increase the degree of integration of semiconductor devices by three-dimensionally integrating their unit cells. Attempts to increase the integration of memory devices such as NAND devices and DRAM devices are being attempted in various forms.

This application seeks to propose a method of manufacturing a vertical semiconductor device. This application seeks to present a vertical semiconductor device.

The problem to be solved in this application is not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the present application presents a method of manufacturing a semiconductor device. The semiconductor device manufacturing method includes forming an upper laminate including a first upper insulating layer, a first upper sacrificial layer, a second upper insulating layer, a second upper sacrificial layer, and an upper buffer layer on a base insulating layer; forming first vertical holes penetrating the upper laminate; forming first recesses by partially removing the first and second upper sacrificial layers and the first and second upper insulating layers exposed to the first vertical holes; forming second recesses by further removing the second upper sacrificial layer exposed to the first recesses; forming gate dielectric layer patterns and channel layer patterns covering side surfaces of the first and second recesses; forming a body insulating layer that covers the channel layer patterns and fills the first vertical holes; forming second vertical holes penetrating the body insulating layer and exposing one ends of the channel layer patterns; forming bit line pillars filling the second vertical holes; forming a first trench extending across a portion between the bit line pillars and penetrating the upper stack; forming third recesses by removing the first upper sacrificial layer exposed in the first trench; and forming word lines that fill the third recessed portions.

A semiconductor device manufacturing method according to another aspect of the present application includes forming a lower laminate including a lower buffer layer, a second lower sacrificial layer, a second lower insulating layer, a first lower sacrificial layer, and a first lower insulating layer. ; forming a base insulating layer on the lower laminate; forming an upper laminate including a first upper insulating layer, a first upper sacrificial layer, a second upper insulating layer, a second upper sacrificial layer, and an upper buffer layer on the base insulating layer; forming first vertical holes penetrating the upper and lower laminates and the base insulating layer; The first and second upper sacrificial layers exposed to the first vertical holes, the first and second upper insulating layers, the first and second lower sacrificial layers, and the first and second lower insulating layers. forming first recesses by removing some of the layers; forming second recesses by further removing the second lower and second upper sacrificial layers exposed to the first recesses; forming gate dielectric layer patterns and channel layer patterns covering side surfaces of the first and second recesses; forming a body insulating layer that covers the channel layer patterns and fills the first vertical holes; forming second vertical holes penetrating the body insulating layer and exposing one ends of the channel layer patterns; forming bit line pillars filling the second vertical holes; forming a first trench extending across a portion between the bit line pillars and penetrating the upper and lower stacked structures; forming third recesses by removing the first upper and first lower sacrificial layers exposed in the first trench; and forming word lines that fill the third recesses.

A semiconductor device according to one aspect of the present application includes a vertical bit line pillar; a body insulating layer including a base portion surrounding an outer peripheral surface of the bit line pillar, a first protrusion portion primarily protruding laterally from the base portion, and a second protrusion portion secondarily protruding laterally from the first protrusion portion; a channel layer pattern extending vertically to cover the outer peripheral surface of the body insulating layer; a gate dielectric layer pattern covering the channel layer pattern; a word line extending so that a side surface overlaps the first protrusion of the body insulating layer; and an upper cell including a plate line extending to overlap the second protrusion of the body insulating layer, wherein one end of the channel layer pattern is connected to the bit line pillar.

According to embodiments of the present application, a method of manufacturing a vertical semiconductor device can be presented. The vertical semiconductor device may include a vertical DRAM device.

1 to 32 are schematic diagrams showing a semiconductor device manufacturing method according to an example.
Figure 33 is a schematic cross-sectional view showing a semiconductor device according to an example.
Figure 34 is a schematic cross-sectional view showing a semiconductor device according to an example.
Figure 35 is a schematic cross-sectional view showing a semiconductor device according to an example.

The terms used in the example description of this application are terms selected in consideration of the functions in the presented embodiments, and the meaning of the terms may vary depending on the intention or custom of the user or operator in the technical field. The meaning of the terms used, if specifically defined in this specification, follows the defined definition, and if there is no specific definition, the meaning may be interpreted as generally recognized by those skilled in the art.

In the example description of this application, descriptions such as “first” and “second”, “top” and “bottom or lower” are intended to distinguish members, limit the members themselves, or indicate a specific order. It is not used to mean, but rather refers to a relative positional relationship and does not limit specific cases where the member is in direct contact or another member is introduced into the interface between them. The same interpretation can be applied to other expressions that describe relationships between components.

Embodiments of the present application can be applied to the technical field of implementing integrated circuits such as DRAM devices, PcRAM devices, or ReRAM devices. Additionally, embodiments of the present application can also be applied to the technical field of implementing memory devices such as SRAM, FLASH, MRAM, or FeRAM, or logic devices with integrated logic circuits. Embodiments of the present application can be applied to the technical field of implementing various products requiring fine patterns.

The same reference signs may refer to the same elements throughout the specification. The same or similar reference signs may be described with reference to other drawings even if they are not mentioned or described in the corresponding drawings. Additionally, even if reference signs are not indicated, description may be made with reference to other drawings.

1 to 32 are diagrams showing a method of manufacturing a vertical semiconductor device according to an example.

Figure 1 is a schematic cross-sectional view showing the steps of forming an upper stack of layers (S1) on a base insulating layer (base insulating layer: 100) according to an example. Figure 1 schematically shows the shape of the X-Z cross section in the X-Y-Z coordinate system.

Referring to FIG. 1, a base insulating layer 100 may be formed on a substrate 1000. The substrate 1000 may be introduced as a handling substrate or a supporting substrate when semiconductor device manufacturing process steps are performed. The substrate 1000 may be made of various materials. The substrate 1000 may include a semiconductor material or an insulating material. The substrate 1000 may include a semiconductor wafer. Substrate 100) is a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, It may include a silicon-germium substrate or a substrate formed through an epitaxial growth process.

The base insulating layer 100 may be formed on the substrate 1000 through a deposition process. The base insulating layer 100 may include a layer of insulating material such as silicon oxide (SiO ₂ ).

A plurality of layers may be sequentially deposited on the base insulating layer 100. A plurality of layers may constitute the upper laminate (S1). The upper stack S1 may be formed as a preliminary structure for forming a unit cell of a vertical semiconductor device. On the base insulating layer 100, a first upper insulating layer 200, a first upper sacrificial layer (300), a second upper insulating layer 400, a second upper sacrificial layer 500, and an upper A buffer layer (upper layer: 600) can be deposited. The upper laminate (S1) includes a first upper insulating layer 200, a first upper sacrificial layer 300, a second upper insulating layer 400, a second upper sacrificial layer 500, and an upper buffer layer 600. It may be composed of a layered structure including:

The first upper insulating layer 200 may be deposited as a layer different from the base insulating layer 100. The first upper insulating layer 200 may be formed as a layer having an etch rate different from that of the base insulating layer 100 in a subsequent etching process step. The first upper insulating layer 200 may be composed of porous silicon oxide (porous SiO ₂ ). The base insulating layer 100 may be formed to include a silicon oxide layer that is more dense than the first upper insulating layer 200 . The first upper insulating layer 200 may be formed to have a thinner thickness than the base insulating layer 100.

The first upper sacrificial layer 300 may be deposited on the first upper insulating layer 200. The first upper sacrificial layer 300 may be formed of a material different from the first upper insulating layer 200 and the base insulating layer 100. The first upper sacrificial layer 300 may be formed as a layer having an etch rate different from that of the first upper insulating layer 200 and the base insulating layer 100 in a subsequent etching process step. The first upper sacrificial layer 300, the first upper insulating layer 200, and the base insulating layer 100 may have an etch selectivity to each other. The first upper sacrificial layer 300 may include a layer of silicon nitride. The first upper sacrificial layer 300 may be formed to have a greater thickness than the first upper insulating layer 200.

The second upper insulating layer 400 may be deposited on the first upper sacrificial layer 300. The second upper insulating layer 400 may be deposited as a layer of a material different from the first upper sacrificial layer 300. The second upper insulating layer 400 may be formed as a layer having an etch rate different from that of the first upper sacrificial layer 300 and the base insulating layer 100 in a subsequent etching process step. The second upper insulating layer 400 may be composed of porous silicon oxide (porous SiO ₂ ). The second upper insulating layer 400 may be formed of a layer of substantially the same material as the first upper insulating layer 200.

A second upper sacrificial layer 500 may be deposited on the second upper insulating layer 400. The second upper sacrificial layer 500 may be formed of a material different from the second upper insulating layer 400 and the base insulating layer 100. The second upper sacrificial layer 500 may be formed as a layer having an etch rate different from the second upper insulating layer 400 and the base insulating layer 100 in a subsequent etching process step. The second upper sacrificial layer 500, the second upper insulating layer 400, and the base insulating layer 100 may have an etch selectivity to each other. The second upper sacrificial layer 500 may be formed as a layer having an etch rate different from that of the first upper sacrificial layer 300.

The second upper sacrificial layer 500 may include a layer of silicon nitride. The second upper sacrificial layer 500 may be formed of silicon nitride having a composition ratio different from that of the first upper sacrificial layer 300. For example, the first upper sacrificial layer 300 may include a layer of silicon nitride having _a composition of _SiN “X1” and “X2” may be different numbers. Since the first upper sacrificial layer 300 and the second upper sacrificial layer 500 are composed of layers of silicon nitride with different compositions, the first upper sacrificial layer 300 and the second upper sacrificial layer ( 500) may have an etch selectivity to each other.

An upper buffer layer 600 may be deposited on the second upper sacrificial layer 500. The upper buffer layer 600 is etched differently from the second upper sacrificial layer 500, the first upper sacrificial layer 300, the second upper insulating layer 400, and the first upper insulating layer 200 in the subsequent etching process step. It can be formed as a layer of a material with a certain rate. The upper buffer layer 600 may include a layer of a different material from the second upper sacrificial layer 500 or the second upper insulating layer 400. The upper buffer layer 600 may be formed including a polysilicon layer.

Before constructing the upper laminate (S1) on the base insulating layer 100, the lower laminate (S2) may be further formed between the base insulating layer 100 and the substrate 1000. The lower stack S2 may be formed on the substrate 1000 before forming the base insulating layer 100. The lower laminated body S2 may have a structure substantially the same as the structure in which the upper laminated body S1 is reversed with the base insulating layer 100 in the center. The lower laminate S2 may be formed to have a decalcomanie configuration or a mirror image shape with respect to the upper laminate S1 with the base insulating layer 100 in the center.

The lower laminate (S2) includes a first lower insulating layer 201, a first lower sacrificial layer 301, a second lower insulating layer 401, and a second lower sacrificial layer 501 below the base insulating layer 100. , and the lower buffer layer 601 may be formed by depositing in the reverse order. That is, the lower buffer layer 601, the second lower sacrificial layer 501, the second lower insulating layer 401, the first lower sacrificial layer 301, and the first lower insulating layer 201 are formed sequentially, The base insulating layer 100 may be formed on the first lower insulating layer 201 of the lower laminate S2. The first lower insulating layer 201, the first lower sacrificial layer 301, the second lower insulating layer 401, the second lower sacrificial layer 501, and the lower buffer layer 601 are the first upper insulating layer 200. ), may be deposited as layers that are substantially the same as each of the first upper sacrificial layer 300, the second upper insulating layer 400, the second upper sacrificial layer 500, and the upper buffer layer 600. The first lower insulating layer 201, the first lower sacrificial layer 301, the second lower insulating layer 401, the second lower sacrificial layer 501, and the lower buffer layer 601 are the first upper insulating layer 200. ), the first upper sacrificial layer 300, the second upper insulating layer 400, the second upper sacrificial layer 500, and the upper buffer layer 600 may be deposited sequentially in the reverse order of the deposition order.

The lower stack S2, the base insulating layer 100, and the upper stack S1 may form one unit stack (SU) in which a plurality of layers are stacked. A plurality of unit stacks SU may be formed on the substrate 1000 to be stacked on top of each other. A structure (SU-N) in which an integer number of unit stacks are stacked (SU-N) may be formed between the substrate 1000 and the unit stack (SU).

The processes for depositing individual layers can be performed using a variety of deposition techniques. For example, the layers may be deposited using Thermal CVD, Plasma enhanced CVD, physical CVD, or Atomic Layer Deposition (ALD) techniques. Atomic layer deposition technology can be effectively used to deposit thin layers.

FIG. 2 is a schematic cross-sectional view showing the step of forming first vertical holes (H1) penetrating the upper laminate (S1) according to an example. Figure 2 schematically shows the shape of the X-Z cross section in the X-Y-Z coordinate system. FIG. 3 is a schematic plan view showing the planar shape in which the first vertical holes H1 of FIG. 2 are formed. Figure 3 schematically shows the shape of the Y-X plane in the X-Y-Z coordinate system.

Referring to FIGS. 2 and 3 , first vertical holes H1 are formed that substantially penetrate the upper laminate S1 and penetrate the base insulating layer 100 located below the upper laminate S1. The first vertical holes H1 may extend vertically further to penetrate the lower stack S2 below the base insulating layer 100 and the stacked structure SU-N. The first vertical holes H1 may be formed through a selective etching process to remove some portions of the unit stack (SU) and the stacked structure (SU-N). For example, an etch mask (not shown) such as a photoresist pattern is formed on the upper buffer layer 600 of the upper stack S1, and the portion exposed to the etch mask is removed by dry etching. Thus, first vertical holes H1 extending vertically can be formed.

FIG. 4 is a schematic cross-sectional view showing the step of forming first recesses (R1) on the side of the first vertical hole (H1) according to an example.

Referring to FIG. 4, the side surfaces of the first and second upper sacrificial layers 300 and 500 and the first and second upper insulating layers 200 and 400 exposed to the first vertical hole H1 are exposed to the first vertical hole H1. It recesses to form a first recessed portion R1 that is concave in the lateral direction. The first recess (R1) may be formed to have an annular shape surrounding the first vertical hole (H1) with the first vertical hole (H1) in the center. The annular shape of the first recess (R1) may have an open shape in the first vertical hole (H1).

The first recess step may include a process of introducing a wet etchant into the first vertical hole H1 to induce each layer to be recessed. By the first recess step, the layers forming the base insulating layer 100, the upper stack S1, and the lower stack S2 may be partially recessed in the lateral direction.

The first and second upper sacrificial layers 300 and 500 and the first and second upper insulating layers 200 and 400 may be recessed laterally larger than the base insulating layer 100 . The upper buffer layer 600 may be recessed laterally smaller than the first and second upper sacrificial layers 300 and 500 and the first and second upper insulating layers 200 and 400. The upper buffer layer 600 may be recessed laterally larger than the base insulating layer 100 . The degree of recess in the order of the base insulating layer 100, the upper buffer layer 600, and the remaining layers may be small.

The upper buffer layer 600 has a first length RD1 with respect to the first recessed sides of the first and second upper sacrificial layers 300 and 500 and the first and second upper insulating layers 200 and 400. ) may protrude toward the first vertical hole (H1). The base insulating layer 100 may protrude toward the first vertical hole H1 by a second length RD2 rather than the protruding end of the upper buffer layer 600. The base insulating layer 100 has a first length ( It may protrude toward the first vertical hole (H1) by an amount equal to the sum of the RD1) and the second length (RD2).

The side surfaces of the first and second lower sacrificial layers 301 and 501 and the first and second lower insulating layers 201 and 401 exposed to the first vertical hole H1 are also first recessed, and One first recess portion R1 may be further formed. Likewise, the first and second lower sacrificial layers 301 and 501 and the first and second lower insulating layers 201 and 401 may be recessed laterally larger than the base insulating layer 100 . The lower buffer layer 601 may be recessed laterally smaller than the first and second lower sacrificial layers 301 and 501 and the first and second lower insulating layers 201 and 401. The lower buffer layer 601 may be recessed laterally larger than the base insulating layer 100. The degree of recess in the order of the base insulating layer 100, the lower buffer layer 601, and the remaining layers may be small.

Through this first recess process, first recess portions R1 may be formed within the stacked structure SU-N from which the first vertical hole H1 is extended.

FIG. 5 is a schematic cross-sectional view showing the step of forming the second recess portion R2 in the first recess portion R1 according to an example.

Referring to FIG. 5, a second recessed portion R2 that is further recessed laterally is formed within the first recessed portion R1. The second recess portion R2 may be formed as a portion where the capacitor portion will be located in a subsequent process. A second recess (R2) may be formed by selectively etching and removing the side surface of the second upper sacrificial layer 500 exposed to the first recess (R1) to form a second recess. The second recess process may be performed as a wet etching process using a wet etchant.

The second recess (R2) may be formed to have an annular shape surrounding the first vertical hole (H1) with the first vertical hole (H1) in the center. The annular shape of the second recess (R2) may have an open shape in the first vertical hole (H1). The resulting recess structure including the first and second recess portions R1 and R2 may be formed in a shape having a stepped structure in the lateral X-axis direction.

A second lower sacrificial layer 501 corresponding to the second upper sacrificial layer 500 is also present in the other first recessed portion (R1) located in the lower laminate (S2) from which the first vertical hole (H1) extends. This additional recess may be further formed to form a second recessed portion (R2). Likewise, second recesses R2 may be further formed in other first recesses R1 in the stacked structure SU-N from which the first vertical hole H1 extends further.

FIG. 6 is a schematic diagram showing the steps of forming a gate dielectric layer 700 and a channel layer 800 covering the sides of the first and second recesses R1 and R2 according to an example. This is a cross-sectional view.

Referring to FIG. 6, a gate dielectric layer 700 is deposited to cover the side surfaces of the structure where the first vertical hole H1 and the first and second recesses R1 and R2 are formed. As a result of the formation of the first vertical hole H1 and the first and second recesses R1 and R2, the side surface of the structure has a curved surface shape. The gate dielectric layer 700 may be formed as a layer that extends to conformally cover the sides of the resulting structure. The channel layer 800 may be formed as a layer extending to cover the surface of the gate dielectric layer 700. The channel layer 800 may be formed as an extended layer to conformally cover the curved surface shape of the gate dielectric layer 700.

The gate dielectric layer 700 may be formed including layers of various dielectric materials. The gate dielectric layer 700 may be formed including a layer of silicon oxide. The channel layer 800 may be formed including various semiconductor materials. The channel layer 800 is a silicon layer doped with impurities, an amorphous indium gallium zirconium oxide (InGaZnO:IGZO) layer, a zirconium stannium oxide ((Zn,Sn)O:ZTO) layer, or an indium stannium oxide ((In,Sn) layer. )O:ITO) layer, a double layer of ITO/IGZO, or an amorphous oxide layer. The channel layer 800 may be formed of a layer containing a gate dielectric material applied to a thin film transistor (TFT). The channel layer 800 may be formed through an atomic layer deposition process that is effective in forming a conformal film.

FIG. 7 is a schematic cross-sectional view showing the steps of separating gate dielectric layer patterns 710 and channel layer patterns 810 according to an example.

Referring to FIG. 7, the gate dielectric layer (700 in FIG. 6) and the channel layer (800 in FIG. 6) covering the side of the base insulating layer 100 facing the first vertical hole (H1) are selectively removed. Thus, the side surface of the base insulating layer 100 is exposed. The upper buffer layer 600 is formed by selectively removing the gate dielectric layer (700 in FIG. 6) and the channel layer (800 in FIG. 6) covering the side facing the first vertical hole (H1) of the upper buffer layer 600. expose the side of In this way, by selectively removing some parts of the gate dielectric layer (700 in FIG. 6) and some parts of the channel layer (800 in FIG. 6), the gate dielectric layer 700 and the channel layer 800 are formed into the gate dielectric layer pattern 710. ) and channel layer patterns 810. The gate dielectric layer patterns 710 and the channel layer patterns 810 may have a structure in which they are stacked perpendicularly to each other along the direction in which the first vertical hole H1 extends.

FIG. 8 is a schematic cross-sectional view showing the steps of forming a body insulating layer 900 that fills the first vertical hole H1 according to an example.

Referring to FIG. 8, the first vertical hole (H1 in FIG. 7) is filled, and the first and second recesses (R1 and R2 in FIG. 7) are filled with an insulating material to form a body insulating layer 900. Since the body insulating layer 900 is formed to cover the channel layer pattern 810, it may be formed as a layer located on the opposite side of the gate dielectric layer pattern 710 and insulating the channel layer pattern 810. The body insulating layer 900 may include an insulating material such as silicon oxide.

FIG. 9 is a schematic cross-sectional view showing the steps of forming second vertical holes H2 penetrating the body insulating layer 900 according to an example.

Referring to FIG. 9 , a portion of the body insulating layer 900 may be selectively removed to form a second vertical hole H2 in the body insulating layer 900 . Some portions of the body insulating layer 900 may be removed through a dry etching process. The second vertical hole H2 may be located at substantially the same position as the first vertical hole (H1 in FIG. 2). The second vertical hole (H2) may be formed to have substantially the same shape as the first vertical hole (H1). The second vertical hole H2 may extend from the upper stack S1 to penetrate the lower stack S2 and the stacked structure SU-N. The second vertical hole H2 may be formed to expose the side surface of the base insulating layer 100. The second vertical hole H2 may be formed to expose one end portion of the channel layer pattern 810 adjacent to the base insulating layer 100 to the side.

FIG. 10 is a cross-sectional view showing the steps of forming pillars of bit lines (1100) according to an example.

Referring to FIG. 10, the second vertical holes H2 are filled with a conductive material to form vertical bit line pillars 1100. The bit line pillar 1100 may be a member that serves as a bit line connected to a cell transistor. The bit line pillar 1100 may have a cylindrical shape extending from the upper stack S1 to penetrate the lower stack S2 and the stacked structure SU-N. The bit line pillar 1100 may be electrically connected to one end of the channel layer pattern 810 in the lateral direction.

The channel layer pattern 810 has one end connected to the side of the bit line pillar 1100 and has a curved shape following the structural shape of the first recess portion R1 and the second recess portion R2. It may be extended. The channel layer pattern 810 may have a cylindric shape surrounding the bit line pillar 1100 with the bit line pillar 1100 in the center. One end of the cylindrical shape is connected to the bit line pillar 1110, and the cylindrical body part may be spaced apart from and insulated from the side of the bit line pillar 1110 by the body insulating layer 900. Since the first recess portion R1 and the second recess portion R2 provide a step shape, the cylindrical shape of the channel layer pattern 810 may also have a cylinder side wall curved to provide a step shape. Since the gate dielectric layer pattern 710 is formed while overlapping the channel layer pattern 810, it may have a cylindrical shape substantially the same as the channel layer pattern 810.

FIG. 11 is a schematic cross-sectional view showing the steps of forming a first trench (T1) according to an example. Figure 11 schematically shows the shape of the X-Z cross section in the X-Y-Z coordinate system. FIG. 12 is a schematic plan view showing the planar shape of the first trench T1 of FIG. 11. Figure 12 schematically shows the shape of the Y-X plane in the X-Y-Z coordinate system.

Referring to FIGS. 11 and 12 , a portion of the upper stack S1 is selectively removed to form a first trench T1 extending long in one direction. The optional removal process may include a dry etch process.

The first trench T1 may extend to penetrate the base insulating layer 100, the lower stack S2, and the structure in which the layers are stacked (SU-N). The first trench T1 may be formed to extend long while separating the bit line pillar 1110 from other neighboring bit line pillars. The first trench T1 may be formed to separate one unit cell including the bit line pillar 1110 from another neighboring unit cell.

FIG. 13 is a schematic cross-sectional view showing the step of forming third recesses R3 in the first trench T1 according to an example.

Referring to FIG. 13, the first upper sacrificial layer (300 in FIG. 11) is removed to form a third recess (R3) in the portion where the first upper sacrificial layer 300 was located. The first upper sacrificial layer 300 can be selectively wet-etched by infiltrating the wet etchant into the first upper sacrificial layer 300 exposed in the first trench (T1) through the first trench (T1). . The first lower sacrificial layer (301 in FIG. 11), which is a layer substantially equal to the first upper sacrificial layer 300, may be selectively removed along with the first upper sacrificial layer 300. As the first lower sacrificial layer 301 is removed, another third recess (R3) may be formed in the lower laminate (S2). Other first upper and first lower sacrificial layers that may be located in the stacked structure (SU-N) may also be removed, and third recesses may be formed in the stacked structure (SU-N).

FIG. 14 is a schematic cross-sectional view showing the step of forming a layer of word line 1200 in the first trench T1 and the third recess R3 according to an example.

Referring to FIG. 14 , the word line layer 1200 may be formed by depositing a conductive material that fills the first trench T1 and the third recess R3. The word line layer 1200 may be formed to fill all of the third recesses R3 located in the upper stack S1, the lower stack S2, and the stacked structure SU-N. The word line layer 1200 may be formed including a conductive silicon layer or a metal layer.

FIG. 15 is a schematic cross-sectional view showing the steps of patterning the word lines 1210 that fill the third recesses R3 according to an example.

Referring to FIG. 15, the word line layer (1200 in FIG. 14) can be etched to separate it into word lines 1210. The word lines 1210 may be formed of conductive patterns that respectively fill the third recesses R3. The process of separating the word lines 1210 may include dry etching the word line layer 1200 to restore the shape of the first trench T1. The word line layer 1200 may be formed to fill all of the third recesses R3 located in the upper stack S1, the lower stack S2, and the stacked structure SU-N. The word line layer 1200 may be formed including a conductive silicon layer or a metal layer.

The word lines 1210 include an upper word line 1211 that fills the third recess (R3) formed in the upper stack (S1) and a lower word line (1212) formed in the lower stack (S2). can do. Additionally, the word lines 1210 may be patterned to be located within the stacked structure (SU-N).

The word line 1210 may be formed as a conductive pattern limited to fill only the third recess R3. The word line 1210 may be formed as a conductive pattern having one side in contact with the gate dielectric layer pattern 710 and surrounding the bit line pillar 1100. The word line 1210, the gate dielectric layer pattern 710, the channel layer pattern 810, and the bit line pillar 1100 may form one cell transistor. Since the portion 811 of the channel layer pattern 810 laterally overlapping the word line 1210 extends perpendicularly to the substrate 1000, the cell transistor may have a vertical transistor structure.

FIG. 16 is a schematic cross-sectional view showing the step of forming the fourth recess portion R4 in the first trench T1 according to an example.

Referring to FIG. 16, the second upper sacrificial layer (500 in FIG. 15) is removed to form a fourth recess (R4) in the portion where the second upper sacrificial layer 500 was located. The second upper sacrificial layer 500 can be selectively wet-etched by infiltrating the wet etchant into the second upper sacrificial layer 500 exposed in the first trench (T1) through the first trench (T1). . Layers substantially equivalent to the second upper sacrificial layer 500, for example, the second lower sacrificial layer (501 in FIG. 15) are also selectively removed, and another fourth recessed portion (R4) is formed in the lower laminate (S2). ) and can be formed in a stacked structure (SU-N).

FIG. 17 is a schematic cross-sectional view showing the step of forming the fifth recess portion R5 in the first trench T1 according to an example.

Referring to FIG. 17, the upper buffer layer (600 in FIG. 16) is removed to form a fifth recess (R5) in the portion where the upper buffer layer 600 was located. The fifth recess portion R5 may be connected to the fourth recess portion R4 and expand the fourth recess portion R4. Accordingly, the portion exposed to the fourth and fifth recesses R4 and R5 of the channel layer pattern 810 may be expanded wider than the portion exposed only to the fourth recess portion R4.

Layers substantially equivalent to the upper buffer layer 600, for example, the lower buffer layer (601 in FIG. 16), are also selectively removed, and another fifth recessed portion (R5) is formed in the lower stacked body (S2) and the stacked structure ( SU-N) can be formed within. By providing a wet etchant to the upper buffer layer 600, the upper buffer layer 600 can be wet removed. At the same time, the lower buffer layer 601 can be selectively wet-etched by infiltrating the wet etchant into the lower buffer layer 601 exposed in the first trench (T1) through the first trench (T1).

FIG. 18 is a schematic cross-sectional view showing the step of forming a plate layer 1300 that fills the fourth and fifth recesses R4 and R5 according to an example.

Referring to FIG. 18 , the plate layer 1300 may be formed by depositing a conductive material that fills the fourth recess (R4) and the fifth recess (R5). The plate layer 1300 may extend to fill the fourth recess R4 and the fifth recess R5 and the first trench T1.

FIG. 19 is a schematic cross-sectional view showing a step of patterning plate lines 1310 filling the fourth and fifth recesses R4 and R5 according to an example. Figure 19 schematically shows the shape of the X-Z cross section in the X-Y-Z coordinate system. FIG. 20 is a schematic plan view showing the planar shape in which the plate line 1310 of FIG. 19 is patterned. Figure 20 schematically shows the shape of the Y-X plane in the X-Y-Z coordinate system.

Referring to FIGS. 19 and 20, the plate layer (1300 in FIG. 18) can be etched and separated into plate lines 1310. The plate lines 1310 may be patterned to have a shape that fills the recess structures including the fourth recess portion R4 and the fifth recess portion R5, respectively. The process of separating the plate lines 1310 may be performed by performing a dry etching process on the plate layer 1300, thereby causing the second trench T2 to separate the plate lines 1310. The second trench T2 may be formed to have substantially the same shape as the first trench T1.

The plate layer 1300 may be etched back so that the upper surface of the bit line pillar 1100 is exposed and the upper surface of the body insulating layer 900 is also exposed. Accordingly, the plate line 1310 may be electrically separated from the bit line pillar 1100. The plate layer 1300 may be further etched so that one side of the word line 1210 is exposed to the second trench T2. Accordingly, the word line 1210 and the plate line 1310 may be electrically separated.

The plate line 1310 may be formed as a conductive pattern limited to fill only the fourth recess (R3) and the fifth recess (R5). The plate line 1310 extends along the curved shape of the gate dielectric layer pattern 710, covering the gate dielectric layer pattern 710, and may be formed as a conductive pattern having a shape surrounding the bit line pillar 1100. The plate line 1310, a portion of the gate dielectric layer pattern 710, and a portion of the channel layer pattern 810 may constitute one cell capacitor. This capacitor consists of capacitor electrodes (capacitor nodes) that face a portion of the channel layer pattern 810 and the plate line 1310, and is formed between a portion of the channel layer pattern 810 and the plate line 1310. A portion of the extended gate dielectric layer pattern 710 may be configured as a capacitor dielectric layer.

The body insulating layer 900 has a step shape in which the portion 901 that fills the first recess (R1) and the portion 902 that fills the second recess (R2) have a step difference in the lateral direction. The plate line 1310 is formed to overlap the portion 902 that fills the second recess portion R2 of the body insulating layer 900. Accordingly, the area where the plate line 1310 overlaps the gate dielectric layer pattern 710 and the channel layer pattern 810 may increase in proportion to the length in which the second recess portion R2 extends in the lateral direction. Since the area where the plate line 1310 overlaps the gate dielectric layer pattern 710 and the channel layer pattern 810 increases, the capacitance that can be provided by the cell capacitor is reduced without introducing the second recess (R2). It may increase compared to other cases.

In this way, a memory cell including a cell capacitor and a cell transistor can be formed. The memory cell may have a DRAM memory cell structure. These memory cells may also be formed in the upper and lower stacks S1 and S2 and in the stacked structure SU-N additionally disposed below them. A process of forming conductive contact plugs that electrically connect such memory cells may be further performed.

FIG. 21 is a schematic cross-sectional view showing the steps of forming the first photoresist pattern 1400 exposing a portion of the plate line 1310 according to an example. Figure 21 schematically shows the shape of the Y-Z cross section in the X-Y-Z coordinate system. FIG. 21 may show a cross-sectional shape cut along the direction in which the plate line 1310 extends in the plan view of FIG. 20. The direction in which the plate line 1310 extends may be the direction in which the word line 1210 extends.

Referring to FIG. 21, a plurality of word lines 1210 are formed in a stacked structure. The word line 1210 may include an upper word line 1211 and a lower word line 1212. The upper word line 1211 formed in the stacked structure S1 and the lower word line 1212 formed in the lower stacked structure S2 are located at different layer levels (layer labels). A process of forming contact plugs that are electrically connected to the upper and lower word lines 1211 and 1212, respectively, may be performed.

A first photoresist pattern 1400 that exposes a portion of the plate line 1310 located on the uppermost layer may be formed. The first photoresist pattern 1400 may be formed as a pattern that covers the bit line pillar 1100 and some other portions of the plate line 1310.

FIG. 22 is a schematic cross-sectional view showing the step of forming a first step shape S1400 exposing a portion of the first upper insulating layer 200 according to an example.

Referring to FIG. 22, a selective etching process is performed using the first photoresist pattern 1400 as an etch mask. A portion of the plate line 1310 located on the uppermost layer is exposed by the first photoresist pattern 1400, and the exposed portion of the plate line 1310 can be removed by selective etching. The exposed portion of the plate line 1310 may be removed and a portion of the exposed second upper insulating layer 400 may be removed. A portion of the second upper insulating layer 400 may be removed, a portion of the exposed upper word line 1211 may be removed, and a portion of the first upper insulating layer 200 may be exposed.

The selective etching process selectively removes portions of the plate line 1310, the second upper insulating layer 400, and the upper word line 1211 to expose a portion of the first upper insulating layer 200. Through this selective removal process, a first step shape S1400 may be formed in which portions of the plate line 1310, the second upper insulating layer 400, and the upper word line 1211 are removed.

FIG. 23 is a schematic cross-sectional view showing the steps of forming the second photoresist pattern 1410 exposing a portion of the plate line 1310 according to an example.

Referring to FIG. 23, a first step shape (S1400) on the plate line 1310 and a second photoresist pattern 1410 exposing a portion of the plate line 1310 adjacent to the first step shape (S1400). can be formed. The second photoresist pattern 1410 can be formed through various processes. For example, the second photoresist pattern 1410 can be formed by shrinking the first photoresist pattern (1400 in FIG. 22) to reduce the width of the first photoresist pattern (1400).

FIG. 24 is a schematic cross-sectional view showing the step of forming a second step shape S1500 exposing a portion of the word line 1210 according to an example.

Referring to FIG. 24, a selective etching process is performed using the second photoresist pattern 1410 as an etch mask. A portion of the plate line 1310 located on the uppermost layer is secondaryly exposed by the second photoresist pattern 1410, and the exposed portion of the plate line 1310 can be removed by selective etching. The exposed portion of the plate line 1310 may be removed, and a portion of the second upper insulating layer 400 that is secondarily exposed may be removed. A portion of the second upper insulating layer 400 may be removed and a portion of the upper word line 1211 may be exposed.

The selective etching process selectively removes portions of the plate line 1310 and the second upper insulating layer 400 to expose portions of the upper word line 1211. The selective etching process may remove some exposed portions of the first upper insulating layer 200 exposed in the first step shape (S1400 in FIG. 23). A portion of the base insulating layer 100 exposed as part of the first upper insulating layer 200 is removed may be removed through an etching process. As part of the base insulating layer 100 is removed, part of the exposed first lower insulating layer 201 may be removed. As a portion of the first lower insulating layer 201 is removed, a portion of the lower word line 1212 may be exposed.

Through this selective removal process, a second step shape S1500 that exposes a portion of the upper word line 1211 and a portion of the lower word line 1212 may be formed. A process of reducing the second photoresist pattern 1410 and a selective etching process are further performed to have a step shape that sequentially exposes some portions of the word lines located in the lower stacked structure (Su-N). The step shape (S1500) can be further expanded. Afterwards, the second photoresist pattern 1410 can be removed.

FIG. 25 is a schematic cross-sectional view showing the steps of forming an insulating filler (1600) that fills the second step shape (S1500) according to an example.

Referring to FIG. 25 , the insulating filler 1600 may be formed by depositing an insulating material that fills the second step shape (S1500). The insulating filler 1600 may be made of various insulating materials including silicon oxide. The insulating filler 1600 may cover exposed portions of the word line 1210 exposed in the second staircase shape S1500 and protect them from subsequent processes.

FIG. 26 is a schematic cross-sectional view showing the steps of forming the third trench T3 according to an example. Figure 26 schematically shows the shape of the Y-Z cross section in the X-Y-Z coordinate system. FIG. 27 is a schematic plan view showing the plan shape of the third trench T3 of FIG. 26. Figure 27 schematically shows the shape of the Y-X plane in the X-Y-Z coordinate system.

Referring to FIGS. 26 and 27 , a plurality of plate lines 1310 are formed in a stacked form in an upper stack (S1), a lower stack (S2), and a stacked structure (SU-N). A process of electrically connecting these plate lines 1310 to each other and forming a contact plug connected to the plate lines 1310 may be performed. To this end, the third trench (T3) penetrating the upper stack (S1), the lower stack (S2), and the stacked structure (SU-N) in which the plate lines 1310 are formed can be formed through a selective etching process. there is. The third trench T3 may extend in a direction substantially perpendicular to the second trench T2 and the first trench T1. If the second trench T2 and the first trench T1 extend in the Y-axis direction, the third trench T3 may be formed to extend in the X-axis direction. The third trench T3 may be located on the opposite side of the second step shape 1500 and the insulating pillar 1600 with the bit line pillar 1100 interposed therebetween. The third trench (T3) may be described as a second trench in the claims for convenience of description.

The third trench T3 is formed to penetrate substantially all of the upper stack S1, the lower stack S2, and the plurality of plate lines 1310 stacked in layers in the stacked structure SU-N. It can be. The third trench T3 may be formed to penetrate all of the layers disposed between the plurality of plate lines 1310. Accordingly, side surfaces 1210S of the word lines 1210 may be exposed to the third trench T3. The side surfaces 1210S exposed to the third trench T3 of the word lines 1210 are sides located on the opposite side of the second step shape 1500 and the insulating pillar 1600 with the bit line pillar 1100 in between. It can be.

FIG. 28 is a schematic cross-sectional view showing the step of forming the sixth recess portion R6 in the third trench T3 according to an example.

Referring to FIG. 28, the side surfaces (1210S in FIG. 26) of the word lines 1210 exposed in the third trench T3 are recessed to selectively remove some portions of the word lines 1210. As some portions of the word lines 1210 are removed, sixth recesses R6 may be formed. The sixth recesses R6 may be formed in the upper stack S1, the lower stack S2, and the stacked structure SU-N.

FIG. 29 is a schematic cross-sectional view showing the step of forming the intermediate insulating layer 1700 in the sixth recess R6 according to an example.

Referring to FIG. 29, the sixth recesses R6 and the third trench T3 are filled with an insulating material, and a portion of the deposited insulating material is removed so that the third trench T3 is exposed and restored. Accordingly, an intermediate insulating layer 1700 having a limited insulating pattern shape may be formed in the sixth recess R6. The intermediate insulating layers 1700 filled in each of the plurality of sixth recesses R6 may be formed as layers that separate the word lines 1210 and the third trench T3.

Figure 30 is a schematic cross-sectional view showing the steps of forming a common plate (common plate: 1800) according to one example.

Referring to FIG. 30 , a common plate 1800 may be formed by depositing a conductive material to fill the third trench T3. The common plate 1800 may be limited to being located within the third trench T3. The common plate 1800 may connect plate lines 1310 that are spaced apart from each other in the vertical and horizontal directions.

FIG. 31 is a schematic cross-sectional view showing the steps of forming conductive contact plugs 1910 and 1950 according to one example. Figure 31 schematically shows the shape of the Y-Z cross section in the X-Y-Z coordinate system. FIG. 32 is a schematic plan view showing the planar shape of the conductive contact plugs 1910 and 1950 of FIG. 31 . Figure 32 schematically shows the shape of the Y-X plane in the X-Y-Z coordinate system.

Referring to FIGS. 31 and 32 , word line contact plugs 1910 connected to exposed portions of the word lines 1210 exposed in the second staircase shape (S1500) may be formed. The word line contact plugs 1910 may be contact plugs having different lengths. The first word line contact plug 1911 may be formed to be connected to a portion of the upper word line 1211 exposed in the second step shape (S1500). The second word line contact plug 1912 may be formed to be connected to a portion of the lower word line 1212 exposed in the second step shape S1500. The insulating filler (1600 in FIG. 30) can be selectively removed.

The plate contact plug 1950 may be formed to connect to the common plate 1800.

FIG. 33 is a schematic cross-sectional view showing a structure in which conductive contact plugs 1910 and 1950 are formed according to an example.

Referring to FIG. 33, the lower stack (S2) is disposed below the upper stack (S1), and the unit stack (SU) is divided from the first unit stack (SU-1) to the nth unit stack (SU-). In the stacked structure SU-N arranged up to n), a second step shape S1500 may be formed to sequentially expose some portions of each word line 1210. Word line contact plugs 1910 may be connected to each exposed portion of the word lines 1210 exposed in the second staircase shape (S1500).

The plate contact plug 1950 is formed to be connected to the common plate 1800 and can be commonly connected to substantially all plate lines 1310. On the other hand, since the word line contact plugs 1910 are individually connected to the word lines 1210, the area where the plate contact plug 1950 is placed may be smaller than the area where the word line contact plugs 1910 are placed. .

FIG. 34 is a schematic cross-sectional view showing a semiconductor device 10 according to an example.

Referring to FIG. 34, the semiconductor device 10 according to an example includes a bit line pillar 1100, a body insulating layer 900, a channel layer pattern 810, a gate dielectric layer pattern 710, a word line 1210, and a vertical semiconductor device including a plate line 1310. The bit line pillar 1100 may have the shape of a conductive pillar extending substantially vertically. The body insulating layer 900 may be formed in a cylindrical shape surrounding the outer peripheral surface of the bit line pillar 1100.

The body insulating layer 900 may be composed of a cylindrical member with a step-shaped outer peripheral surface structure. The body insulating layer 900 includes a base portion 910 that extends to cover the outer peripheral surface of the bit line pillar 1100, a first protrusion 920 that primarily protrudes laterally from the base portion 910, and It may be a structure including a second protrusion 930 that secondarily protrudes laterally from the first protrusion 920. The first protrusion 920 and the second protrusion 930 may be parts extending in a direction perpendicular to the outer peripheral surface of the bit line pillar 1100.

The base portion 910 of the body insulating layer 900 extends between the plate line 1310 and the bit line pillar 1100, and the extended base portion 910 connects the plate line 1310 and the bit line pillar 1100. Can be electrically isolated.

A channel layer pattern 810 is formed to cover the outer peripheral surface of the stepped outer peripheral surface structure provided by the first and second protrusions 920 and 930, and one end of the channel layer pattern 810 is formed with a bit line pillar 1100. ) is electrically connected to the The gate dielectric layer pattern 710 covering the channel layer pattern 810 may extend in a shape that overlaps the channel layer pattern 810.

The word line 1210 may be positioned so that one side 1210L laterally overlaps the first protrusion 920 of the body insulating layer 900. A first overlapping portion 811 of the channel layer pattern 810 overlapping the side surface 1210L of the word line 1210, and a gate dielectric layer pattern overlapping the first overlapping portion 811 of the channel layer pattern 810 ( The bit line pillar 1100 electrically connected to the first overlapping portion 711 of 710 and the channel layer pattern 810 may constitute a cell transistor of a unit cell. Since the first overlapping portion 811 of the channel layer pattern 810 laterally overlapping the word line 1210 is a layer extending substantially vertically, the cell transistor may have a vertical transistor structure.

The plate line 1310 may extend to cover the second protrusion 930 of the body insulating layer 900 and one upper surface of the first protrusion 920. A second overlapping portion 812 of the channel layer pattern 810 and a second overlapping portion 712 of the gate dielectric layer pattern 710 may be located between the plate line 1310 and the body insulating layer 900. The plate line 1310, the second overlapping portion 812 of the channel layer pattern 810, and the second overlapping portion 712 of the gate dielectric layer pattern 710 may form a cell capacitor electrically connected to the cell transistor. . The cell capacitor may be connected substantially vertically to the vertical cell transistor. The cell capacitor and the cell transistor form a unit cell, and the semiconductor device 10 may be configured to include such a unit cell.

The plate line 1310 and the second overlapping portion 812 of the channel layer pattern 810 may form two capacitor electrodes facing each other of a cell capacitor. Since the second protrusion 930 protrudes in the side direction of the first protrusion 910, the area of the plate line 1310 overlapping the second protrusion 930 is proportional to the degree to which the second protrusion 920 protrudes. It can increase. As the area of the plate line 1310 increases, the capacitance of the cell capacitor may increase.

The channel layer pattern 810 may be formed as a medium for electrically connecting the cell capacitor to the cell transistor and the cell transistor to the bit line pillar 1100.

Figure 35 is a schematic cross-sectional view showing a semiconductor device 11 according to an example.

Referring to FIG. 35 , the semiconductor device 11 according to an example may include an upper cell constructed on the base insulating layer 100 and a lower cell constructed below the base insulating layer 100. Since both the lower cell and the upper cell may be composed of DRAM memory cells, the semiconductor device 11 may be composed of a DRAM device.

The upper cell and the lower cell may commonly share the bit line pillar 1100. Since the upper cell and the lower cell are electrically connected to the bit line pillar 1100, the RC delay between the upper cell and the lower cell can be reduced. The upper cell may include an upper capacitor and an upper transistor. The upper capacitor may include the plate line 1310, a portion of the channel layer pattern 810, and a portion of the gate dielectric layer pattern 710. The upper transistor may include the word line 1210, another portion of the channel layer pattern 810, another portion of the gate dielectric layer pattern 710, and a portion of the bit line pillar 1100.

The lower cell may have substantially the same configuration as the upper cell inverted. The lower cell may have a decalcomania shape or a mirror image shape with respect to the upper cell.

The lower cell may include a lower capacitor and a lower transistor. The lower capacitor may include the lower plate line 1310-1, a portion of the lower channel layer pattern 810-1, and a portion of the lower gate dielectric layer pattern 710-1. The lower transistor is connected to the lower word line 1210-1, another portion of the lower channel layer pattern 810-1, another portion of the lower gate dielectric layer pattern 710-1, and another portion of the bit line pillar 1100. It may be composed of parts. The lower cell transistor and the lower cell capacitor may be configured to have a shape in which the upper cell transistor and the upper cell capacitor are inverted under the base insulating layer.

So far, the present invention has been examined focusing on the embodiments. A person skilled in the art to which the present invention pertains will understand that the present invention can be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments should be considered from an illustrative rather than a restrictive perspective. The scope of the present invention is indicated in the claims rather than the foregoing description, and all differences within the equivalent scope should be construed as being included in the present invention.

710: gate dielectric layer pattern,
810: channel layer pattern,
900: body insulation layer,
1100: bit line pillar,
1210: word line,
1310; plate line.

Claims (20)

Forming an upper laminate including a first upper insulating layer, a first upper sacrificial layer, a second upper insulating layer, a second upper sacrificial layer, and an upper buffer layer on the base insulating layer;
forming first vertical holes penetrating the upper laminate;
forming first recesses by partially removing the first and second upper sacrificial layers and the first and second upper insulating layers exposed to the first vertical holes;
forming second recessed portions by further removing the second upper sacrificial layer exposed to the first recessed portions;
forming gate dielectric layer patterns and channel layer patterns covering side surfaces of the first and second recesses;
forming a body insulating layer that covers the channel layer patterns and fills the first vertical holes;
forming second vertical holes penetrating the body insulating layer and exposing one ends of the channel layer patterns;
forming bit line pillars filling the second vertical holes;
forming a first trench extending across a portion between the bit line pillars and penetrating the upper stack;
forming third recesses by removing the first upper sacrificial layer exposed in the first trench; and
A method of manufacturing a semiconductor device comprising: forming word lines that fill the third recesses. According to paragraph 1,
forming a fourth recess by removing the second upper sacrificial layer exposed in the first trench;
forming a fifth recess connected to the fourth recess by removing the upper buffer layer exposed in the first trench; and
A semiconductor device manufacturing method further comprising forming plate lines filling the fourth and fifth recesses. According to paragraph 2,
The word line, portions of the gate dielectric layer pattern and the channel layer pattern overlapping the word line, and the bit line pillar constitute an upper cell transistor,
The plate line, and portions of the gate dielectric layer pattern and the channel layer pattern overlapping the plate line constitute an upper cell capacitor. According to paragraph 3,
The channel layer pattern is
Electrically connecting the upper cell capacitor to the upper cell transistor,
A semiconductor device manufacturing method of electrically connecting the upper cell transistor to the bit line pillar. According to paragraph 4,
The channel layer pattern is
A method of manufacturing a semiconductor device comprising a layer of semiconductor material. According to paragraph 3,
Below the base insulating layer
The upper cell transistor and the upper cell capacitor have an inverted shape.
A semiconductor device manufacturing method in which a lower cell transistor and a lower cell capacitor are formed. According to paragraph 2,
forming a staircase shape exposing a portion of the word line by removing portions of the plate lines and the second upper insulating layer;
forming an insulating filler that fills the step shape;
forming a second trench penetrating the base insulating layer on an opposite side of the step shape with the bit line pillar interposed therebetween;
forming sixth recesses by removing a portion of the word lines exposed to the second trench;
forming an intermediate insulating layer that fills the sixth recesses to separate the word lines from the second trench; and
A semiconductor device manufacturing method further comprising: filling the second trench to form a common plate connecting the plate lines to each other. In clause 7,
a plate contact plug connected to the common plate; and
A method of manufacturing a semiconductor device further comprising forming a word line contact plug connected to the word line exposed in the step shape. In clause 7,
The step of forming the staircase shape is
forming a first photoresist pattern exposing a portion of the plate line;
exposing a portion of the first upper insulating layer by selectively removing portions of the plate line, the second upper insulating layer, and the word line using the first photoresist pattern as an etch mask;
forming a second photoresist pattern by shrinking the first photoresist pattern; and
A semiconductor device further comprising using the second photoresist pattern as an etch mask to selectively remove the plate line and other portions of the second upper insulating layer to expose other portions of the word line. Device manufacturing method. According to paragraph 1,
Below the base insulating layer
A semiconductor device manufacturing method further comprising forming a lower laminated body having a shape in which the upper laminated body is inverted. According to paragraph 1,
The first upper sacrificial layer and the second upper sacrificial layer are
A method of manufacturing a semiconductor device each including silicon nitride layers of different compositions. According to paragraph 1,
The upper buffer layer is
Method for manufacturing a semiconductor device including a polysilicon layer. According to paragraph 1,
The first and second upper insulating layers are
It is formed including a silicon oxide layer,
The method of manufacturing a semiconductor device wherein the base insulating layer includes a silicon oxide layer more dense than the first and second upper insulating layers. forming a lower laminate including a lower buffer layer, a second lower sacrificial layer, a second lower insulating layer, a first lower sacrificial layer, and a first lower insulating layer;
forming a base insulating layer on the lower laminate;
forming an upper laminate including a first upper insulating layer, a first upper sacrificial layer, a second upper insulating layer, a second upper sacrificial layer, and an upper buffer layer on the base insulating layer;
forming first vertical holes penetrating the upper and lower laminates and the base insulating layer;
The first and second upper sacrificial layers exposed to the first vertical holes, the first and second upper insulating layers, the first and second lower sacrificial layers, and the first and second lower insulating layers. forming first recesses by removing some of the layers;
forming second recesses by further removing the second lower and second upper sacrificial layers exposed to the first recesses;
forming gate dielectric layer patterns and channel layer patterns covering side surfaces of the first and second recesses;
forming a body insulating layer that covers the channel layer patterns and fills the first vertical holes;
forming second vertical holes penetrating the body insulating layer and exposing one ends of the channel layer patterns;
forming bit line pillars filling the second vertical holes;
forming a first trench extending across a portion between the bit line pillars and penetrating the upper and lower stacked structures;
forming third recesses by removing the first upper and first lower sacrificial layers exposed in the first trench; and
forming word lines filling the third recessed portions; A semiconductor device manufacturing method comprising. According to clause 14,
forming fourth recesses by removing the second upper and second lower sacrificial layers exposed in the first trench;
forming fifth recessed portions connected to the fourth recessed portions by removing the upper and lower buffer layers exposed in the first trench; and
A semiconductor device manufacturing method further comprising forming plate lines filling the fourth and fifth recesses. According to clause 15,
forming a staircase shape exposing some portions of the word lines by removing portions of the plate lines and the second upper and first lower insulating layers;
forming an insulating filler that fills the step shape;
forming a second trench on an opposite side of the step shape with the bit line pillar in between;
forming sixth recesses by removing portions of the word lines exposed to the second trench;
forming intermediate insulating layers that fill the sixth recesses to separate the word lines from the second trench; and
A semiconductor device manufacturing method further comprising: filling the second trench to form a common plate connecting the plate lines to each other. According to clause 16,
a plate contact plug connected to the common plate; and
A method of manufacturing a semiconductor device further comprising forming a word line contact plug connected to the word line exposed in the step shape. According to clause 16,
The step of forming the staircase shape is
forming a first photoresist pattern exposing a portion of the plate line located on the uppermost layer;
Using the first photoresist pattern as an etch mask to selectively remove portions of the uppermost plate line, the second upper insulating layer, and the word line to expose a portion of the first upper insulating layer. ;
forming a second photoresist pattern by shrinking the first photoresist pattern; and
Using the second photoresist pattern as an etch mask, the plate line of the uppermost layer, some other parts of the second upper insulating layer, some parts of the first upper insulating layer, some parts of the base insulating layer, and A semiconductor device manufacturing method further comprising selectively removing a portion of the first lower insulating layer to expose other portions of the word lines. vertical bit line pillars;
A base portion surrounding the outer peripheral surface of the bit line pillar,
A first protrusion that primarily protrudes laterally from the base portion, and
a body insulating layer including a second protrusion that secondarily protrudes laterally from the first protrusion;
a channel layer pattern extending vertically to cover the outer peripheral surface of the body insulating layer;
a gate dielectric layer pattern covering the channel layer pattern;
a word line extending so that a side surface overlaps the first protrusion of the body insulating layer; and
an upper cell including a plate line extending to overlap the second protrusion of the body insulating layer;
A semiconductor device in which one end of the channel layer pattern is connected to the bit line pillar. According to clause 19,
below the upper cell
A semiconductor device further comprising a lower cell having a shape inverted from the upper cell.

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