WO2024060322A1

WO2024060322A1 - Semiconductor structure, manufacturing method therefor, and memory

Info

Publication number: WO2024060322A1
Application number: PCT/CN2022/124049
Authority: WO
Inventors: 赵文礼
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-09-21
Filing date: 2022-10-09
Publication date: 2024-03-28
Also published as: CN117794235A

Abstract

Disclosed in the embodiments of the present disclosure are a semiconductor structure, a manufacturing method therefor, and a memory. The method comprises: providing a stack structure in which semiconductor layers and sacrificial layers are alternately stacked, the stack structure comprising first stack areas and a second stack area connected to first ends of the plurality of first stack areas, and insulating materials filling parts between the first stack areas; etching in a first direction the sacrificial layers in the second stack area and in part of the first stack areas to form a first multi-layer gap, the semiconductor layers in the second stack area being used for forming a plurality of stacked bit line structures; filling the part of the first multi-layer gap located in the first stack areas to form a first isolation layer; forming in the insulating materials adjacent to the first stack areas an opening in the direction perpendicular to the surface of the stack structure; etching the first isolation layer from the opening so as to remove at least part of the first isolation layer; forming at the opening a word line structure extending in the direction perpendicular to the surface of the stack structure; and forming a plurality of stacked storage structures in each first stack area.

Description

Semiconductor structure and manufacturing method thereof, and memory

Cross-references to related applications

This disclosure is based on the Chinese patent application with application number 202211153060.8, the filing date is September 21, 2022, and the invention name is "Semiconductor Structure and Manufacturing Method, Memory", and claims the priority of the Chinese patent application. The Chinese patent The entire contents of this application are hereby incorporated by reference into this disclosure.

Technical field

The embodiments of the present disclosure relate to the field of semiconductor technology, and relate to but are not limited to a semiconductor structure, a manufacturing method thereof, and a memory.

Background technique

Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory. Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit (bit) is 1 or 0. In the development process of DRAM, as the size further shrinks, the bottleneck encountered by the vertical capacitor structure begins to appear. In order to increase the unit density of capacitors, stacked capacitors began to appear. The gate structure defined by bidirectionally etching the source and drain of DRAM is prone to irregular shapes. The performance and quality of DRAM devices are related to the regularity of the gate structure. How to control the source and drain of DRAM devices? The etching of the electrode and drain electrode to form a gate structure with a target shape has become an urgent problem that needs to be solved.

Contents of the invention

In view of this, embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory.

In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

A stacked structure consisting of semiconductor layers and sacrificial layers stacked alternately is provided; the stacked structure includes a plurality of first stacking regions extending along a first direction, and is connected to the first end of the plurality of first stacking regions and along a first A second stacking area extending in two directions; wherein the first direction intersects the second direction; an insulating material is filled between the first stacking areas;

Etching the sacrificial layer of the second stacking area and part of the first stacking area along the first direction to form a first multi-layer void; the semiconductor layer of the second stacking area is used to form a multi-layer void. A stacked bit line structure;

Filling the portion of the first multi-layer gap located in the first stacking region to form a first isolation layer;

forming an opening perpendicular to the surface of the stacked structure in the insulating material adjacent to the first stacking region;

Etch the first isolation layer from the opening to remove at least part of the first isolation layer;

forming a word line structure extending in a direction perpendicular to the surface of the stacked structure at the opening;

A plurality of stacked memory structures are formed in the first stacking area.

In some embodiments, an etching selectivity ratio of a sacrificial layer material used for the sacrificial layer to a semiconductor material used for the semiconductor layer is greater than or equal to a first preset value.

In some embodiments, the sacrificial layer material is silicon germanium SiGe, and the semiconductor material is silicon Si.

In some embodiments, filling the portion of the first multi-layer void located in the first stacking region to form a first isolation layer includes:

Along the first direction, the first isolation material, the second isolation material and the first isolation material are sequentially filled into the first multi-layer gap to form the first isolation layer; wherein, the first isolation layer A length of a layer along the first direction is greater than or equal to a length of the first multi-layer void within the first stacking region.

In some embodiments, the etching selectivity ratio of the second isolation material to the first isolation material is greater than or equal to a second preset value.

In some embodiments, the step of sequentially filling the first multi-layer gap with a first isolation material, a second isolation material, and the first isolation material to form the first isolation layer includes:

Filling the first multi-layer void with a first isolation material;

Etching the first isolation material and retaining a portion of the first isolation material located in the first stacking region;

Filling the first multi-layer void with a second isolation material;

Etching the second isolation material, and retaining a portion of the second isolation material located in the first stacking region; wherein, along the first direction, the length of the remaining second isolation material is a predetermined gate pole length;

Filling the first multi-layer void with the first isolation material again;

The first isolation material is etched, and the first isolation material located in a portion of the first stacking region and located outside the second isolation material is retained.

In some embodiments, etching the first isolation layer from the opening to remove at least part of the first isolation layer includes:

The first isolation layer is etched from the opening to remove the second isolation material in the first isolation layer.

In some embodiments, forming a word line structure extending in a direction perpendicular to the surface of the stacked structure at the opening includes:

Form a gate oxide layer on the surface of each layer of the semiconductor layer in the opening;

Cover the surface of the gate oxide layer with a first conductive material as a gate conductive layer;

Fill the opening covered with the gate conductive layer with a second conductive material to form the word line structure.

In some embodiments, providing a stacked structure consisting of semiconductor layers and sacrificial layers alternately stacked includes:

provide a substrate;

Stack semiconductor materials and sacrificial layer materials alternately on the substrate;

Etch the stacked semiconductor material and sacrificial layer material along the first direction to form a plurality of first stacking regions extending along the first direction, and a first stacking region connected to the plurality of first stacking regions. One end, and the second stacking area extending along the second direction; the area outside the stacking structure is a groove formed by etching;

The insulating material is filled in the groove formed after etching.

In some embodiments, the method further comprises:

At a second end of the first stacking region away from the second stacking region, etching the insulating material to form a groove located between adjacent first stacking regions;

Filling the slot with isolation material;

Remove the insulating material on a side of the second end away from the first end, and etch part of the sacrificial layer in the first stacking region from the second end in a first direction to form a second multi-layer void ;

The isolation material is filled in the second end of the first stacking region where part of the sacrificial layer is etched away to form a support structure.

In some embodiments, the plurality of stacked memory structures formed in each of the first stacking areas include:

removing the insulating material between the first stacking regions;

Remove the sacrificial layer in the first stacking area so that each layer of the semiconductor layer is suspended;

Perform metal silicide treatment on the surface of the semiconductor layer;

The surface of the semiconductor layer after metal silicide treatment is covered with a first metal material to form a lower electrode of the capacitor structure;

Cover the surface of the lower electrode with a dielectric layer;

Cover the surface of the dielectric layer with a third metal material to form an upper electrode of the capacitor structure;

Polysilicon material is filled in the gaps between adjacent semiconductor layers where the upper electrode is formed and in the grooves between the first stacking regions.

In some embodiments, after forming the stacked plurality of capacitor structures, the method further includes:

Remove the isolation material at the second end of the first stacking region, and simultaneously remove at least part of the first isolation layer on the side of the capacitor structure close to the first end to form trenches at both ends of the capacitor structure. groove;

The trenches are filled with insulating material.

In some embodiments, after forming the first isolation layer, the method further includes:

Perform a metal silicide treatment on the semiconductor layer not covered by the first isolation layer in the second stacking region along the second direction;

Covering the surface of the semiconductor layer with a second metal material;

Etch the second metal material at the connection between each layer of the semiconductor layer along a third direction to separate the second metal materials covered by each layer of the semiconductor layer from each other; the third direction is perpendicular to the The first direction and the second direction;

An insulating material is filled between each layer of the semiconductor layer covered with the second metal material and on the side of the second stacking area away from the first stacking area; wherein each layer is covered with the semiconductor layer of the second metal material. is the bit line structure.

In some embodiments, the method further includes:

Process the bit line structure to form a step structure whose length decreases from bottom to top;

A bit line lead-out structure is formed on each layer of the stepped structure.

In a second aspect, embodiments of the present disclosure also provide a semiconductor structure, which is formed by the method described in any of the above embodiments.

In a third aspect, an embodiment of the present disclosure also provides a memory, including:

A semiconductor structure formed by the method described in any one of the above embodiments.

The embodiment of the present disclosure uses a unidirectional etching process from the side. After forming the AA (Active Area) region, the middle layer is etched unidirectionally from one end and filled with different isolation materials to define the source of the transistor. , drain and channel length and range. In this way, irregularities in the gate structure caused by bidirectional side etching of the source and drain can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

1A to 1C are schematic diagrams of semiconductor structures formed by bidirectional etching in some embodiments;

Figure 2 is a method flow chart according to an embodiment of the present disclosure.

3 is a schematic diagram of an alternately stacked stack structure composed of a semiconductor layer and a sacrificial layer in an embodiment of the present disclosure;

Figure 4 is a schematic diagram of a semiconductor structure including a first multi-layer void in an embodiment of the present disclosure;

FIG5A is a schematic diagram of a semiconductor structure including a first isolation layer in an embodiment of the present disclosure;

Figure 5B is an enlarged schematic diagram of the first isolation layer in an embodiment of the present disclosure;

6 is a schematic diagram of a semiconductor structure including openings perpendicular to the surface direction of the stacked structure in an embodiment of the present disclosure;

Figure 7 is a schematic diagram of a semiconductor structure with through-holes and openings in an embodiment of the present disclosure;

FIG8A is a schematic diagram of a semiconductor structure including a word line structure in an embodiment of the present disclosure;

FIG. 8B is an enlarged schematic diagram of the word line structure in an embodiment of the present disclosure;

Figure 9 is a schematic diagram of a semiconductor structure including a semiconductor pillar array in an embodiment of the present disclosure;

10 is a schematic diagram of another alternately stacked stack structure composed of semiconductor layers and sacrificial layers in an embodiment of the present disclosure;

Figure 11 is a schematic diagram of a semiconductor structure including a first stacking region and a second stacking region in an embodiment of the present disclosure;

Figure 12 is a schematic diagram of a semiconductor structure in which insulating material is filled between first stacking regions in an embodiment of the present disclosure;

13 is a schematic diagram of a semiconductor structure including a trench between adjacent first stacking regions in an embodiment of the present disclosure;

FIG14 is a schematic diagram of a semiconductor structure including a first support structure located between adjacent first stacking regions in an embodiment of the present disclosure;

FIG15 is a schematic diagram of a semiconductor structure including a second multi-layer void in an embodiment of the present disclosure;

Figure 16 is a schematic diagram of a semiconductor structure including a support structure in an embodiment of the present disclosure;

Figure 17 is a schematic diagram of a semiconductor structure including a second opening in an embodiment of the present disclosure;

FIG. 18A is a schematic diagram of a semiconductor structure including a first multi-layer void according to an embodiment of the present disclosure;

Figure 18B is an enlarged schematic diagram of the first multi-layer void in an embodiment of the present disclosure;

Figure 19 is a schematic diagram of a semiconductor structure including a first isolation structure in an embodiment of the present disclosure;

FIG20 is a schematic diagram of a semiconductor structure including a first isolation portion according to an embodiment of the present disclosure;

Figure 21 is a schematic diagram of a semiconductor structure including a second isolation structure in an embodiment of the present disclosure;

Figure 22 is a schematic diagram of a semiconductor structure including a second isolation portion in an embodiment of the present disclosure;

Figure 23 is a schematic diagram of a semiconductor structure including a third isolation structure in an embodiment of the present disclosure;

24A to 24B are schematic diagrams of a semiconductor structure including a first isolation layer in an embodiment of the present disclosure;

Figure 25 is a schematic diagram of a semiconductor structure including a first metal silicide structure in an embodiment of the present disclosure;

Figure 26 is a schematic diagram of a semiconductor structure including a second metal material layer in an embodiment of the present disclosure;

27A and 27B are schematic diagrams of a semiconductor structure including a fourth metal structure in an embodiment of the present disclosure;

FIG. 27C is a schematic diagram of a semiconductor structure including a first-order line structure in an embodiment of the present disclosure;

Figure 28 is a schematic diagram of a semiconductor structure including a fourth insulating structure in an embodiment of the present disclosure;

29 is a schematic diagram of another semiconductor structure including openings perpendicular to the surface direction of the stacked structure in an embodiment of the present disclosure;

30 is a schematic diagram of another semiconductor structure including a through hole between the first isolation structure and the third isolation structure in an embodiment of the present disclosure;

31A to 31B are schematic diagrams of a semiconductor structure including a gate oxide layer and a gate conductive layer in an embodiment of the present disclosure;

Figure 32 is a schematic diagram of a semiconductor structure covered with a metallic tungsten layer in an embodiment of the present disclosure;

Figure 33 is a schematic diagram of a semiconductor structure including a word line structure in an embodiment of the present disclosure;

34 is a schematic diagram of a semiconductor structure including a semiconductor pillar array in an embodiment of the present disclosure;

Figure 35 is a schematic diagram of a semiconductor structure including a metal suicide layer in an embodiment of the present disclosure;

Figure 36 is a schematic diagram of a semiconductor structure including a first metal material layer in an embodiment of the present disclosure;

FIG37 is a schematic diagram of a semiconductor structure including a dielectric layer in an embodiment of the present disclosure;

Figure 38 is a schematic diagram of a semiconductor structure including a polysilicon layer in an embodiment of the present disclosure;

FIG39 is a schematic diagram of a semiconductor structure covered with photoresist in an embodiment of the present disclosure;

40A is a schematic diagram of a semiconductor structure including trenches located at both ends of the capacitor structure in an embodiment of the present disclosure;

Figure 40B is a schematic diagram of a capacitor structure formed in an embodiment of the present disclosure;

FIG. 41 is a schematic diagram of a semiconductor structure formed in an embodiment of the present disclosure.

Detailed ways

In order to facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that a thorough understanding of the disclosure will be provided, and the scope of the disclosure will be fully conveyed to those skilled in the art.

In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

Generally, terms can be understood, at least in part, from context of use. For example, depending at least in part on context, the term "one or more" as used herein may be used in the singular to describe any feature, structure or characteristic, or may be used in the plural to describe a combination of features, structures or characteristics. . Similarly, terms such as "a" or "the" may equally be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on context.

Unless otherwise defined, the terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the terms "consisting of" and/or "comprising", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or parts but do not exclude one or more others The presence or addition of features, integers, steps, operations, elements, parts, and/or groups. When used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

DRAM is a kind of semiconductor memory. Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit (bit) is 1 or 0. In the development process of DRAM, as the size further shrinks, the bottleneck encountered by the vertical capacitor structure begins to appear. In order to increase the unit density of capacitors, stacked capacitors began to appear. In some embodiments, a DRAM device can be formed by etching the source and drain ends of the transistor in the DRAM toward the channel region. First, as shown in FIG. 1A , the insulating structure 20 is etched to form a plurality of trenches 10 to open both sides of the source and drain regions of the transistor, and the sacrificial layer below the direction of the arrow is removed through a wet etching process. . As shown in Figure 1B, the sacrificial layer etched in Figure 1A is filled with SiN. Because the etched sacrificial layer corresponds to the source and drain regions. The etched sacrifice is irregular, and the filled SiN is also irregular, causing the sacrifice in the gate region of the transistor to be irregular as well. As shown by the box in Figure 1B. As shown in FIG. 1C , during the process of removing the sacrificial layer in FIG. 1B to form the gate structure, since the sacrificial layer removed in FIG. 1B is irregular, the subsequently formed gate structure is also irregular.

The performance and quality of DRAM devices are related to the regularity of the gate structure. How to control the etching of the source and drain electrodes in DRAM devices to form a gate structure with a target shape has become an urgent problem that needs to be solved.

The present disclosure provides a method for manufacturing a semiconductor structure, as shown in FIG2 , the method comprising:

Step S101: Provide a stacked structure consisting of semiconductor layers and sacrificial layers alternately stacked; as shown in FIG. 3, the stacked structure 300 includes a plurality of first stacking regions 320 extending along the first direction (ie, the X direction), and connected to a plurality of first stacking regions 320. The first end D1 of the first stacking area 320 and the second stacking area 310 extending along the second direction (ie, Y direction); wherein the first direction and the second direction are perpendicular to or intersect; between the first stacking areas 320 filled with insulating material;

Step S102: Etch the second stacking region 310 and part of the sacrificial layer of the first stacking region 320 along the first direction to form the first multi-layer gap 510 as shown in FIG. 4; the semiconductor layer of the second stacking region 310 is used to form Multi-layer stacked bit line structure;

Step S103: Fill the portion of the first multi-layer void 510 located in the first stacking region 320 to form the first isolation layer 600 as shown in Figures 5A to 5B;

Step S104, forming an opening 730 perpendicular to the surface of the stack structure 300 as shown in FIG. 6 in the insulating material adjacent to the first stacking region 320;

Step S105: Etch the first isolation layer from the opening 730, as shown in Figure 7 to remove at least part of the first isolation layer;

Step S106, as shown in Figures 8A to 8B, form a word line structure 754 extending in a direction perpendicular to the surface of the stacked structure at the opening 730;

Step S107: Form multiple stacked memory structures in the first stacking area 320.

First, step S101 is performed to provide a semiconductor structure as shown in FIG. 3 . The semiconductor structure includes a stacked structure 300 and an insulating structure 410 . The stacked structure 300 further includes alternately stacked semiconductor layers 101 and sacrificial layers 102 . In some embodiments, the stacked structure 300 may be a superlattice structure. In this case, the semiconductor layer 101 and the sacrificial layer 102 are both thin films, and their thickness may range from several to dozens of atomic layers. The composition material of the semiconductor layer 101 can be a P-type semiconductor material (such as silicon (Si) or germanium (Ge), etc.), an N-type semiconductor material (such as indium phosphide (InP), etc.). The composition material of the sacrificial layer 102 is mainly considered. The etching selectivity ratio between it and the material of the semiconductor layer 101. In some embodiments, if the etching selectivity ratio of the material used for the sacrificial layer 102 and the material used for the semiconductor layer 101 is greater than or equal to the first preset value, the first preset value is the lowest etching selectivity ratio (for example, 10), that is, the material used for the sacrificial layer 102 and the material used for the semiconductor layer 101 that meet the above conditions can be selected. That is, the material of the sacrificial layer 102 can be selected according to the material of the semiconductor layer 101 and the lowest etching ratio to make the selection. In the embodiment of the present disclosure, the material of the semiconductor layer 101 can be silicon Si, and the material of the sacrificial layer 102 can be silicon germanium SiGe. As shown in Figure 3, the stacked structure 300 is formed from AA' along the Y direction The division can be divided into a second stacking area 310 and a plurality of first stacking areas 320, where the second stacking area 310 extends along the second direction (ie, the Y direction), and the first stacking area 320 extends along the first direction (ie, the X direction). ), in some embodiments, the X direction and the Y direction may intersect or be perpendicular. In the embodiment of the present disclosure, the X direction and the Y direction are perpendicular to each other for illustration. Each first stacking area 320 has a The first end D1 (the end close to the second stacking area) is connected to the second stacking area 310. The adjacent first stacking areas 320 can also be filled with insulating material to form an insulating structure 410. The insulating structure 410 It can support the stacking structure. The insulation structure 410 can be located on the side of the second stacking area 310 away from the first stacking area 320, between the first stacking areas 320, and on the side of the first stacking area 320 away from the second stacking area 310. one side.

Step S102 is continued, and the sacrificial layer 102 of the second stacking area 310 shown in FIG. 3 and part of the first stacking area 320 is etched along the X direction to form a first multi-layer gap 510 as shown in FIG. 4 . Instead of etching the second stacking region 310 from the upper surface of the stacked structure along the Z direction, the embodiment of the present disclosure etches the second stacking region 310 and part of the first stacking region 320 along the X direction to remove the second stack. The sacrificial layer 102 in region 310 and a portion of the sacrificial layer 102 in first stack region 320 . The etching method includes but is not limited to dry etching and wet etching. In the embodiment of the present disclosure, wet etching can be used. For example, hydrofluoric acid, nitric acid, hydrogen peroxide, ammonium hydroxide, etc. can be used. or multiple preparation etching solutions. The selection of the etching liquid is not limited to this, and any etching liquid with a high etching selectivity ratio between the material used for the sacrificial layer 102 and the material used for the semiconductor layer 101 can be applied in the embodiments of the present disclosure. As shown in FIG. 4 , the semiconductor structure after performing step S102 has first multi-layer voids 510 . Between adjacent first multi-layer voids 510 are semiconductor layers 101 , including all

semiconductor layers

101 and 101 in the second stacking region 310 . At least part of the semiconductor layer 101 in the first stacking region 320, wherein all of the semiconductor layer 101 in the second stacking region 310 may be subsequently used to form a multi-layer stacked bit line structure.

Step S103 is continued to fill the portion of the first multi-layer void 510 located in the first stacking region 320 as shown in FIG. 4 to form the first isolation layer 600 as shown in FIG. 5 . The method of filling the first multi-layer gap 510 includes, but is not limited to, a growth process and a deposition process. Among them, the deposition process can include chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), plasma enhanced chemical vapor deposition (Plasma Enhanced CVD, PECVD), sputtering (Sputtering), organic metal Chemical vapor deposition (Metal Organic Chemical Vapor Deposition, MOCVD) or atomic layer deposition (Atomic Layer Deposition, ALD), etc. Growth processes include but are not limited to In-Situ Steam Generation (ISSG). The first multi-layer gap 510 may be filled with at least two insulating materials to form the first isolation layer 600 . And at least one insulating material is a low dielectric constant material (that is, the dielectric constant value is lower than the dielectric constant value of SiO2), such as silicon nitride. The first isolation layer 600 can subsequently be used to isolate the word line structure and the capacitor structure, and can also be used to isolate the electrical properties between adjacent transistors on the semiconductor structure.

Step S104 is continued to form an opening 730 perpendicular to the surface direction of the stacked structure as shown in FIG. 6 in the insulating material adjacent to the first stacking area 320 as shown in FIG. 5A. On the insulating material on both sides of the first stacking area 320, select the partial area where the insulating material overlaps the first isolation layer in the X direction for etching. The etching method includes but is not limited to dry etching and wet etching. Etch to form openings 730 perpendicular to the surface direction of the stacked structure. That is, the opening 730 overlaps with a partial area of the first isolation layer in the X direction, and the opening 730 does not overlap with both ends of the first isolation layer. The length of the opening 730 in the The length of the layer in the X direction, the length and shape of the opening 730 can be defined through a mask, and the cross-sectional shape of the opening 730 along the XY direction includes but is not limited to circles, squares, and rectangles. In some embodiments, the center line of the opening 730 in the Y direction may overlap with the center line of the first isolation layer in the Y direction.

Continue to step S105 to etch the first isolation layer from the opening to remove at least part of the first isolation layer.

The first isolation layer may include a plurality of isolation materials, such as a first isolation material and a second isolation material. The first isolation layer may be a sandwich structure including a first isolation material, a second isolation material, and a first isolation material. It may also be a structure in which three materials including a first isolation material, a second isolation material and a third isolation material are arranged in sequence. In embodiments of the present disclosure, the etching liquid can be selected to have a high etching selectivity ratio for the second isolation material compared to the first isolation material and the third isolation material.

To remove at least part of the first isolation layer, specifically, an etching liquid can be poured into the opening to etch and remove the second isolation material in the first isolation layer. As shown in FIG. 7 , after at least part of the first isolation layer is removed, a through hole 740 can be formed, and the through hole 740 is connected to the opening 730 .

Step S106 is continued to form a word line structure 754 extending perpendicularly to the surface direction of the stacked structure 300 as shown in FIGS. 8A and 8B at the opening.

The word line structure 754 includes a gate conductive layer 752, a gate oxide layer 751 and a word line 753. First, a growth process or a deposition process may be used to grow or deposit an oxide layer as the gate oxide layer 751 at the opening 730 . In some embodiments, oxygen atoms can be introduced at the opening 730 in a high temperature environment to combine with atoms (eg, silicon atoms) in the stacked structure 300 to form a high-quality oxide film. In some embodiments, a deposition process, such as chemical vapor deposition (CVD), may also be used to form an oxide film as the gate oxide layer.

The opening 730 covered with the gate oxide layer 751 is then filled with one or more of conductive material (eg, tungsten), polysilicon, or metal suicide to form a gate conductive layer and a word line.

Step S107 is continued to form multiple stacked memory structures in each first stacking area 320 .

The insulating material between the first stacking regions 320 is etched to form the second groove 760 shown in FIG. 9 . Specifically, the non-overlapping area (defined as the sixth interval X6) of the insulating material between the first stacking area 320 and the first isolation layer 600 is etched. In the Z direction, the etching depth may be equal to the first stacking area. The depth of the region 320 is determined by using the substrate 100 as an etching barrier. This may form a second groove 760 between the first stacking areas 320 .

Then the sacrificial layer in the first stacking region 320 can be removed through the etching process, as shown in FIG. 9 , so that the semiconductor layer 101 in the first stacking region 320 is suspended, so that there are a plurality of layers on both sides of the second groove 760 . Semiconductor pillar array 770 is formed by mutually separated semiconductor layers 101 .

Then continue to form a memory structure between the suspended semiconductor layers 101 .

In an embodiment of the present disclosure, the storage structure may include a capacitor structure, and the capacitor structure may include a lower plate, a dielectric layer, and an upper plate. The method of forming the capacitor structure includes depositing a first conductive material between suspended semiconductor layers to form a lower plate, depositing a high dielectric constant material to form a dielectric layer, and depositing a second conductive material to form an upper plate. The above is only an example of forming a storage structure, and the shape of the storage structure includes but is not limited to cylindrical capacitors, disc capacitors, rectangular capacitors, stacked capacitors, and various special-shaped capacitors.

The disclosed embodiment uses a unidirectional side etching process along the X direction. After forming the AA (Active Area) area, unidirectional etching is performed from the side, and isolation materials with different etching selectivities are filled in. The length and range of the source, drain and channel of the transistor are defined according to the areas of the semiconductor layer corresponding to the different isolation materials. This can reduce the problem of irregular gate structure caused by bidirectional side etching of the source and drain.

In some embodiments, in step S103, filling the portion of the first multi-layer gap located in the first stacking region to form a first isolation layer includes:

Step S201, along the first direction, sequentially fill the first isolation material, the second isolation material and the first isolation material into the first multi-layer void to form a first isolation layer; wherein, the length of the first isolation layer along the first direction Is equal to the length of the first multi-layer void located in the first stacking area.

In some embodiments, step S103 may be replaced by step S201.

As shown in FIGS. 5A to 5B , the first isolation layer 600 may be a first isolation portion 611 formed of a first isolation material, a second isolation portion 621 formed of a second isolation material, and a third isolation formed of the first isolation material. A sandwich structure composed of parts 631. Specifically, the forming step includes filling the first isolation material into the first interval X1 of the first multi-layer gap 510 as shown in FIG. 5A along the The second isolation material is filled in the interval X2, and the third isolation material is filled into the third interval X3 of the first multi-layer gap along the X direction. Therefore, the length of the first isolation layer 600 in the X direction is the sum of the distances between the first interval X1, the second interval X2, and the third interval X3. The length of the first isolation layer 600 in the X direction is equal to the length of the first multi-layer void 510 located in the first stacking area, that is, the first multi-layer void 510 located in the first stacking area can be used to form the first isolation layer 600 .

In some embodiments, the etching selectivity ratio of the second isolation material to the first isolation material and/or the third isolation material is greater than or equal to a second preset value. In some embodiments, the second preset value may be is 20. Compared with the first isolation material, the second isolation material has a high etching selectivity ratio, so that when the second isolation material is selectively removed, the first isolation material may not be removed, thereby achieving the purpose of accurately controlling the gate length. The second isolation material refers to the material used to fill the middle portion of the first isolation layer 600 . The first isolation material refers to the material used to fill both sides of the first isolation layer.

In some embodiments, the first isolation material and the third isolation material may be the same.

In some embodiments, in step S201, the first isolation material, the second isolation material and the first isolation material are sequentially filled into the first multi-layer void to form a first isolation layer, including:

Step S301: Fill the first isolation material into the first multi-layer gap;

Step S302: Etch the first isolation material and retain part of the first isolation material located in the first stacking region;

Step S303: Fill the first multi-layer gap with the second isolation material;

Step S304: Etch the second isolation material and retain part of the second isolation material located in the first stacking region; wherein, along the first direction, the length of the remaining second isolation material is a predetermined gate length;

Step S305: Fill the first isolation material into the first multi-layer gap again;

Step S306: Etch the first isolation material, and retain the portion of the first isolation material located in the first stacking region and located outside the second isolation material.

Step S201 can be further divided into steps S301 to S306 in detail.

First, step S301 is performed to fill the first section X1 of the first multi-layer gap 510 with the first isolation material along the X direction as shown in FIG. 4 . The filling method includes but is not limited to a growth process and a deposition process. The first isolation material may be an insulating material, such as silicon nitride.

In some embodiments, if the filling range exceeds the first interval X1, step S302 may be performed to etch the first isolation material and retain the first isolation material in the first interval X1 of the first stack region.

The etching method includes but is not limited to dry etching and wet etching. The first isolation material exceeding the range of the first interval X1 is removed, and the first isolation material located in the first interval X1 of the first stacking region is retained.

Continue to perform step S303, and fill the second isolation material into the second interval X2 of the first multi-layer gap 510 along the X direction. The filling method includes but is not limited to a growth process and a deposition process. The second isolation material can be any insulating material different from the first isolation material. In particular, the second isolation material can be a material with a greater etching selectivity than the first isolation material, so as to facilitate the subsequent selective removal of the second isolation material.

In some embodiments, if the filling range exceeds the second interval X2, step S304 may be performed to etch the second isolation material and retain the second isolation material located in the first stacking region in the second interval X2.

The etching method includes but is not limited to dry etching and wet etching, and the second isolation material exceeding the second interval X2 is removed, and the second isolation material in the second interval X2 of the first stacking area is retained. The length of the retained second isolation material is the predetermined gate length, because the gate of the transistor can be formed in the second interval X2 in the semiconductor layer in the subsequent steps, so the length of the second interval X2 is the predetermined gate length.

The embodiment of the present disclosure uses the length of the second isolation material in the first isolation layer to define the gate length of the semiconductor layer, thereby achieving precise control of the gate length.

Then step S305 is performed to fill the third interval X3 in the first multi-layer gap 510 with the first isolation material again. The third interval X3 may be the remaining interval of the first multi-layer void located in the first stacking region. The filling method includes but is not limited to a growth process and a deposition process. The first isolation material can be any insulating material, such as silicon nitride.

In some embodiments, if the filling range exceeds the third interval X3, step S306 may be performed to etch the excess first isolation material and the first isolation material located in the first stacking region in the third interval X3.

In some embodiments, in step S105, etching the first isolation layer from the opening to remove at least part of the first isolation layer includes:

Step S401 , etching the first isolation layer from the opening 730 in FIG. 6 to remove the second isolation material in the first isolation layer 600 .

In some embodiments, step S105 may be replaced by step S401 .

When the first isolation layer 600 is a first isolation portion 611 composed of a first isolation material, a second isolation portion 621 composed of a second isolation material, and a third isolation portion 631 composed of the first isolation material, it can be regarded as a sandwich structure. Removing at least part of the first isolation layer 600 can be removing the second isolation portion 621 in the first isolation layer 600 to form a through hole 740 as shown in FIG. 7, wherein the through hole 740 can be connected to the opening 730.

In some embodiments, a wet etching process may be used to pour an etching liquid from the opening 730 to remove the second isolation portion 621 in the first isolation layer 600 .

In some embodiments, in step S106, a word line structure extending perpendicular to the surface direction of the stacked structure is formed at the opening, including:

Step S501: Form a gate oxide layer on the surface of each semiconductor layer in the opening;

Step S502: Cover the surface of the gate oxide layer with a first conductive material as a gate conductive layer;

Step S503: Fill the opening covered with the gate conductive layer with the second conductive material to form a word line structure.

In some embodiments, step S106 may be replaced by step S501, step S502, and step S503.

The word line structure may include a gate oxide layer, a gate conductive layer, and a word line connecting a plurality of gates.

First, step S501 is performed to form the gate oxide layer 751 shown in FIG. 8A on the surface of each semiconductor layer 101 in the opening 730 shown in FIG. 7 .

For example, oxygen atoms can be introduced into the surface of each exposed semiconductor layer 101 at the opening 730 in a high temperature environment, and the oxygen atoms combine with the silicon atoms in the exposed semiconductor layer 101 to form a high-quality oxide film, that is, gate oxidation. Object 751. A deposition process, such as chemical vapor deposition (CVD), may also be used to form an oxide film as the gate oxide layer 751.

The constituent materials of the gate oxide layer 751 include, but are not limited to, oxides (eg, silicon oxide, aluminum oxide), nitrogen-doped oxides, and the like. Then step S502 is performed, using a growth process or a deposition process to cover the surface of the gate oxide layer 751 with a first conductive material to form a gate conductive layer 752. The first conductive material may be metal (eg, TiN) or polysilicon.

Then step S503 is performed, using a growth process or a deposition process to fill the opening 730 covered with the gate conductive layer 752 with a second conductive material to form a word line 753. The word line 753, the gate conductive layer 752 and the gate oxide layer 751 together form a word line structure 754.

The second conductive material includes but is not limited to metal (e.g., metal W) and polysilicon. The second conductive material can fill the opening 730 covered with the gate conductive layer 752 to form a word line 753 connecting multiple gates as shown in FIG. 8A. If the deposition height of the second conductive material exceeds the surface of the stacked structure, the excess second conductive material can be removed by CMP.

FIG. 8B is a partially enlarged schematic diagram of the word line structure 754 composed of the gate oxide layer 751, the gate conductive layer 752 and the word line 753.

In some embodiments, in step S101, a stacked structure consisting of semiconductor layers and sacrificial layers alternately stacked is provided, including:

Step S601: Provide a substrate;

Step S602, alternately stack semiconductor materials and sacrificial layer materials on the substrate;

Step S603: Etch the stacked semiconductor material and sacrificial layer material along the first direction to form several first stacking regions extending along the first direction, and connect the first ends of the plurality of first stacking regions and along the second The second stacking area extends in the direction; the area outside the stacking structure is a groove formed by etching;

Step S604: Fill the first insulating material into the groove formed after etching.

In some embodiments, step S101 may include step S601, step S602, and step S603.

First, step S601 is performed to provide a substrate, which can be a P-type semiconductor material substrate (such as a silicon (Si) substrate or a germanium (Ge) substrate, etc.), an N-type semiconductor substrate (such as indium phosphide) (InP) substrate), compound semiconductor material substrate (such as silicon germanium (SiGe) substrate, etc.), silicon-on-insulator (SOI) substrate, and germanium-on-insulator (GeOI) substrate, etc.

Then step S602 is performed, sequentially using a deposition process or a growth process to stack semiconductor materials and sacrificial layer materials on the substrate to form alternately stacked first semiconductor layers 201 and first sacrificial layers 202 on the substrate 100 as shown in FIG. 10 . In some embodiments, the first half-body layer 201 is made of the same material as the substrate 100 .

In some embodiments, sputtering or atomic layer deposition may be used, and a target of semiconductor material (for example, Si) and a target of sacrificial layer material (for example, SiGe) may be provided to form the first layer of the superlattice structure. Semiconductor layer 201 and first sacrificial layer 202.

Then perform step S603: cover the upper surface (for example, the first sacrificial layer 202) of the alternately stacked first semiconductor layer 201 and the first sacrificial layer 202 with a layer of photoresist, and use a patterned mask to align and remove the required part and then expose it. The photoresist can be a negative resist, and the photoresist corresponding to the mask pattern is removed, and the process continues to the portions of the alternately stacked first semiconductor layer 201 and the first sacrificial layer 202 that are not covered by the photoresist. During etching, the substrate 100 may serve as an etch stop layer. Then a stacked structure 300 as shown in FIG. 11 can be formed, which includes a plurality of first stacking areas 320 extending in the X direction, and a first end D1 connected to the plurality of first stacking areas 320 and extending in the Y direction. Second stacking area 310. Several first stacking areas 320 and second stacking areas 310 may form a stacked structure 300, and the area outside the stacked structure 300 is a groove 400 formed by etching.

In some embodiments, step S604 may be continued to fill the groove 400 formed after etching with an insulating material to form the insulating structure 410 shown in FIG. 12 . The insulating structure 410 respectively includes a first insulating structure 411 located on one side of the second stacking area 310 in the negative X direction, a second insulating structure 412 on one/or both sides of the first stacking area 320 in the Y direction, and the first stacking area 320 The second end D2 is the third insulation structure 413 on the side of the positive X direction.

The filling height of the insulating material may be flush with the upper surface of the stacked structure 300 . In some embodiments, if the filling height of the insulating material exceeds the upper surface of the stacked structure 300, CMP (Chemical Mechanical Polishing) may be used to remove excess insulating material. The support structure 410 formed of insulating material can function to support a plurality of first stacking areas 320 and second stacking areas 310 .

In some embodiments, the method further includes:

Step S701: At the second end of the first stacking area away from the second stacking area, etch the insulating material to form a groove between adjacent first stacking areas;

Step S702: Fill the slot with isolation material;

Step S703: Remove the insulating material on the side of the second end away from the first end, and etch part of the sacrificial layer in the first stacking region from the second end along the first direction to form a second multi-layer void;

Step S704: Fill the second end of the first stacking region with part of the sacrificial layer etched away with an isolation material to form a support structure.

After step S604 is executed, steps S701 to S704 may be continued.

First, step S701 is performed. As shown in FIG. 12 , at the second end D2 of the first stacking area 320 away from the second stacking area 310 , the insulating material in the fourth interval X4 is etched to form an adjacent layer as shown in FIG. 13 . slots 402 between the first stacking areas 320 . The first end of the fourth section X4 overlaps with the second end D2 of the first stacking area 320, and the second end of the fourth section X4 is located in the first stacking area 320. The etched insulating material is part of the insulating material in the second insulating structure 412 . The width of the etched groove 402 in the Y direction is the distance between the two first stacking regions 320 in the Y direction, and the length of the etched groove 402 in the X direction is the length of the fourth interval X4.

Then step S702 is performed to fill the trench 402 with an isolation material, which may be a first isolation material, to form a semiconductor structure including a first support structure 420 as shown in FIG. 14 .

The plurality of grooves 402 in FIG. 13 are filled with a fourth isolation material through a deposition process or a growth process to form a first support structure 420 as shown in FIG. 14 . The fourth isolation material includes, but is not limited to, SiN, SiCN, SiBN, and SiON. The upper surface of the first support structure 420 should be flush with the upper surface of the stacked structure. In some embodiments, if the upper surface of the first support structure 420 protrudes from the upper surface of the stacked structure, CMP can be used to remove excess fourth Isolating materials.

Then step S703 is performed to remove the insulating material on the side of the second end D2 away from the first stacking region 320 in FIG. 12 , that is, the third insulating structure 413 is removed, and the fourth isolation material is used as an etching stop layer to form a structure as shown in FIG. The first opening 401 shown in 15 continues to etch part of the sacrificial layer 102 in the first stacking area 320 from the second end D2 along the negative direction of One end of the fifth section X5 is at the second end D2, and the other end of the fifth section X5 is part of the sacrificial layer 102 in the first stacking area) to form a second multi-layer gap 500 as shown in FIG. 15 .

Then, step S704 is performed to fill the second end D2 of the first stacking area 320 where part of the sacrificial layer 102 is etched away with an isolation material, which may be a fifth isolation material, to form a second support structure 421 as shown in FIG. 16 , and the first support structure 420 and the second support structure 421 together constitute a support structure 430 .

The fourth isolation material and the fifth isolation material may be the same or different. In the embodiment of the present disclosure, both the fourth isolation material and the fifth isolation material can be SiN. The second multi-layer gap 500 is filled with the fifth isolation material, and the exposed substrate 100 on the side of the second end D2 of the first stacking area 320 away from the first stacking area is continued to be filled with the fifth isolation material. As a result, the fifth isolation material and the fourth isolation material filled in steps S702 and S704 are connected to each other to form the support structure 430 shown in FIG. 16 to prevent the semiconductor structure from collapsing in subsequent steps.

In some embodiments, in step S107, multiple stacked memory structures are formed in the first stacking area, including:

After the word line structure is formed, a plurality of stacked capacitor structures are formed using the semiconductor layer in the first stacking region.

In some embodiments, the memory structure includes a transistor and a capacitor structure; in some embodiments, the memory structure includes a capacitor structure.

The remaining sacrificial layer in the first stacking region is removed, leaving the semiconductor layer. Based on multiple semiconductor layers, multiple stacked capacitor structures are formed. N sacrificial layers are removed from each first stacking region, so N stacked capacitor structures can be formed; the stacked structure in the embodiment of the present disclosure includes M first stacking regions, which can be used to form N*M capacitor structures.

Step S801, removing the insulating material between the first stacking regions;

Step S802: Remove the sacrificial layer in the first stacking area to make each semiconductor layer suspended;

Step S803: Perform metal silicide treatment on the surface of the semiconductor layer;

Step S804, covering the surface of the semiconductor layer after the metal silicide treatment with a first metal material to form a lower electrode of the capacitor structure;

Step S805: Cover the surface of the lower electrode with a dielectric layer;

Step S806, covering the surface of the dielectric layer with a third metal material to form an upper electrode of the capacitor structure;

Step S807: Fill the gaps between the layers where the upper electrode is formed and the grooves between the first stacking regions with polysilicon material.

In some embodiments, step S107 may be replaced by steps S801 to S807.

First, step S801 is performed to remove the insulating material located in the sixth interval X6 between the first stacking areas as shown in FIG. 33 .

Specifically, photoresist can be coated on the first stacking area 320 and the insulating material shown in FIG. 33 to form a photoresist layer, using a patterned mask (the pattern on the mask is opaque, The pattern of the mask (corresponding to the insulating material) is aligned with the photoresist layer. When the photoresist is negative, the photoresist corresponding to the mask pattern is removed, forming an opening on the photoresist layer. , the size of the opening just covers the insulating material between the first stacking areas. Then, a dry etching or wet etching process is used to remove the insulating material using the substrate as an etching stop layer. After the insulating material is removed, a plurality of second grooves 760 are formed as shown in FIG. 34 .

Step S802 is continued to remove the sacrificial layer 102 in the first stacking region 320 so that each semiconductor layer 101 is suspended. When the material of the semiconductor layer 101 is silicon, a silicon pillar array can be formed. Specifically, an etching solution with a high etching selectivity for the sacrificial layer material can be used to remove the sacrificial layer 102 in the first stack region 320 to expose the semiconductor layer 101 in the first stack layer 320 . The semiconductor layers 101 are not connected to each other and are suspended from each other. A capacitive structure is formed based on said semiconductor layer 101 . The height between the semiconductor layers 101 (along the Z direction) and the length of the semiconductor layer 101 itself (along the Y direction) determine the size of the capacitor structure to a certain extent.

Step S803 is continued to perform a metal silicide treatment on the surface of the semiconductor layer 101 as shown in Figure 34, so that the surface silicon of the semiconductor layer is processed into metal silicide, forming a metal covering the surface of the semiconductor layer as shown in Figure 35. Silicide layer 780. Metal silicides include, but are not limited to, titanium silicide, zirconium silicide, tantalum silicide, tungsten silicide, and the like. On the one hand, metal silicide can prevent Si in the semiconductor layer from reacting with oxygen to form a dense oxide film, so the metal silicide layer 780 can serve as a protective layer for the semiconductor layer. On the other hand, metal silicide has a low resistivity, which can also be used to reduce the contact resistance of a subsequently formed storage capacitor.

Step S804 is continued to cover the surface of the semiconductor layer after metal silicide treatment with a first metal material to form a first metal material layer 790 as shown in FIG. 36 , which is subsequently used to form a lower electrode of a stacked multi-layer storage capacitor. A growth process or a deposition process (eg, atomic layer deposition) may be used to deposit the first metal material onto the surface of the semiconductor layer (including the upper and lower surfaces parallel to the XY plane and the sidewalls in the YZ direction) after the metal silicide treatment.

In some embodiments, the first metal material is also deposited on all exposed surfaces of the semiconductor structure, for example, connecting sidewalls of the first isolation layer between adjacent semiconductor layers (parallel to the YZ direction), removing the first On the substrate surface of the groove behind the insulating material, on the upper surface of the support structure, etc.

Subsequently, at least part of the sidewalls of the first isolation layer connecting adjacent semiconductor layers in the YZ direction can be removed, so that the first metal materials covered by the adjacent semiconductor layers are not connected to each other, that is, the lower electrodes of each capacitor are interconnected. Disconnected.

Then step S805 is performed, using a growth process or a deposition process (eg, atomic layer deposition) to cover the surface of the first metal material layer with the dielectric layer 791 as shown in FIG. 37 . The material of the dielectric layer may be a high-k (dielectric coefficient) dielectric material, such as zirconium oxide (ZrOX) or hafnium oxide (HfO _x ). The dielectric layer 791 may be formed on the sidewall of the first isolation layer in the YZ direction, and the sidewall is connected to a plurality of semiconductor layers whose surfaces are covered with the dielectric layer 791. That is, the dielectric layers in multiple capacitors can be connected to each other.

Then step S806 is performed, using a growth process or a deposition process (eg, atomic layer deposition) to cover the surface of the dielectric layer 791 with a third metal material to form an upper electrode of the capacitor structure. The third metal material covered in step S906 may also be formed on the sidewall of the first isolation layer in the YZ direction, and the sidewall is connected to a plurality of semiconductor layers whose surfaces are covered with the third metal material. That is, the upper electrodes of multiple capacitors can be connected to each other. The first metal material and the third metal material may be the same or different.

Then step S807 is performed, using a growth process or a deposition process to fill the polysilicon material in the silicon pillar array covered with the upper electrode and in the second groove covered with the upper electrode between the first stacking areas to form the polysilicon material shown in Figure 38 Polysilicon layer 793. The height of the upper surface of the filled polysilicon material is flush with the height of the upper surface of the isolation material. In some embodiments, if the height of the upper surface of the filled polysilicon material exceeds the height of the upper surface of the isolation material, the excess can be removed by CMP. polycrystalline silicon material. In the embodiment of the present disclosure, CMP can also be used to remove the first metal material and dielectric layer material higher than the upper surface of the isolation material to form a semiconductor structure as shown in Figure 38, which includes polysilicon connected to the upper electrode of the capacitor. Layer 793. The filled polysilicon material can serve as a common connection layer for the upper electrodes of multiple capacitors to connect to external circuits.

Step S901, remove the isolation material located at the second end D2 of the first stacking area 320 in Figure 38, and simultaneously remove at least part of the first isolation layer close to the second end D2 of the first stacking area 320, forming the structure shown in Figure 40A trenches 912 located at both ends of the capacitor structure. This is because the first metal material is deposited on the sidewall S2 (along the YZ direction, perpendicular to the substrate surface) of the capacitor structure combined with the second end D2 of the first stacking region 320; the capacitor structure is combined with the first isolation layer. The sidewall S3 (along the YZ direction, perpendicular to the substrate surface) is also deposited with a first metal material. The first metal material connects multiple capacitor structures between the semiconductor layers. At this time, the multiple capacitor structures can be removed. The part of the first metal material at the connection separates the lower plates of each capacitor structure, thereby separating each capacitor structure. Specifically, the upper surface of the semiconductor structure as shown in Figure 38 can be covered with a layer of photoresist, and a patterned mask can be used to align the parts that need to be removed, where the corresponding part of the mask pattern is the first stacking area The area where the isolation material is located at the second end D2 of 320 and the area where the first isolation material is located are then exposed. The photoresist may be a negative resist, and then the photoresist corresponding to the mask pattern is removed. As shown in FIG. 39, the remaining photoresist layer is the first photoresist layer 900. The semiconductor structure not covered by the first photoresist layer 900 in FIG. 39 is etched downward, and trenches 912 located at both ends of the capacitor structure as shown in FIG. 40A are formed, which include the first trench 910 and the second trench 912 . Trench 911.

Step S902: Fill the trench 912 shown in FIG. 40A with insulating material. Using a growth process or a deposition process to fill the trenches 912 at both ends of the capacitor structure with insulating materials can avoid the leakage phenomenon caused by the capacitor structure in the semiconductor structure, and at the same time, the capacitor structure can be electrically connected to other structures (for example, peripheral circuit areas). Sexual isolation.

In some embodiments, after forming the first isolation layer 600 as shown in 24A, the method further includes:

Step S1001: Along the second direction (ie, Y direction), perform a metal silicide treatment on the semiconductor layer 101 not covered by the first isolation layer 600 in the second stacking region 310 to form the first metal silicide structure 700 in FIG. 25 ;

Specifically, along the Y direction, the semiconductor layer 101 in the second stacking area 310 (the sacrificial layer in the second stacking area has been removed at this time) is subjected to metal silicide treatment, so that the surface silicon of the semiconductor layer 101 is processed into metal. silicide. For example, titanium silicide, zirconium silicide, tantalum silicide, tungsten silicide, etc. Metal silicide can serve as a protective layer for the semiconductor layer 101 . Metal silicide has a low resistivity and can also be used to reduce the contact resistance of subsequently formed bit lines.

Step S1002: Continue to cover the surface of the semiconductor layer with a second metal material to form a second metal structure 711 as shown in FIG. 27A. Specifically, a growth process or a deposition process (for example, atomic layer deposition) may be used to deposit a second metal material onto the surface of the semiconductor layer covered with metal silicide (including upper and lower surfaces parallel to the XY plane and sidewalls in the YZ direction), The second metal structure 711 is used to subsequently form a bit line structure. In some embodiments, when the second metal material is deposited, it is also deposited on the upper surface of the semiconductor structure to form a second metal material layer 710 as shown in FIG. 26 . At this time, the excess second metal material covering the upper surface of the second stacking region of the semiconductor structure and the second insulating structure can be removed through the CMP process to form a second metal structure located on the semiconductor layer of the second stacking region as shown in FIG. 27A 711.

Step S1003: Etch part of the second metal material at the connection between the semiconductor layers in the second stacking region along the third direction (i.e., the Z direction), so that the second metal material between the semiconductor layers connected in the third direction is etched. are separated from each other; the third direction is perpendicular to the first direction and the second direction. That is, at least part of the second metal material connected between adjacent semiconductor layers and covering the sidewalls of the first isolation layer YZ is removed, so that the semiconductor layers covered with the second metal material are separated from each other. As shown in FIG. 27C , in the second stacking area, the semiconductor layer covered with the second metal material can serve as the first first line structure 712, and multiple first line structures 712 are stacked in the Z direction and separated from each other. The first bit line structure 712 may serve as a target bit line structure or as an intermediate structure for forming the final bit line structure.

Step S1004: Fill insulating material between the semiconductor layers covered with the second metal material (i.e., the first line structure 712) and the side of the second stacking region away from the first stacking region as shown in FIG. 27C, as shown in FIG. The fourth insulation structure 720 shown in 28.

By filling insulating material between the first bit line structures 712, electrical isolation between adjacent first bit line structures 712 is achieved. By also filling the side of the second stacking area away from the first stacking area with insulating material, the plurality of first-order line structures 712 can be supported.

In some embodiments, the method further includes:

Step S1101: Process the bit line structure to form a step structure whose length decreases from bottom to top; the bit line structure can continue to be etched.

Step S1102: Form a bit line lead-out structure on each layer of step structure.

The bit line structure can be introduced through a staircase. The steps may be a structure whose length decreases along the Y direction from bottom to top. A specific method of etching the steps may be: etching the first interval at the first end of the bit line structure to a first depth, etching the second interval at the first end of the bit line structure to a second depth, and so on. until all steps are formed. The first depth is greater than the second depth, and the first interval is the protruding length of the bit line structure of the lowest layer relative to the bit line structure of the penultimate layer.

In the above-mentioned step S1102, a bit line lead-out structure is formed on each layer of the step structure, that is, metal through holes are formed on the steps with different lengths along the Y direction formed in step S1101, and are connected to other conductors as the bit line lead-out structure.

An embodiment of the present disclosure also provides a semiconductor structure, which is formed by the method described in any of the above embodiments. include:

a plurality of first stacking areas extending along the first direction;

A second stacking area connected to the first ends of the plurality of first stacking areas and extending in a second direction; the first direction is perpendicular to the second direction;

Each first stacking area includes a plurality of stacked storage structures;

Each first stacking area also includes a word line structure located between the plurality of memory structures and the second stacking area; the word line structure extends in a direction perpendicular to the surface of the stacking structure;

a first isolation layer located on the sidewall of the word line structure;

The second stacking region includes a multi-layer stacked bit line structure extending along the second direction.

An embodiment of the present disclosure also provides a memory, including:

A semiconductor structure formed by the method of any of the above embodiments.

Embodiments of the present disclosure also include the following examples:

Step S601: Provide a substrate, and the substrate material may be Si.

Step S602: Stack semiconductor materials and sacrificial layer materials alternately on the substrate in sequence. In the embodiment of the present disclosure, the semiconductor material may be Si and the sacrificial layer material may be SiGe. A semiconductor structure as shown in Figure 10 is formed. The semiconductor structure includes a substrate 100, alternately stacked first sacrificial layers 202 and first semiconductor layers 201 from bottom to top. The upper surface S1 of the semiconductor structure may also be the upper surface of the uppermost first semiconductor layer 201 . In other embodiments, the material of the substrate may be different from the semiconductor material of the semiconductor layer.

Step S603: Etch the above-mentioned stacked first sacrificial layer 202 and first semiconductor layer 201 along the X direction to form a stacked structure 300 as shown in Figure 11. The stacked structure 300 can be divided into: It includes several first stacking regions 320 extending along the X direction, including alternately stacked sacrificial layers 102 and semiconductor layers 101; and a first end D1 connected to the plurality of first stacking regions 320 and extending along the Y direction. Two stacking regions 310 include alternately stacked sacrificial layers 102 and semiconductor layers 101 . Here, the end of the first stacking area 320 connected to the second stacking area 320 in the X direction is called the first end D1, and the end of the first stacking area 320 away from the second stacking area 320 in the X direction is called the second end. D2. Here, the direction in which the second end D2 points to the first end D1 can also be defined as the negative X direction, and the direction in which the first end D1 points to the second end D2 can be defined as the positive X direction. The stacked structure 300 is located on the substrate 100, and the area outside the stacked structure 300 is defined as a groove 400 formed by etching. As shown in FIG. 11 , looking downward from the Z direction, the exposed area of the substrate 100 (that is, the substrate not covered by the stacked structure 300 ) may be the area where the groove 400 is located.

Step S604: Fill the groove 400 formed after etching with an insulating material. The insulating material may be oxide (Oxide) to form a semiconductor structure as shown in FIG. 12. The semiconductor structure includes a semiconductor structure located in the groove 400. Insulating structure 410 formed by oxide. The insulation structures 410 respectively include a first insulation structure 411 located on one side of the second stacking area in the negative direction in the The end D2 is the third insulation structure 413 on the side of the positive X direction.

Step S701: At the second end D2 of the first stacking region 320 away from the second stacking region 310, etch the insulating material between the adjacent first stacking regions 320 at the second end D2 to form an insulating layer located between the adjacent first stacking regions 320 as shown in Figure 13. The length of the slot 402 between adjacent first stacking areas 320 in the X direction is X4, and the width of the slot 402 in the Y direction is the distance Y1 between adjacent first stacking areas 320 in the Y direction. . In the embodiment of the present disclosure, the thickness of the second insulation structure 412 in the Z direction may be greater than or equal to the depth of the slot 402 in the Z direction.

Step S702: Fill the groove 402 with a fourth isolation material, which may be SiN, to form a semiconductor structure as shown in FIG14. The semiconductor structure includes a first support structure 420 located in the groove 402 and made of the fourth isolation material SiN. Therefore, the length of the first support structure 420 in the X direction is X4, and the length in the Y direction is Y1.

Step S703: Remove the insulating material on the side of the second end D2 of the first stacking area 320 away from the second stacking area 310 shown in Figure 14 (ie, remove the third insulating structure 413) to form the first opening as shown in Figure 15 401. After removing the third insulating structure 413, continue to etch laterally from the second end D2 in the negative X direction to part of the sacrificial layer 102 in the first stacking region 320. The length of the removed part of the sacrificial layer 102 in the X direction may be X5 , thus forming the second multi-layer void 500 as shown in FIG. 15 , with the semiconductor layer 101 between adjacent second multi-layer voids 500 .

Step S704: Fill the second end D2 of the first stacking region 320 with part of the sacrificial layer etched away, that is, the second multi-layer gap 500 and the first opening 401 shown in FIG. 15, with the fifth isolation material to form the second support structure 421. , the fifth isolation material may be SiN. The second support structure 421 and the above-mentioned first support structure 420 together form a support structure 430 as shown in FIG. 16 . The support structure 430 is used to support the first stacking area 320 . In other embodiments, the fourth isolation material used in step S702 and the fifth isolation material used in step S704 may be different.

Step S102, etching the sacrificial layer 102 of the second stacking area 310 and part of the first stacking area 320 as shown in FIG16 along the positive X direction. Before performing step S102, the first isolation structure 411 can be removed by an etching process, and the sidewall of the second stacking area is used as an etching stop layer to form a semiconductor structure including a second opening 403 as shown in FIG17. Then, based on the semiconductor structure shown in FIG17, step S102 is continued to be performed, and all sacrificial layers in the second stack 320 and sacrificial layers with a length of L3 in the first stacking area 310 are laterally etched along the positive X direction to form a first multi-layer gap 510 as shown in FIGS. 18A to 18B. That is, the length L1 of the first multi-layer gap 510 in the X direction is equal to the sum of the length L2 of the sacrificial layer of the second stacking area 310 in the X direction and the length L3 etched away in the X direction of the first stacking area 320. FIG18B is an enlarged schematic diagram of the first multi-layer gap 510 in FIG18A.

Step S301: Fill at least the first multi-layer gap 510 shown in FIG. 18A with a first isolation material. The first isolation material may be SiN. In some embodiments, the first isolation material can also be used to fill the second opening 403 and the location of the first multi-layer gap 510 to form a first isolation structure 610 as shown in FIG. 19 .

Step S302: Etch the portion of the first isolation structure 610 outside the first interval X1 in Figure 19 along the positive direction of X. The remaining first isolation structure 610 can be recorded as the first isolation portion 611 as shown in Figure 18 , that is, the length of the first isolation portion 611 in the X direction is X1, the first isolation portion 611 is in contact with the semiconductor layer in the first stacking region 320 in the Z direction, and the length pole or drain length. As shown in FIG. 20 , after step S302 is performed, the semiconductor structure still has a second opening 403 on one side of the second stacking region 310 along the negative X direction.

Step S303: Continue to fill the remaining intervals of the first multi-layer gap 510 in Figure 20 that are not filled with the first isolation material with the second isolation material along the positive X direction to form the second isolation structure 620 as shown in Figure 21. The second isolation material may be a low dielectric constant material, that is, a dielectric with a relatively low dielectric constant (k) (lower than SiO ₂ ), which includes but is not limited to inorganic porous materials (for example, silicon oxide porous materials, silicon nitride porous materials materials, etc.) and organic porous materials (e.g., polyethylene porous materials, etc.). In embodiments of the present disclosure, the second isolation material may be different from the first isolation material.

Step S304: Etch the portion of the second isolation structure 620 outside the second interval X2 in Figure 21 along the positive X direction to form a second isolation portion 621 as shown in Figure 22. FIG. 22 is a partial enlarged view of the first multi-layer void filled with the first isolation portion 611 and the second isolation portion 621 . The second isolation portion 621 is in contact with the semiconductor layer in the first stacking region in the Z direction. The length X2 of the second isolation portion 621 in the X direction may be used to define the gate length of the transistor. In subsequent steps, the gate material can be used to replace the second isolation material to produce the gate structure of the transistor. As shown in FIG. 22 , after etching the second isolation structure 620 , there is still a second opening 403 on the side of the second stacking region 310 along the negative X direction.

Step S305: Continue to fill the remaining portion of the first multi-layer gap 510 in FIG. 22 that is not filled with the first isolation material and the second isolation material with the first isolation material along the positive direction of X. The first isolation material is also filled in the second opening 403 to form a semiconductor structure including a third isolation structure 630, a second isolation portion 621 and a first isolation portion 611 as shown in FIG. 23 .

Step S306: Etch the portion of the third isolation structure 630 outside the third interval X3 in Figure 23 along the positive for X3. The third isolation portion 631 is in contact with the semiconductor layer in the first stacking region in the X direction. The length of the third isolation portion 631 in the X direction may be used to define the length of the source or drain of the transistor. For example, the length X1 of the first isolation portion 611 in the X direction is used to define the source (or drain) of the transistor, and the length X3 of the third isolation portion 631 in the pole). Subsequently, ions of different concentrations may be implanted into the semiconductor layer in the first stack region in contact with the first isolation part 611 and the second isolation part in the Z direction to form the source and drain of the transistor.

After steps S301 to S306, the first isolation layer 600 as shown in FIG. 24A and FIG. 24B is formed. Among them, FIG. 24B is a partial enlarged view of the first isolation layer 600 in FIG. 24A. The first isolation layer 600 includes a first isolation part 611, a second isolation part 621 and a third isolation part 631. The first isolation layer 600 is located between the semiconductor layers of the first stacking region, and the first end d1 of the first isolation layer 600 overlaps the first end D1 of the first stacking region 320 in the X direction.

Step S1001 , perform a metal silicide treatment on the semiconductor layer 101 in the second stacking area shown in FIG. 24B that is not covered by the first isolation layer 600 along the X direction to form a first metal silicide structure 700 .

The second stacking region 310 at this time only includes the semiconductor layer 101 . The semiconductor layer 101 located in the second stacking area is processed using a metal silicide process to form a metal silicide 700 covering the surface of the semiconductor layer 101 in the second stacking area 310 as shown in FIG. 25 . Specifically, a PVD process is first used to deposit a layer of metal (for example, Ti, Co, NiPt, etc.) on the surface of the semiconductor layer 101 located in the second stacking area, and then rapid thermal annealing (RTA, Rapid Thermal Annealing) is performed twice. and a selective wet etching process to finally form a first metal silicide structure 700 on the surface of the semiconductor layer 101 in the second stacking region. The metal silicide includes but is not limited to TiSi2 (titanium silicide), CoSi2 (cobalt silicide) and nickel alloy (eg, NiPt, NiAl, NiY) silicide films, etc. In the embodiment of the present disclosure, since the substrate is a Si substrate, metal silicide can also be formed on the exposed surface of the Si substrate at the same time.

Step S1002: Continue to cover the surface of the semiconductor layer 101 located in the second stack structure and covered with metal silicide in FIG. 25 with a second metal material. The second metal material may be TiN. When TiN is actually deposited, TiN will not only cover the surface of the first metal silicide structure 700, but also cover the upper surface S1 of the semiconductor structure shown in FIG. 25. Therefore, when looking down at the semiconductor structure from the Z direction, only the second metal material layer 710 as shown in FIG. 26 can be seen. The second metal material layer 710 on the non-second stacking area may be removed using a CMP process. As shown in FIG. 27A , the remaining second metal material layer 710 located on the second stacking area can be recorded as a second metal structure 711 .

Step S1003: Etch the second metal material at the connections between the semiconductor layers in the Z direction in FIG. 27B, so that the semiconductor layers covered with the second metal material are separated from each other in the Z direction. In some embodiments, when the second metal material is deposited, the second metal material is also deposited on the sidewalls of the first isolation layer 600, so that the adjacent semiconductor layer covered by the second metal material in the second stacking region They can be connected through the second metal material covered by the sidewalls of the first isolation layer 600 .

A partial enlarged view of the second metal structure 711 in the embodiment of the present disclosure is shown in FIG. 27B , which includes a multi-layer stacked first first line structure 712 and a second metal material between adjacent first first line structures 712 . In the embodiment of the present disclosure, a lateral etching process can be used to remove part or all of the second metal material between adjacent first-order line structures 712, as shown in FIG. 27C, so that the first-order line structure 712 is in the Z direction. are not connected to each other. The subsequent first bit line structure 712 can also undergo a step processing process to form a target bit line structure. The target bit line structure of each layer can correspondingly control the memory cells located on the same layer.

Step S1004: Fill insulating material between the semiconductor layers covered with the second metal material as shown in FIG. 27C and on one side of the second stack region along the negative silicon). Among them, each layer of the semiconductor layer covered with the second metal material is the first line structure 712. That is, the oxide is filled between the first first line structure 712 and the side of the second stacking region along the negative X direction to form the fourth insulation structure 720 as shown in FIG. 28 . The fourth insulating structure 720 can not only electrically isolate adjacent first-bit line structures 712, but also play a supporting role in supporting the first-bit line structure 712.

Step S104: Form an opening 730 perpendicular to the surface direction of the stacked structure as shown in FIG. 29 in the insulating material adjacent to the first stacking region 320. The insulating material may be an oxide. Specifically, a portion of the oxide connected to the first stacking region 320 may be etched from the first surface S1 along the Z direction to form the opening 730 . In some embodiments, the coordinate axis interval of the opening 730 in the X direction may be the same as the coordinate axis interval of the second isolation portion 621 in the first isolation layer in the X direction, that is, the length of the second isolation portion 621 in the X direction. is X2, and the width of the opening 730 in the X direction may also be X2. The plane where the upper surface of the lowest semiconductor layer in the stack structure is located can be used as an etching stop layer for the insulating material adjacent to the first stack region 320. That is, the depth of the opening 730 can be equal to the thickness of the stack structure in the Z direction minus one. The thickness of the semiconductor layer in the Z direction.

Step S401: Etch the first isolation layer from the opening 730 in Figure 29 to remove the second isolation part 621 in the first isolation layer. The material used for the second isolation part 621 includes the second isolation material.

In the embodiment of the present disclosure, at least part of the first isolation layer can be removed by using a wet etching process by pouring etching liquid into the opening 730. This part of the first isolation layer can be the above-mentioned second isolation portion 621 to form as follows. The semiconductor structure shown in FIG. 30 includes a plurality of through holes 740 located between the first isolation part 611 and the third isolation part 631. The plurality of through holes 740 are connected through the opening 730 . Subsequently, a word line structure may be formed in the opening 730 and a gate structure may be formed in the through hole 740 . A wordline structure can be used to control multiple gate structures interconnected with it, which further controls multiple transistors.

Step S501: Form a gate oxide layer on the surface of each semiconductor layer 101 in the opening 730 as shown in FIG. 30 .

For example, an atomic layer deposition process may be used to deposit an oxide layer film on both the through hole 740 and the surface of the semiconductor 101 exposed by the opening 730 to form the gate oxide layer 751 in FIG. 31A .

Step S502: Continue to cover the surface of the gate oxide layer 751 with a first metal material (for example, TiN (titanium nitride)) to form the gate conductive layer 752 in FIG. 31A. Specifically, a growth process or a deposition process may be used to further deposit a TiN layer on the thin film of the gate oxide layer 751 as the gate conductive layer 752. In some embodiments, the gate conductive layer 752 also covers the upper surface of the stacked structure to form a semiconductor structure as shown in FIG. 31A. As shown in FIG. 31A , both the gate oxide layer 751 and the gate conductive layer 752 may be located in the through hole 740 and the opening 730 . FIG. 31B is a partial enlarged view of the through hole 740 and the opening 730 in FIG. 31A .

Step S503: Fill the through hole 740 and the opening 730 covered with the gate conductive layer 752 with the second metal material to form the word line structure 753 shown in FIG. 33. Specifically, continue to fill the opening 730 and the through hole 740 covered with the gate oxide layer 751 and the gate conductive layer 752 with the second metal material (for example, metal tungsten W). During the actual filling process, the second metal material and the first metal material can be deposited on the upper surface of the semiconductor structure shown in Figure 30 to form a semiconductor structure with a metal tungsten layer 753 on the upper surface as shown in Figure 32. Subsequently, CMP is used to remove excess metal tungsten layer 753 and gate conductive layer 752 on the upper surface of the semiconductor structure shown in FIG. 32 to expose the opening 730 including the word line structure. As shown in FIG. 33 , the word line structure 754 in the opening 730 includes a gate oxide layer 751 , a gate conductive layer 752 and a metal tungsten layer 753 . Among them, the metal tungsten layer 753 is used to form a word line.

Step S801: An etching process may be used to remove the insulating material between the first stacking areas 320 in FIG. 33 and located in the sixth interval X6. Specifically, the upper surface S1 of the semiconductor structure as shown in FIG. 33 can be covered with a layer of photoresist, and a patterned mask is used to align the portions that need to be removed (the pattern corresponds to the portion between the first stacking regions 320 ). The area where the insulating material is located in the six intervals X6), and then exposed. The photoresist can be a negative resist, and the photoresist corresponding to the mask pattern is removed, and the parts not covered by the photoresist continue to be etched, and the substrate can be used as an etching stop layer.

Step S802, a wet etching process can be used to remove the sacrificial layer in the first stacking area, so that each semiconductor layer is suspended, as shown in Figure 34, to form a semiconductor column array (for example, a silicon column array) 770 arranged along the Z direction and stacked in the X direction on both sides of each second groove 760.

Step S903, metal silicide treatment is performed on the surface of the semiconductor layer 101 in the first stacking area 320, that is, metal silicide treatment is performed on the surface of the semiconductor column array 770. In some embodiments, a layer of metal (e.g., Ti, Co, NiPt, etc.) can be first deposited on the exposed surface of the silicon column array and the substrate silicon using a PVD process. Then, two rapid thermal annealing processes (RTA, Rapid Thermal Annealing) and a selective wet etching process are performed, and finally a metal silicide layer 780 covering the silicon column array and the substrate silicon surface is formed on the surface of the silicon column array as shown in FIG. 35. The metal silicide includes but is not limited to thin films such as TiSi2, CoSi2, and NiPtSi.

Step S804: Use a deposition process to cover the surface of the semiconductor layer after metal silicide treatment with a first metal material. The first metal material can be TiN to form a first metal material layer 790 as shown in Figure 34. The first metal material layer 790 follows Can be further processed for use as a lower electrode of a capacitive structure connected to a transistor.

Step S805: Use a deposition process to cover the surface of the first metal material layer 790 with a dielectric material to form a dielectric layer 791 as shown in FIG37. The dielectric material may be a high dielectric constant material, which refers to a material with a dielectric constant higher than SiO _2. The higher the dielectric constant of the dielectric material, the more capacitance the capacitor structure formed by it can store.

Step S806: Use a deposition process to cover the surface of the dielectric layer 791 with a third metal material, where the third metal material may be TiN to form an upper electrode of the capacitor structure.

At this point, the first metal material layer 790, the dielectric layer 791 and the upper electrode are formed on all the silicon pillar arrays and the exposed surfaces of the silicon substrate. The upper electrodes between adjacent silicon pillars are not connected to each other. Then step S807 is performed to fill polysilicon material in the gaps between the layers of silicon pillars covered with the upper electrode and in the grooves 760 between the first stacking areas covered with the upper electrode. In some embodiments, the polysilicon material will also cover the upper surface of the uppermost silicon pillar. At this time, the excess polysilicon material, dielectric material and third metal material deposited on the upper surface can be removed through the CMP process. A semiconductor structure as shown in Figure 38 is formed. As shown in Figure 38, the semiconductor structure includes a polysilicon layer 793.

In order to use the first metal material layer as the lower electrode of the capacitor structure, the first metal material layer can also be divided into a plurality of mutually separated lower electrodes, so that the first metal material layer contained between each capacitor structure does not Electrical connection.

Step S901: Remove the isolation material located at the second end D2 of the first stacking area 320 in FIG. 38, that is, the support structure 430, and simultaneously remove at least part of the first isolation layer close to the second end D2 of the first stacking area 320, that is, First isolation portion 611 to form trenches 912 at both ends of the capacitor structure as shown in Figure 40A. In the embodiment of the present disclosure, when the first metal material is deposited, the first metal material will also cover the sidewall S3 of the first isolation structure 611. At this time, part of the first isolation layer connected to the first metal material layer can be removed. 600 (or first isolation portion 611). In the embodiment of the present disclosure, the first isolation portion 611 and the first metal material layer covering the surface S3 of the first isolation portion 611 can be removed. Therefore, the first metal material layers included in each layer of the capacitor structure are not connected to each other.

The first metal material also covers the exposed side wall S2 of the support structure 430 . Therefore, the first metal material layer covered by the support structure 430 and its side wall S2 can be removed at the same time. After step S1001, trenches 912 located at both ends of the capacitor structure as shown in FIG. 40A may be formed. The groove 912 includes a first groove 910 and a second groove 911 . Specifically, the semiconductor structure shown in FIG. 38 can be covered with photoresist, a patterned mask is used to align the portions that need to be removed, and then exposed. The photoresist can be a negative resist, then the photoresist corresponding to the mask pattern is removed, and the remaining photoresist is as shown in Figure 39. Then, an etching process is used to remove the portion not covered by the photoresist in FIG. 39 to form a semiconductor structure as shown in FIG. 40A. The capacitor structure included in the semiconductor structure is as shown in FIG. 40B. The capacitor structure is located between silicon pillars whose surfaces are covered with a metal silicide layer 780, and includes a lower electrode 794, a dielectric layer 791 and an upper electrode 792. The upper electrode 792 also has a polysilicon layer 793 inside. The lower electrodes 794 of different capacitances are not connected to each other, and the upper electrodes 792 of different capacitances are connected together through the polysilicon layer 793 .

Step S902 is performed to fill the trench 912 with insulating material. The trench 912 shown in Figure 40A is filled with an insulating material, such as an oxide, using a growth process or a deposition process. Insulating material wraps around the transistors to electrically isolate adjacent transistors to reduce leakage from the transistors.

In some embodiments, step S1101 may also be performed to process the first bit line structure 712 shown in FIG. 41 to form a step structure whose length decreases from bottom to top. The first line structures located on different layers can be etched with different depths and different widths. For example, a deeper etching process is performed on the first bit line structure in the lower layer, and a shallower etching process is performed on the first bit line structure in the upper layer. The etching width of the lower first bit line structure along the Y direction is smaller than the etching width of the upper first bit line structure along the Y direction, thereby forming a bit line structure with a step structure whose length decreases from bottom to top. .

Step S1102: Form a bit line lead-out structure on each layer of step structure. Conductive material can be deposited on the surface of each step that is not covered by the previous step to form a bit line lead-out structure on each step structure.

In the embodiment of the present disclosure, a one-way side eating method is used to form the support structure of the bottom frame of the storage structure. In the later process of forming the storage structure, the support structure is etched and the lower electrode material at the connection between the upper and lower storage structures is removed. , thereby isolating the upper and lower capacitor structures from each other. After forming the AA area, a one-way side eating method is used and filled with different isolation materials to define the length and range of the source, drain and channel of the transistor. The one-way side eating process can avoid the two-way side eating process caused by The problem of irregular gate structure. Embodiments of the present disclosure also perform metal silicide treatment on the Si layer connected to the capacitor structure and the bit line structure, thereby enhancing the conduction performance of the capacitor structure and the bit line structure.

It will be understood that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the size of the sequence numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its functions and internal logic, and should not be used in the embodiments of the present disclosure. The implementation process constitutes any limitation. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments.

It should be noted that, in this document, the terms "comprising", "comprises" or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device that includes a series of elements not only includes those elements, It also includes other elements not expressly listed or inherent in the process, method, article or apparatus. Without further limitation, an element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article or apparatus that includes that element.

The above are only embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Industrial applicability

Claims

A method of manufacturing a semiconductor structure, the method comprising:

A stacked structure consisting of semiconductor layers and sacrificial layers stacked alternately is provided; the stacked structure includes a plurality of first stacking regions extending along a first direction, and is connected to the first end of the plurality of first stacking regions and along a first A second stacking area extending in two directions; wherein the first direction intersects the second direction; an insulating material is filled between the first stacking areas;

Etching the sacrificial layer of the second stacking area and part of the first stacking area along the first direction to form a first multi-layer void; the semiconductor layer of the second stacking area is used to form a multi-layer void. A stacked bit line structure;

Filling the portion of the first multi-layer gap located in the first stacking region to form a first isolation layer;

forming an opening perpendicular to the surface of the stacked structure in the insulating material adjacent to the first stacking region;

Etch the first isolation layer from the opening to remove at least part of the first isolation layer;

forming a word line structure extending in a direction perpendicular to the surface of the stacked structure at the opening;

A plurality of stacked memory structures are formed in the first stacking area.
The method of claim 1, wherein an etching selectivity ratio of the sacrificial layer material used for the sacrificial layer and the semiconductor material used for the semiconductor layer is greater than or equal to the first preset value.
The method of claim 2, wherein the sacrificial layer material is silicon germanium (SiGe), and the semiconductor material is silicon Si.
The method of claim 1, wherein filling a portion of the first multi-layer void located in the first stacking region to form a first isolation layer includes:

Along the first direction, the first isolation material, the second isolation material and the first isolation material are sequentially filled into the first multi-layer gap to form the first isolation layer; wherein, the first isolation layer A length of a layer along the first direction is greater than or equal to a length of the first multi-layer void within the first stacking region.
The method of claim 4, wherein an etching selectivity ratio of the second isolation material to the first isolation material is greater than or equal to a second preset value.
The method of claim 4, wherein the first isolation material, the second isolation material and the first isolation material are sequentially filled into the first multi-layer void to form the first isolation layer, including :

Filling the first multi-layer void with a first isolation material;

Etching the first isolation material and retaining a portion of the first isolation material located in the first stacking region;

Filling the first multi-layer gaps with a second insulating material;

Etching the second isolation material, and retaining a portion of the second isolation material located in the first stacking region; wherein, along the first direction, the length of the remaining second isolation material is a predetermined gate pole length;

Filling the first multi-layer void with the first isolation material again;

The first isolation material is etched, and the first isolation material located in a portion of the first stacking region and located outside the second isolation material is retained.
The method of claim 6, wherein etching the first isolation layer from the opening to remove at least part of the first isolation layer includes:

The first isolation layer is etched from the opening to remove the second isolation material in the first isolation layer.
The method of claim 1, wherein forming a word line structure extending in a direction perpendicular to a surface of the stacked structure at the opening includes:

Form a gate oxide layer on the surface of each layer of the semiconductor layer in the opening;

Cover the surface of the gate oxide layer with a first conductive material as a gate conductive layer;

Fill the opening covered with the gate conductive layer with a second conductive material to form the word line structure.
The method of claim 1, wherein said providing a stacked structure consisting of semiconductor layers and sacrificial layers alternately stacked includes:

provide a substrate;

Stack semiconductor materials and sacrificial layer materials alternately on the substrate;

Etch the stacked semiconductor material and sacrificial layer material along the first direction to form a plurality of first stacking regions extending along the first direction, and a first stacking region connected to the plurality of first stacking regions. One end, and the second stacking area extending along the second direction; the area outside the stacking structure is a groove formed by etching;

The insulating material is filled in the groove formed after etching.
The method according to claim 9, wherein the method further comprises:

At a second end of the first stacking area away from the second stacking area, etching the insulating material to form a groove between adjacent first stacking areas;

Filling the slot with isolation material;

Remove the insulating material on a side of the second end away from the first end, and etch part of the sacrificial layer in the first stacking region from the second end in a first direction to form a second multi-layer void ;

The isolation material is filled in the second end of the first stacking region where part of the sacrificial layer is etched away to form a support structure.
The method of claim 10, wherein forming a plurality of stacked memory structures in the first stacking area includes:

removing the insulating material between the first stacking regions;

Removing the sacrificial layer in the first stacking area to leave each semiconductor layer suspended;

Perform metal silicide treatment on the surface of the semiconductor layer;

The surface of the semiconductor layer after metal silicide treatment is covered with a first metal material to form a lower electrode of the capacitor structure;

Cover the surface of the lower electrode with a dielectric layer;

Cover the surface of the dielectric layer with a third metal material to form an upper electrode of the capacitor structure;

Polysilicon material is filled in the gaps between adjacent semiconductor layers where the upper electrode is formed and in the grooves between the first stacking regions.
The method of claim 11 , wherein after forming the stacked plurality of capacitor structures, the method further includes:

Removing the isolation material at the second end of the first stacking region, and simultaneously removing at least a portion of the first isolation layer on a side of the capacitor structure close to the first end, to form grooves at both ends of the capacitor structure;

The trench is filled with an insulating material.
The method of claim 1, wherein after forming the first isolation layer, the method further includes:

Performing metal silicide treatment on the semiconductor layer not covered by the first isolation layer in the second stacking region along a second direction;

Cover the surface of the semiconductor layer with a second metal material;

Etch the second metal material at the connection between each layer of the semiconductor layer along a third direction to separate the second metal materials covered by each layer of the semiconductor layer from each other; the third direction is perpendicular to the The first direction and the second direction;

An insulating material is filled between each layer of the semiconductor layer covered with the second metal material and on the side of the second stacking area away from the first stacking area; wherein each layer is covered with the semiconductor layer of the second metal material. is the bit line structure.
The method of claim 13, wherein the method further includes:

Process the bit line structure to form a step structure whose length decreases from bottom to top;

A bit line lead-out structure is formed on the step structure of each layer.
A semiconductor structure formed by the method of any one of claims 1 to 14.
A memory consisting of:

A semiconductor structure formed by the method of any one of claims 1 to 14.