KR102623393B1 - Light emitting display apparatus - Google Patents

Abstract

The purpose of the present invention is to determine the level of the panel voltage supplied to the light emitting display panel during the blank period when internal compensation is not performed. The aim is to provide a light emitting display device that can be controlled to be equal to or similar to the level of the panel voltage supplied to the light emitting display panel during the active period in which internal compensation is performed.

Description

Light emitting display device {LIGHT EMITTING DISPLAY APPARATUS}

The present invention relates to a light emitting display device.

In a light emitting display device, the current flowing through the light emitting element of each pixel may change due to variations in threshold voltages of driving transistors caused by process variations, etc. In order to solve defects caused by the above deviation, internal compensation is performed in light emitting display devices to compensate for the threshold voltage of the driving transistor.

Internal compensation can be performed through an initialization process, a sampling process, and a light emission process, and an initialization voltage, etc. is supplied to the light emitting display panel.

Additionally, in a light emitting display device, the brightness difference between gray levels may not be clear, and in particular, the brightness difference between low gray levels may not be clear. Therefore, in light emitting display devices, a method of correcting the difference in brightness between low gray levels is used using the duty ratio of an emission signal that controls the output of light.

However, in a method for changing the duty ratio of an emission signal and a conventional light emitting display device using internal compensation, the level of the initialization voltage may be changed in the active period in which internal compensation is performed and the blank period in which internal compensation is not performed. there is. Accordingly, in a conventional light emitting display device, stripes in the form of horizontal strips may be generated depending on the luminance difference in each area of the light emitting display panel.

Additionally, in a conventional light emitting display device, horizontal stripes may be generated due to a difference in the level of the driving voltage supplied to the top of the light emitting display panel and the level of the driving voltage supplied to the bottom of the light emitting display panel.

The purpose of the present invention proposed to solve the above-mentioned problems is to change the level of the panel voltage supplied to the light emitting display panel during the blank period when internal compensation is not performed. The aim is to provide a light emitting display device that can be controlled to be equal to or similar to the level of the panel voltage supplied to the light emitting display panel during the active period in which internal compensation is performed.

A light emitting display device according to the present invention for achieving the above-described technical problem includes a display panel including pixels for displaying an image, gate lines and data lines connected to the pixels, and a panel voltage supply provided in the display panel. During the active period when internal compensation is performed to compensate for changes in the threshold voltage or mobility of the voltage supply unit that supplies the panel voltage to the line and the driving transistors provided in the pixels, the panel voltage supplied to the panel voltage supply line is and a control unit that detects a change amount and controls the voltage supply unit to output a panel voltage having a corrected panel voltage corresponding to the change amount during a blank period of the display panel.

According to the present invention, the level of the panel voltage supplied to the light emitting display panel during the blank period in which internal compensation is not performed can be controlled to be the same or similar to the level of the panel voltage supplied to the light emitting display panel in the active period in which internal compensation is performed. You can.

Therefore, according to the present invention, luminance deviation is not generated due to the difference between the panel voltage in the active period and the panel voltage in the blank period, and accordingly, horizontal stripes are not generated due to the luminance deviation.

1 is an exemplary diagram showing the configuration of a light emitting display device according to the present invention.
Figure 2 is an exemplary diagram showing the configuration of a control unit applied to the light emitting display device according to the present invention.
Figure 3 is an exemplary diagram showing the structure of a pixel provided in a light-emitting display device according to the present invention.
Figure 4 is an example diagram showing the waveforms of gate signals and emission signals applied to the light emitting display device according to the present invention.
Figure 5 is an example diagram showing the waveforms of emission signals applied to the light emitting display device according to the present invention.
Figure 6 is an exemplary diagram showing the waveform of the initialization voltage applied to the light emitting display device according to the present invention.
Figure 7 is an exemplary diagram showing the configuration of an initialization voltage generator applied to the light emitting display device according to the present invention.
Figure 8 is another example diagram showing the configuration of an initialization voltage generator applied to the light emitting display device according to the present invention.
Figure 9 is an exemplary diagram showing the configuration of a driving voltage generator applied to the light emitting display device according to the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. These embodiments only serve to ensure that the disclosure of the present invention is complete, and those skilled in the art It is provided to fully inform the person of the scope of the invention, and the present invention is only defined by the scope of the claims.

In this specification, it should be noted that when adding reference numbers to components in each drawing, the same components are given the same number as much as possible even if they are shown in different drawings.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship of two parts is described as 'on top', 'on the top', 'on the bottom', 'next to', etc., 'immediately' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the case of a description of a temporal relationship, for example, if a temporal relationship is described as 'after', 'successfully after', 'after', 'before', etc., 'immediately' or 'directly' Unless used, non-consecutive cases may also be included.

The term ‘at least one’ should be understood to include all possible combinations from one or more related items. For example, 'at least one of the first item, the second item and the third item' means each of the first item, the second item or the third item, as well as two of the first item, the second item and the third item. It means a combination of all items that can be presented from more than one.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be partially or fully combined or combined with each other, various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

1 is an exemplary diagram showing the configuration of a light emitting display device according to the present invention.

The light emitting display device according to the present invention can constitute an electronic device. The electronic device may be, for example, a smartphone, tablet PC, television, monitor, etc.

As shown in FIG. 1, the light emitting display device according to the present invention includes pixels 110 on which images are displayed, gate lines (GL1 to GLg) and data lines (DL1 to DL1) connected to the pixels 110. DLd), a voltage supply unit 500 that supplies panel voltage to a panel voltage supply line (PVL) provided in the display panel, and driving transistors provided in the pixels 110. During the active period when internal compensation for compensating voltage deviation is performed, the amount of change in the panel voltage supplied to the panel voltage supply line (PVL) is detected, and during the blank period when the internal compensation is not performed, the correction panel corresponding to the amount of change is detected. A control unit 400 that controls the voltage supply unit 500 to output a panel voltage having a voltage, a gate driver 200 that supplies gate signals to the gate lines (GL1 to GLg), and the data lines (DL1 to GLg). It includes a data driver 300 that supplies data voltages to DLd). That is, the control unit 400 controls the amount of change in the panel voltage supplied to the panel voltage supply line during the active period when internal compensation is performed to compensate for changes in the threshold voltage or mobility of the driving transistors provided in the pixels. , and controls the voltage supply unit to output a panel voltage having a corrected panel voltage corresponding to the change amount during a blank period of the display panel.

In the display area AA of the light emitting display panel 100, pixels 110 including a light emitting device and a pixel driving circuit that drives the light emitting device are provided. Additionally, signal lines are formed in the light emitting display panel 100 to define a pixel area where the pixels 110 are formed and to supply signals to the pixel driving circuit. The signal lines include various types of lines in addition to the gate lines (GL1 to GLg) and the data lines (DL1 to DLd). The pixel driving circuit is explained with reference to FIG. 3.

The gate driver 200 may be configured as an integrated circuit and then mounted in the non-display area (NAA), or may be directly embedded in the non-display area (NAA). The gate driver 200 may perform the function of supplying emission signals to emission transistors provided in the pixels 110. Additionally, the gate driver 200 may perform a function of supplying gate signals to gate lines provided in the pixels 110.

The light emitting display device according to the present invention may include an emission driver. The emission driver may perform a function of supplying emission signals to emission transistors provided in the pixels 110 through the emission line EL. In this case, the emission driver may be implemented by being built into the gate driver 200, or may be implemented independently of the gate driver 200.

The data driver 300 may be provided on a chip-on-film attached to the light-emitting display panel 100. The chip-on-film is also connected to the main board on which the control unit 400 is provided. In this case, the chip-on-film is provided with lines that electrically connect the control unit 400, the data driver 300, and the light emitting display panel 100. To this end, the lines are connected to the main board and the light emitting display panel 100. It is electrically connected to pads provided on the light emitting display panel 100. The main board may be electrically connected to an external board on which the external system is mounted. However, the data driver 300 may be directly mounted on the light emitting display panel 100 and then electrically connected to the main board.

The external system performs the function of driving the control unit 400 and the electronic device. That is, when the electronic device is a smartphone, the external system performs various types of audio information, video information, and text information through a wireless communication network, and transmits the video information to the control unit 400.

The voltage supply unit 500 supplies panel voltage to a panel voltage supply line provided in the non-display area (NAA) of the display panel 100. The panel voltage is a driving voltage (Vdd) supplied to the driving transistor so that current can be supplied to the light-emitting device connected to the driving transistor provided in the pixel 110, or, when performing the internal compensation, the pixel ( 110) may be an initialization voltage (Vref) for initializing the voltage.

To this end, the voltage supply unit 500 includes an initialization voltage generator 510 that generates the initialization voltage (Vref) and a driving voltage generator 520 that generates the driving voltage (Vdd).

The panel voltage supply line connected to the initialization voltage generator 510 supplies an initialization voltage (Vref) to the pixels 110 provided in the light emitting display panel 110.

Additionally, the panel voltage supply line connected to the driving voltage generator 520 supplies the driving voltage (Vdd) to the pixels 110 provided in the light emitting display panel 110.

The panel voltage supply line that supplies the initialization voltage (Vref) is also connected to the control unit 400. Accordingly, the same voltage as the initialization voltage (Vref) supplied to the pixels 110 may also be transmitted to the control unit 400.

Additionally, the panel voltage supply line that supplies the driving voltage (Vdd) may also be connected to the control unit 400. That is, in the present invention, at least one of the initialization voltage (Vref) and the driving voltage (Vdd) may be transmitted to the control unit 400.

Therefore, in the following description, in cases where there is no need to distinguish between the initialization voltage (Vref) and the driving voltage (Vdd), the initialization voltage (Vref) and the driving voltage (Vdd) are referred to as panel voltage (PV). do. In this case, a line provided in the light emitting display panel 100 to supply the initialization voltage (Vref) or the driving voltage (Vdd) to the pixels 110 is called a panel voltage supply line (PVL).

That is, the initialization voltage (Vref) or the driving voltage (Vdd) may be supplied to the panel voltage supply line (PVL) shown in FIG. 1. In addition, the non-display area (NAA) may be provided with both a panel voltage supply line (PVL) for supplying the initialization voltage (Vref) and a panel voltage supply line (PVL) for supplying the driving voltage (Vdd). there is.

The internal compensation means that even if the threshold voltage or mobility of the driving transistor changes due to deterioration of the driving transistor, the current supplied to the light emitting device is not affected by the change in the threshold voltage or the change in mobility. This refers to a method of controlling the voltage of the gate of the driving transistor during the period when an image is displayed, that is, the active period.

The specific structures of the initialization voltage generator 510 and the driving voltage generator 520 are described below with reference to FIGS. 7 to 9 .

The control unit 400 provides a gate control signal (GCS) for controlling the operation of the gate driver 200 and data for controlling the operation of the data driver 300 based on a timing synchronization signal input from an external system. Each control signal (DCS) is generated.

During an active period in which internal compensation is performed to compensate for voltage deviations of the driving transistors provided in the pixels 110, the control unit 400 controls the amount of change in the panel voltage supplied to the panel voltage supply line (PVL). can be detected. The control unit 400 may control the voltage supply unit 500 to output a panel voltage having a corrected panel voltage corresponding to the change amount during a blank period in which the internal compensation is not performed. For this purpose, as described above, the initialization voltage (Vref) or the driving voltage (Vdd) may be supplied to the control unit 400. The specific configuration and function of the control unit 400 will be described with reference to FIG. 2.

Figure 2 is an exemplary diagram showing the configuration of a control unit applied to the light emitting display device according to the present invention.

The control unit 400 uses a timing synchronization signal (TSS) transmitted from an external system to rearrange the input image data (Ri, Gi, Bi) transmitted from the external system using the external compensation value, and rearranges the input image data (Ri, Gi, Bi) transmitted from the external system. A data alignment unit 430 that supplies the image data (Data) to the data driver 300, and a control for generating the gate control signal (GCS) and the data control signal (DCS) using the timing synchronization signal. A signal generator 420, a detection unit 410 that analyzes the panel voltage (PV) transmitted from the panel voltage supply line (PVL) to detect the amount of change in the panel voltage and controls the control signal generator according to the change amount, A storage unit 450 for storing the change in the panel voltage and for outputting the image data and various control signals (DCS, GCS) to the data driver 300 or the gate driver 200. Includes an output unit 440.

The control unit 400 controls the panel voltage supplied to the panel voltage supply line PVL ( PV) is detected, and during a blank period when the internal compensation is not performed, the voltage supply unit 500 is controlled to output a panel voltage having a corrected panel voltage corresponding to the change. That is, the control unit 400 controls the amount of change in the panel voltage supplied to the panel voltage supply line during the active period when internal compensation is performed to compensate for changes in the threshold voltage or mobility of the driving transistors provided in the pixels. , and controls the voltage supply unit to output a panel voltage having a corrected panel voltage corresponding to the change amount during a blank period of the display panel.

To this end, the detection unit 410 analyzes the panel voltage (PV) transmitted from the panel voltage supply line (PVL) to detect the amount of change in the panel voltage (PV), and the control signal generator 420 according to the change amount. ) is controlled.

The storage unit 450 may store panel voltage information including the amount of change in the panel voltage (PV). The panel voltage information includes, for example, the change amount, level, change timing of the panel voltage (PV), the level of the corrected panel voltage according to the change amount, a control signal for controlling the control signal generator 420, etc. may be included.

The detector 410 controls the control signal generator 420 so that a corrected panel voltage corresponding to the panel voltage information can be generated.

The control signal generation unit 420 may generate a voltage control signal (VCS) for controlling the voltage supply unit 500 according to the control of the detection unit 410.

The panel voltage information may be generated during manufacturing of the light emitting display device according to the present invention and stored in the storage unit 450. For example, during manufacturing of the light emitting display device, the amount of change in the panel voltage (PV) can be determined through various tests and simulations, and accordingly, the panel voltage information is stored in the storage unit 450. It can be. When the light emitting display device according to the present invention is used by a user, the detection unit 410 can control the control signal generation unit 420 using the panel voltage information, and accordingly, the blank period (BP) ), the corrected panel voltage may be generated.

However, the panel voltage information may be stored in the storage unit 450 when used by a user after the light emitting display device according to the present invention is manufactured. That is, when the light emitting display device is used by a user, the detection unit 410 generates the panel voltage information using the panel voltage (PV) transmitted from the light emitting display panel 110, and then the storage unit It can be saved at (450). The detector 410 can control the control signal generator 420 using the panel voltage information, and accordingly, the voltage control signal (VCS) can be generated, and thus, the blank period (BP) ), the corrected panel voltage may be generated.

In the following description, an example in which the panel voltage information is generated and stored when the light emitting display device according to the present invention is manufactured and used by a user is explained as an example of the present invention. However, the present invention described below can be applied even when the panel voltage information is stored during manufacturing of the light emitting display device.

Figure 3 is an exemplary diagram showing the structure of a pixel provided in a light emitting display device according to the present invention.

In the display area (AA) of the light emitting display panel 100, pixels 110 including a light emitting element (ED) and a pixel driving circuit (PDC) that drive the light emitting element (ED) are provided. Additionally, signal lines are formed in the light emitting display panel 100 to define a pixel area where the pixels 110 are formed and to supply a driving signal to the pixel driving circuit (PDC).

The light emitting device may include any one of an organic light emitting layer, an inorganic light emitting layer, and a quantum dot light emitting layer, or may include a stacked or mixed structure of an organic light emitting layer (or inorganic light emitting layer) and a quantum dot light emitting layer. The light emitting element (ED) emits light by the data current supplied from the driving transistor (Tdr) and emits light with luminance corresponding to the data current.

The signal lines include a gate line (GL), a data line (DL), a driving voltage line (PLA), a voltage line (PLB), an emission line (EL), and an initialization voltage line (RVL).

The gate lines GL may be formed parallel to each other at regular intervals along the second direction of the light emitting display panel 100, for example, the horizontal direction. The pixel 110 may be provided with at least one gate line (GL). In FIG. 3, a pixel equipped with two gate lines, that is, an n-th gate line (GLn) and an n-1-th gate line (GLn-1), is shown as an example of the present invention. The n-1th gate signal (VSn-1) including the n-1th gate pulse is supplied to the n-1th gate line (GLn-1), and the n-th gate signal (VSn-1) is supplied to the n-th gate line (GLn-1). An n-th gate signal (VSn) including a gate pulse is supplied. The n-1th gate pulse refers to a gate pulse generated before the nth gate pulse.

Each of the gate signals VSn-1 and VSn includes a gate pulse and a gate off signal. The gate pulse refers to a signal that can turn on the first transistor (T1), the second transistor (T2), and the fifth transistor (T5) shown in FIG. 3, and the gate off signal refers to a signal that turns on the first transistor (T1). , refers to a signal that can turn off the second transistor (T2) and the fifth transistor (T5).

The emission line EL may be formed parallel to the gate lines. An emission signal (EM) is supplied to the emission line (EL). The emission signal EM is an emission pulse capable of turning on the third transistor T3 and the fourth transistor T4 connected to the emission line EL, and the third transistor T3 and the fourth transistor T4 are connected to the emission line EL. It includes an emission off signal that can turn off the transistor (T4).

The data line DL is arranged at regular intervals along the first direction of the light emitting display panel 100, for example, the vertical direction, so as to intersect the gate line GL and the emission line EL. can be formed.

The driving voltage line (PLA) may be formed at regular intervals parallel to the data line (DL). The driving voltage line (PLA) is connected to the driving voltage generator 520 provided in the voltage supply unit 500, and transmits the driving voltage (Vdd) supplied from the driving voltage generator 520 to the pixel 110. supply to. In particular, the driving voltage (Vdd) is supplied to the driving transistor (Tdr) so that current can be supplied to the light emitting element (ED) connected to the driving transistor (Tdr). The driving voltage line (PLA) may be connected to the panel voltage supply line (PVL) provided in the non-display area (NAA) of the light emitting display panel 100.

The voltage line (PLB) supplies the voltage (EVSS) supplied from the voltage supply unit 500 to each pixel 110.

The initialization voltage line RVL is connected to the initialization voltage generator 510 provided in the voltage supply unit 500, and the initialization voltage Vref supplied from the initialization voltage generator 520 is applied to the pixel 110. ) is supplied to. In particular, the initialization voltage Vref performs a function of initializing the pixel 110 when the internal compensation is performed. The initialization voltage line (RVL) may be connected to the panel voltage supply line (PVL) provided in the non-display area (NAA) of the light emitting display panel 100.

The pixel driving circuit (PDC) may include first to fifth transistors, a capacitor (C), and a driving transistor (Tdr) that controls the amount of current flowing through the light emitting device (ED).

The first terminal of the driving transistor (Tdr) is connected to the driving voltage line (PLA), and the second terminal is connected to the second terminal of the second transistor (T2) and the first terminal of the fourth transistor (T4). The gate is connected to the second terminal of the capacitor C and the first terminal of the second transistor T2.

The first terminal of the first transistor T1 is connected to the data line DL, the second terminal is connected to the first terminal of the capacitor C, and the gate is connected to the nth gate line GLn. connected.

The first terminal of the second transistor (T2) is connected to the gate of the driving transistor (Tdr), the second terminal is connected to the second terminal of the driving transistor (Tdr), and the gate is connected to the n-1th gate. Connected to line (GLn-1).

The first terminal of the third transistor T3 is connected to the second terminal of the first transistor T1, the second terminal is connected to the initialization voltage line RVL, and the gate is connected to the emission line EL. ) is connected to.

The first terminal of the fourth transistor T4 is connected to the second terminal of the driving transistor Tdr, and the second terminal is connected to the second terminal of the fifth transistor T5 and the light emitting device ED. And the gate is connected to the emission line (EL).

The first terminal of the fifth transistor T5 is connected to the second terminal of the third transistor T3 and the initialization voltage line RVL, and the second terminal is connected to the second terminal of the fourth transistor T4. and the light emitting device (ED), and its gate is connected to the n-1th gate line (GLn-1).

The first terminal of the capacitor C is connected to the second terminal of the first transistor T1 and the first terminal of the third transistor T3, and the second terminal is connected to the gate and the third terminal of the driving transistor Tdr. It is connected to the first terminal of the second transistor (T2).

The structure of the pixel driving circuit (PDC) may be formed in various structures other than the structure shown in FIG. 3. In this case, in the pixel driving circuit (PDC), as will be described below, in the initialization section, a short circuit occurs between the initialization voltage line (RVL) and the driving voltage line (PLA), and the initialization voltage (Vref) is short-circuited. can rise. Additionally, in the pixel driving circuit (PDC), a short circuit as described above may occur even in a section other than the initialization section, causing the initialization voltage (Vref) to increase.

That is, the pixel driving circuit (PDC) applied to the present invention can be changed to various structures other than the structure shown in FIG. 3. In this case, while internal compensation is performed in the pixel driving circuit (PDC), A short circuit occurs between the initialization voltage line (RVL) and the driving voltage line (PLA), thereby increasing the initialization voltage (Vref).

Hereinafter, a basic driving method of a light emitting display device according to the present invention will be described with reference to FIGS. 1 to 6.

Figure 4 is an example diagram showing the waveforms of gate signals and emission signals applied to the light emitting display device according to the present invention, and Figure 5 is an example diagram showing the waveforms of emission signals applied to the light emitting display device according to the present invention. 6 is an exemplary diagram showing the waveform of the initialization voltage applied to the light emitting display device according to the present invention.

The pixel 110 applied to the present invention may include a pixel driving circuit (PDC) as shown in FIG. 3. In the light emitting display device according to the present invention, internal compensation is performed. The internal compensation may include an initialization period (P1), a sampling period (P2), a holding period (P3), and a light emission period (P4). In particular, Figure 3 shows a method of operating the pixel 110 in the initialization period (P1).

For example, one frame period of the light emitting display device according to the present invention includes an initialization period (P1) that initializes the gate of the driving transistor (Tdr), and a characteristic value (e.g., threshold voltage) of the driving transistor (Tdr). and a sampling section (P2) that stores the data voltage (Vdata), a holding section (P3) that continues the sampling section, and a light emitting section (P4) that causes the light emitting element (ED) to emit light according to the current corresponding to the data voltage. It can be included.

In this case, in the light emission section P4, the light emitting element ED repeats light emission and extinguishment by the emission signal. That is, in the present invention, a method of correcting the brightness difference between low gray levels using the duty ratio of the emission signal is used.

For example, in order for a light emitting display device to display low brightness, the current flowing through the light emitting element (ED) must be reduced. However, it is difficult to finely control the current flowing through the light emitting device (ED) through the driving transistor (Tdr). Therefore, the lower the luminance, the greater the difference between each pixel, and dark stripes may appear in the image. In particular, as the current flowing through the light emitting device ED decreases, the luminance deviation may further increase.

To overcome this, the light emitting display device according to the present invention uses a duty driving method of an emission signal (EM) to turn the light emitting device on or off, instead of reducing the amount of current flowing through the light emitting device. The time can be adjusted, and accordingly, the brightness of the light emitting device can be adjusted.

To elaborate, for example, in the present invention, a data voltage twice as high as the data voltage corresponding to the gray level of the image to be expressed is supplied to the pixel, and the emission signal includes at least two emission pulses in one frame period. (EMP) is output.

The light emitting device (ED) starts to emit light by the first emission pulse (ELP), the light emitting device (ED) is turned off by the emission off signal (EMO), and then the light emitting device (ED) starts to emit light by the second emission pulse (EMP). By this, the light emitting element (ED) starts emitting light again.

That is, a data voltage twice as high was supplied to the pixel, but since the light emitting element was turned off once and then emitted again, the brightness of the pixel in one frame period was 1/2 of the data voltage actually supplied to the pixel. It can correspond to the brightness when voltage is supplied. This method can be useful for correcting or clarifying brightness differences between low gray levels.

Therefore, as described above, the present invention uses a method of correcting the brightness difference between low gray levels using the duty ratio of the emission signal. In Figure 5, a light emitting display device in which two emission pulses are supplied to one emission line (EL) in one frame period is shown as an example of the present invention. Therefore, below, as shown in FIG. 5, a light emitting display device in which two emission pulses are supplied to one emission line EL in one frame period will be described as an example of the present invention.

First, as shown in FIG. 4, in the initialization period (P1), the n-1th gate signal (VSn-1) having a low level is transmitted to the n-1th gate line (GL(n-1)). The n-th gate signal (VSn) having a high level is supplied to the n-th gate line (GLn), and the emission signal (EM) having a low level is supplied to the emission line (EL). Accordingly, the second transistor (T2), the third transistor (T3), the fourth transistor (T4), and the fifth transistor (T5) are turned on.

In this case, the initialization voltage (Vref) is supplied to the first terminal of the capacitor (C) and the light emitting element (ED), and the initialization voltage (Vref) is also supplied to the gate of the driving transistor (Tdr). Accordingly, the first and second terminals of the capacitor C may be initialized by the initialization voltage Vref.

However, in the initialization period P1, the driving transistor Tdr may be turned on due to the initialization voltage Vref or another voltage. In this case, because the fourth transistor (T4) and the fifth transistor (T5) are turned on, the driving voltage (Vdd) and the initialization voltage (Vref) are shorted in the pixel 110, and the initialization voltage (Vref) may rise momentarily. Accordingly, the first and second terminals of the capacitor C and the gate of the driving transistor Tdr may be initialized by the instantaneously increased initialization voltage Vref.

Next, in the sampling period (P2), the n-1th gate signal (VSn-1) having a low level is supplied to the n-1th gate line (GL(n-1)), and the n-th gate signal (VSn-1) is supplied to the n-1th gate line (GL(n-1)). The nth gate signal (VSn) having a low level is supplied to (GLn), and the emission signal (EM) having a high level is supplied to the emission line (EL). Accordingly, the second transistor (T2), the first transistor (T1), the fifth transistor (T5), and the driving transistor (Tdr) are turned on.

In this case, the data voltage supplied through the data line (DL) is charged to the first terminal of the capacitor (C), and the voltage (Vdd) supplied through the driving transistor (Tdr) and the second transistor (T2) -Vth) is charged to the second terminal of the capacitor C, that is, the gate of the driving transistor Tdr.

Accordingly, the gate of the driving transistor (Tdr) becomes a differential voltage (=Vdd - Vth) obtained by subtracting the threshold voltage (Vth) of the driving transistor (Tdr) from the data voltage (Vdata).

Next, after the sampling period (P2), the holding period (P3) may be performed. The holding period P3 is a period for adjusting the emission timing of the n-1th gate line GLn-1, the nth gate line GLn, and other gate lines. In the holding period (P3), signals having a high level are supplied to the n-1th gate line (GLn-1), the nth gate line (GLn), and the emission line (EL). Accordingly, the state of the sampling period (P2) can be maintained in the maintenance period (P3).

Finally, in the light emission period (P4), the n-1th gate signal (VSn-1) having a high level is supplied to the n-1th gate line (GL(n-1)), and the n-th gate signal (VSn-1) is supplied to the light emission section (P4). The nth gate signal VSn having a high level is supplied to the line GLn, and the emission signal EM having a low level is supplied to the emission line EL. Accordingly, the third transistor (T3) and the fourth transistor (T4) are turned on. Accordingly, the initialization voltage (Vref) is supplied to the first terminal of the capacitor (C), and the current (I _OLED ) is supplied to the light emitting device (ED) through the fourth transistor (T4).

In this case, the current (I _OLED ) supplied to the light emitting device (ED) is proportional to the square of the difference voltage between the gate-source voltage (Vgs) of the driving transistor (Tdr) and the threshold voltage (Vth).

In the light emission period P4, the gate voltage of the driving transistor Tdr, that is, the voltage of the first node n1 shown in FIG. 3 is the sum of the driving voltage Vdd and the initialization voltage Vref. , is the difference voltage (= Vdd + Vref - Vth - Vdata) obtained by subtracting the threshold voltage (Vth) and the data voltage (Vdata).

In this case, the source voltage of the driving transistor (Tdr) is the driving voltage (Vdd) supplied through the driving voltage line (PLA).

Therefore, the difference voltage between the gate-source voltage (Vgs) of the driving transistor (Tdr) and the threshold voltage (Vth) is equal to [Equation 1]. That is, as described above, in the light emission period P4, the source voltage (Vs) is the driving voltage (Vdd), and the gate voltage (Vg) is Vdd - Vth - (Vdata - Vref) (= Vdd + Vdata - Vth - Vdata), so the current flowing to the light emitting device (ED) in the light emitting section (P4) is equal to [Equation 1]. In [Equation 1], the remaining values excluding the source voltage (Vs), the gate voltage (Vg), the data voltage (Vdata), the initialization voltage (Vref), and the driving voltage (Vdd) are the current ( These can be various constants or variables used in the calculation of I _OLED ).

As described in [Equation 1], according to the present invention, the current (I _OLED ) supplied to the light emitting device (ED) is unrelated to the threshold voltage (Vth) of the driving transistor (Tdr), and the data voltage (Vdata) and the initialization voltage (Vref).

Therefore, according to the present invention, even if the driving transistor (Tdr) is deteriorated and the threshold voltage (Vth) of the driving transistor (Tdr) changes, the current (I _OLED ) supplied to the light emitting device (ED) is equal to the threshold voltage. It is not affected by changes in (Vth). Accordingly, according to the present invention, the current (I _OLED ) can be controlled only by the data voltage (Vdata), regardless of the amount of change in the threshold voltage of the driving transistor (Tdr).

After the emission period (P4), in the active period, the emission signal (EM) may change from low level to high level and then again from high level to low level, as shown in FIG. 5, Accordingly, light may be blocked from the pixels and then output again.

That is, as described above, the present invention uses a method of correcting the brightness difference between low gray levels using the duty ratio of the emission signal.

In this case, for example, as shown in FIGS. 1 and 5, in the pixels provided in the middle area (M) and the bottom area (L) of the display panel 100, the emission signal (EM) Periods in which light is changed to a low level and light is output may be included in the blank period BP, and pixels provided in the remaining portion of the display panel 100 (hereinafter simply referred to as the normal area N) In , periods in which the emission signal (EM) is converted to a low level and light is output may be included only in the active period (AP).

As described above, when the internal compensation is performed, especially when the initialization process (P1) is performed, the driving voltage (Vdd) and the initialization voltage (Vref) are shorted in the pixel 110. , as shown in FIG. 6, a phenomenon occurs in which the initialization voltage (Vref) is instantaneously increased. That is, since the initialization voltage (Vref) is generally smaller than the driving voltage (Vdd), the initialization voltage (Vref) may be momentarily increased due to a short circuit as described above.

The phenomenon in which the driving voltage and the initialization voltage (Vdd) are short-circuited and the initialization voltage (Vref) rises instantaneously occurs when the internal compensation is performed. Therefore, in the active period (AP), the phenomenon continues. occurs.

Accordingly, the characteristics of the initialization voltage (Vref) when the internal compensation is performed in the pixel and light is generated, and the emission signal is converted to a high level and then converted to a low level after the internal compensation is performed, thereby producing light. When this occurs again, the characteristics of the initialization voltage (Vref) may remain the same.

That is, during the active period (AP), when internal compensation is performed on pixels connected to one emission line (EL), the characteristics of the initialization voltage (Vref) are similar to those of the other emission line (EL). The characteristics of the initialization voltage (Vref) are the same as those when internal compensation is performed on connected pixels.

In further detail, the initialization voltage Vref is equally supplied to all pixels provided in the light emitting display panel 100. Therefore, when the internal compensation is performed on one pixel, if the characteristics of the initialization voltage (Vref) are changed due to the short circuit as described above, the changed characteristics are applied to all pixels provided in the light emitting display panel 100. It is also reflected in the field.

Therefore, even when the light emitting device (ED) repeats the operation of outputting or not outputting light by converting the emission signal (EM) in the active period (AP), the changed characteristics of the initialization voltage (Vref) can be continuously reflected in the light emitting device (ED).

Accordingly, in the active period (AP), the light emitting elements (ED) provided in the light emitting display panel 100 may emit light by the initialization voltage (Vref) as shown in FIG. 6.

In particular, as described in [Equation 1], the current (I _OLED ) flowing to the light emitting device (ED) may vary depending on the initialization voltage (Vref), so the amount of change in the initialization voltage (Vref) is the amount of change in the light emission. It is closely related to the quality of the image output from the display panel 100.

However, as described above, in the pixels provided in the middle area (M) and the bottom area (L) of the display panel 100, the emission signal (EM) is changed to a low level, thereby causing light These output periods may be included in the blank period (BP).

For example, as shown in FIG. 5, when pixels provided in the middle area (M) start emitting light in the active period (AP), the initialization voltage (Vref) in the active period (AP) This can be applied to the pixels. However, the timing at which the output of light is blocked due to a change in the emission signal and then the light is output again may be included in the blank period BP.

In this case, since the internal compensation is not performed in the blank period BP, the initialization voltage Vref and the driving voltage Vdd do not short-circuit. Therefore, the phenomenon in which the initialization voltage (Vref) increases instantaneously as shown in FIG. 6 does not occur.

Therefore, the voltage level of the initialization voltage (Vref) when light is output in the blank period (BP) is the voltage level (Vref_H) of the initialization voltage (Vref) when light is output in the active period (AP) ) is different from

In particular, as shown in FIG. 5, in the pixels provided in the lower area (L), light is output from the light emitting element (ED) by the g-th emission signal (EM) in the active period (AP). In this case, the initialization voltage (Vref) in the active period (AP) may be applied. However, immediately after the light emitting device ED starts emitting light, the blank period BP begins. Therefore, the initialization voltage (Vref) applied to the light emission of the pixels provided in the lower region (L) is the initialization voltage (Vref_H) applied to the pixels provided in the normal region (N) in the active period (BP) becomes different.

In this case, the voltage level of the initialization voltage (Vref) in the blank period (BP) may be different from the level of the initialization voltage (Vref) in the active period (AP), and in particular, may be smaller.

Therefore, when the pixel outputs light in the blank period (BP) and the active period (AP) by the same data voltage, the brightness of the light output in the blank period (BP) is It may be smaller than the brightness of the output light.

Accordingly, in the middle area (M) and the bottom area (L) of the light emitting display panel 100, stripes in the form of horizontal strips that appear as the brightness of light is reduced may be generated.

To solve this problem, the light emitting display device according to the present invention changes the voltage level of the initialization voltage (Vref) in the blank period (BP) to the voltage level of the initialization voltage (Vref) in the active period (AP). It performs the function of changing it to a form similar to the level.

In the above, an example in which horizontal stripes are generated in a light emitting display panel due to a brightness deviation due to a change in the initialization voltage (Vref) has been described.

However, horizontal stripes that are darker than other parts may be generated not only by the initialization voltage (Vref) but also by the driving voltage (Vdd).

For example, as shown in FIG. 1, the driving voltage (Vdd) is input from the bottom of the light emitting display panel 100 and is supplied through the panel voltage supply line (PVL) and the driving voltage line (PLA). When supplied to the pixels, the level of the driving voltage (Vdd) applied to the pixels provided at the bottom of the light emitting display panel 100 is the level applied to the pixels provided at the top of the light emitting display panel 100. It may be different from the level of the driving voltage (Vdd).

That is, the longer the length of the panel voltage supply line (PVL) and the driving voltage line (PLA), the more the voltage drop occurs in the lines, and accordingly, the panel provided at the top of the light emitting display panel 100 The level of the driving voltage (Vdd) applied to the pixels may be lower than the level of the driving voltage (Vdd) applied to the pixels provided at the bottom of the light emitting display panel 100.

Accordingly, even if the same data voltages are supplied to the pixels, the brightness of the light output from the pixels provided at the top of the light emitting display panel may become darker, and thus, horizontal stripes may be generated.

According to the light emitting display device according to the present invention, defects caused by deviations not only in the initialization voltage (Vref) but also in the driving voltage (Vdd) can be prevented.

Additionally, in the light emitting display device, deviation of the driving voltage (Vdd) may occur not only due to the above-mentioned causes but also for other reasons.

For example, the driving voltage (Vdd) may change along with the initialization voltage (Vref) during the internal compensation, or for reasons independent of the initialization voltage (Vref) during the internal compensation, the initialization voltage It may change in a similar form to (Vref).

Therefore, in the following, the driving voltage (Vdd) is changed in a similar form to the initialization voltage (Vref), that is, the driving voltage (Vdd) is different from the active period (AP) and the blank period (BP). The case where the level changes and a luminance deviation occurs due to the driving voltage (Vdd) will be described as an example of the present invention.

A detailed description of this is provided below with reference to FIGS. 7 to 9.

FIG. 7 is an exemplary diagram showing the configuration of an initialization voltage generator applied to a light-emitting display device according to the present invention, and FIG. 8 is another exemplary diagram showing the configuration of an initialization voltage generator applied to a light-emitting display device according to the present invention. In the following description, content that is the same or similar to the content described above is omitted or simply described.

In the present invention, the control unit 400 detects the amount of change in the panel voltage (PV) supplied to the panel voltage supply line (PVL) during an active period (AP) in which internal compensation is performed, and the internal compensation is performed. During the blank period BP during which no operation is performed, the voltage supply unit 500 is controlled to output a panel voltage having a corrected panel voltage corresponding to the change amount.

As described above, the panel voltage (PV) is the driving voltage (Vdd) supplied to the driving transistor (Tdr) so that current can be supplied to the light emitting element (ED) connected to the driving transistor (Tdr). , may be an initialization voltage (Vref) for initializing pixels when performing the internal compensation.

After starting to emit light due to the internal compensation, the light emitting elements (EDs) provided in the pixels repeatedly emit light and turn off due to the emission signal during one frame period, as shown in FIG. 5. You can.

In this case, at least one of the light emitting elements provided in the pixels, for example, a pixel provided in the middle area (M), starts emitting light in the active period (AP) and then turns off by the emission signal. Then, light may be emitted again in the blank period (BP).

In addition, at least one of the light-emitting elements provided in the pixels, for example, a pixel provided in the lower area (L), starts emitting light by the internal compensation in the active period (AP), and then starts emitting light by the internal compensation in the active period (AP). The luminescence can be continued for a period (BP).

In this case, as described above, the panel voltage (PV) supplied to the light emitting display panel 100 in the active period (AP), in particular, the initialization voltage (Vref), is the blank period (AP). may be different from the initialization voltage (Vref) supplied to the light emitting display panel, and in particular, may be smaller.

For example, in the initialization section P1 among the sections in which the internal compensation is performed, as shown in FIG. 6, the initialization voltage having a first voltage value (Vref_H) is applied to the panel voltage supply line ( It can be supplied to the light emitting display panel through PCL). Among the sections in which the internal compensation is performed, in the sections (P2 to P3) excluding the initialization section (P1), the panel voltage has a second voltage value (Vref_L) smaller than the first voltage value (Vref_H), It may be supplied to the light emitting display panel through the panel voltage supply line.

In this case, only the panel voltage having the second voltage value (Vref_L) smaller than the first voltage value (Vref_H) can be supplied to the light emitting display panel during the blank period (BP).

Accordingly, a luminance difference may occur between pixels emitting light in the blank period BP and pixels emitting light in the active period AP.

To solve this problem, the present invention receives feedback from the panel voltage supplied to the light emitting display panel 100 during the active period (AP), and calculates the amount of change in the panel voltage supplied during the active period (AP). , the voltage supply unit 500 can be controlled so that the panel voltage corresponding to the change amount is output during the blank period BP.

That is, the panel voltage (PV) output from the voltage supply unit 500 during the blank period (BP) has a corrected panel voltage calculated according to the amount of change in the panel voltage.

In this case, the corrected panel voltage is the average value (Vref_av) of the panel voltage supplied to the light emitting display panel in the active period, or the maximum value (Vref_av) of the panel voltage supplied to the light emitting display panel in the active period ( It has a value that varies between a first voltage value (Vref_H)) and a minimum value (second voltage value (Vref_L)), or a waveform of the panel voltage supplied to the light emitting display panel during the active period and a waveform corresponding to the voltage. and voltage.

To elaborate, the corrected panel voltage has the form shown in FIG. 6, has the average value (Vref_av) shown in FIG. 6, or has the maximum value (first voltage value (Vref_H) shown in FIG. )) and may have values that swing between the minimum value (the second voltage value (Vref_L)).

In order to generate the corrected panel voltage as described above, the voltage supply unit 500 has a resistance value according to the voltage control signal (VCS) supplied from the control unit 400, as shown in FIGS. 7 and 8. It may include a variable resistance variable unit 512 and a voltage generator 511 that generates the corrected panel voltage using the resistance value. 7 and 8 particularly show the configuration of the initialization voltage generator 510 that generates the initialization voltage (Vref). Therefore, hereinafter, the configuration and function of the initialization voltage generator 510 will be described with reference to FIGS. 7 and 8.

The voltage generator 511 of the initialization voltage generator 510 includes a voltage generator 511a that amplifies or varies the input voltage Vin, and a reference voltage generated from the voltage generator 511a and the resistance variable portion. It includes a generator that generates the initialization voltage (Vref) using the resistance value generated at 512. In addition to the input voltage Vin, an amplifier driving voltage VINB for driving the voltage generator 511a may be input to the voltage generator 511a along with the input voltage Vin.

The generator may be variously equipped with at least one resistor and at least one capacitor in parallel or series, as shown in FIGS. 7 and 8. 7 and 8 show a generator including two resistors (R81, R82) and two capacitors (C81, C82) as an example of the present invention.

As shown in FIG. 8, the resistance variable unit 512 of the initialization voltage generator 510 is turned on or off according to the first voltage control signal VCS1 supplied from the control unit 400. 1 Resistance variable unit 512a, a second resistance variable unit 512b that is turned on or off according to the second voltage control signal VCS2 supplied from the control unit 400, and the first resistance variable unit 512a It may include a resistor (Rt) connected to the resistor (Rt) and a resistor (Rt) connected to the second resistance variable portion (512b).

For example, as shown in FIG. 7, only one voltage control signal (VCS) can be supplied to the resistance variable unit 512, and accordingly, the resistance variable unit 512 has one resistance value. can only be created.

However, as shown in FIG. 8, two voltage control signals (VCS1, VCS2) may be supplied to the resistance variable part 512, and accordingly, the resistance variable part 512 has two resistors. Values can be created. For example, the first resistance variable part 512a and the second resistance variable part 512b may be formed of a transistor, as shown in FIGS. 7 and 8, and the transistor responds to the voltage control signal. When turned on, a resistance value can be generated by a resistor connected to the transistor. In this case, when a plurality of transistors are provided, a plurality of resistance values may be generated as the transistors are turned on. In particular, whether the transistors are turned on can be set in various ways using the voltage control signal, and various resistance values can be generated accordingly.

Therefore, according to the resistance variable unit 512 shown in FIG. 7, one resistance value can be generated in the resistance variable unit 512, and the voltage generator 510 uses the resistance value to generate one resistance value. A corrected panel voltage can be generated.

However, according to the resistance variable part 512 shown in FIG. 8, three different resistance values can be generated in the resistance variable part 512, and the voltage generator 510 can generate the three resistance values. Various correction panel voltages can be generated using at least one of these.

In this case, if the voltage control signal (VCS) is not supplied to the resistance variable part 512, the resistance variable part 512 may not reach the generation of the initialization voltage (Vref).

For example, during the active period (AP), the voltage control signal (VCS) may not be received from the control unit 400, and in this case, the initialization voltage (Vref) is generated by the voltage generator 511. ) can be created.

However, during the blank period BP, the voltage control signal VCS may be received from the control unit 400, and accordingly, at least one resistance value may be generated in the resistance variable unit 512. , the voltage generator 511 may generate the corrected panel voltage using at least one resistance value.

To elaborate, the control unit 400 analyzes the initialization voltage (Vref) transmitted from the panel voltage supply line (PVL) in the active period (AP) and changes the initialization voltage (Vref) (Vref_H, Vref_L). , Vref_av) and controls the control signal generator 520 according to the change amount. The control signal generator 420 may generate the voltage control signal (VCS) according to the control and supply it to the voltage supply portion 500. The resistance variable unit 512, which receives the voltage control signal (VCS), generates a resistance value according to the voltage control signal (VCS), and the voltage generator 511 uses the resistance value to generate the blank. The correction panel voltage to be used in the period BP can be generated.

That is, the initialization voltage generator 510 may generate a correction panel voltage that is the same as or similar to the initialization voltage shown in FIG. 6, that is, a correction initialization voltage, according to the resistance value.

For example, the initialization voltage generator 510 uses the resistance value to generate a correction panel voltage (correction) corresponding to the average value (Vref_av) of the initialization voltage supplied to the light emitting display panel in the active period (AP). Initialization voltage) may be generated, or the maximum value (first voltage value (Vref_H)) and minimum value (second voltage value (Vref_L)) of the initialization voltage supplied to the light emitting display panel in the active period (AP) ), or a correction panel having a waveform and voltage corresponding to the waveform and voltage of the initialization voltage supplied to the light emitting display panel in the active period (AP). A voltage, that is, a correction panel voltage (correction initialization voltage) having the form shown in FIG. 6 may be generated.

In particular, as shown in FIG. 8, as the number of voltage control signals (VCS) supplied to the resistance variable part 512 increases, the resistance value that can be generated in the resistance variable part 512 will vary. Accordingly, the form and level of the correction panel voltage (correction initialization voltage) that can be generated by the initialization voltage generator 510 may vary. Accordingly, a panel voltage having the form shown in FIG. 6, that is, a corrected panel voltage (corrected initialization voltage) similar to the initialization voltage transmitted to the light emitting display panel in the active period (AP), can be generated.

Accordingly, the resistance variable unit 512 receives more voltage control signals (VCS) in addition to the first voltage control signal (VCS1) and the second voltage control signal (VCS2) and generates four or more resistance values. In order to do this, it can be changed into various forms other than the structure shown in FIGS. 7 and 8.

Figure 9 is an exemplary diagram showing the configuration of a driving voltage generator applied to the light emitting display device according to the present invention.

In the above, the structure and function of the initialization voltage generator 510 were described with reference to FIGS. 7 and 8, but the driving voltage generator 520 is also formed in various forms as shown in FIGS. 7 and 8. It can be.

That is, FIG. 9 shows the driving voltage generator 520 having a structure similar to the initialization voltage generator 510 shown in FIG. 8. For example, in Figure 9, the third resistance variable unit 522a is turned on or off according to the third voltage control signal VCS3 supplied from the control unit 400, and the fourth voltage supplied from the control unit 400. A fourth resistance variable unit 522b that is turned on or off according to the control signal VCS4, a resistor Rt connected to the third resistance variable unit 522a, and a resistor connected to the fourth resistance variable unit 522b ( A resistance variable portion 522 including Rt) is shown. The configuration and function of the voltage generator 521 provided in the driving voltage generator 520 may be the same as the configuration and function of the voltage generator 511 included in the initialization voltage generator 510.

Additionally, the configuration and function of the resistance variable portion 522 of the driving voltage generator 520 may also be the same as the configuration and function of the resistance variable portion 512 described in the initialization voltage generator 510. .

Accordingly, the driving voltage generator 520 can also be changed into various forms so as to be able to generate various types of corrected panel voltages, that is, corrected driving voltages.

Below, the features of the present invention described above are briefly summarized.

In the present invention, the control unit 400 uses at least one of timing synchronization signals, for example, a vertical synchronization signal or a data enable signal, to determine the timing at which the blank period (BP) starts during one frame period. It can be detected.

When the blank period (BP) starts, the control unit 400 adjusts the level of the panel voltage (initialization voltage (Vref) or driving voltage (Vdd)) supplied to the light emitting display panel 100 to the active period (BP). ) can be changed to a level similar to the level of the panel voltage supplied to the light emitting display panel 100.

To this end, the control unit 400 receives panel voltage supplied to the light emitting display panel 100 during the active period (AP) and calculates the average value of the panel voltage supplied during the active period (AP). In addition, the voltage supply unit 500 can be controlled so that the panel voltage having the average value is output during the blank period BP.

Accordingly, the difference between the level of the panel voltage in the active period (AP) and the level of the panel voltage in the blank period (BP) may be reduced, and thus, the level of the panel voltage in the active period (AP) and the blank period (BP) may be reduced. There is no luminance deviation due to the level difference of the panel voltage at (BP). Therefore, according to the present invention, dark patterns in the form of horizontal bands due to the luminance deviation as described above are not generated.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. The scope of the present invention is indicated by the claims described below rather than the detailed description above, and all changes or modified forms derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: light emitting display panel 200: gate driver
300: data driver 400: control unit
500: voltage supply unit

Claims (10)

A display panel including pixels on which images are displayed and gate lines and data lines connected to the pixels;
a voltage supply unit that supplies panel voltage to a panel voltage supply line provided in the display panel; and
During the active period when internal compensation is performed to compensate for changes in the threshold voltage or mobility of the driving transistors provided in the pixels, the voltage supplied to the panel voltage supply line by the panel voltage is detected, and the voltage supplied to the panel voltage supply line is detected. A control unit that controls the voltage supply unit so that a corrected panel voltage corresponding to the voltage is output to the panel voltage supply line during the blank period,
The internal compensation is not performed during the blank period,
The panel voltage supply line includes at least one of a driving voltage line connected to the driving transistor and an initialization voltage line provided in the pixel,
The panel voltage is a driving voltage supplied to the driving transistor through the driving voltage line so that current can be supplied to the light emitting device connected to the driving transistor, and through the initialization voltage line to initialize the pixels when performing the internal compensation. It includes at least one of the supplied initialization voltages, and the voltage measured by the detection in the active period is greater than, equal to, or between values greater than or equal to the value of the panel voltage supplied to the panel voltage supply line. has a value that swings from
The corrected panel voltage supplied to the panel voltage supply line in the blank period is the average value of the voltage measured by the detection in the active period, or has a value that varies between the maximum and minimum values of the voltage. , or a light emitting display device having a waveform and voltage corresponding to the waveform and voltage of the voltage. According to claim 1,
A light emitting display device in which the light emitting elements provided in the pixels start emitting light by the internal compensation and then repeatedly emit and extinguish light by an emission signal during one frame period. According to claim 2,
A light emitting display device in which at least one of the pixels starts emitting light in the active period, is turned off by the emission signal, and then emits light again in the blank period. According to claim 1,
A light emitting display device in which at least one of the light emitting elements provided in the pixels starts emitting light by the internal compensation in the active period and then continues to emit light in the blank period. According to claim 1,
The correction panel voltage includes at least one of a voltage corresponding to the driving voltage and a voltage corresponding to the initialization voltage. According to claim 1,
Among the sections in which the internal compensation is performed, in an initialization section, the panel voltage having a first voltage value is supplied to the display panel through the panel voltage supply line,
Among the sections in which the internal compensation is performed, in sections excluding the initialization section, the panel voltage having a second voltage value smaller than the first voltage value is supplied to the display panel through the panel voltage supply line to emit light. Display device. According to claim 1,
The period during which the internal compensation is performed in the active period includes at least two sections,
In at least one of the at least two sections, the initialization voltage line and the driving voltage line are connected, so that a voltage greater than the initialization voltage is supplied through the initialization voltage line, or a voltage greater than the driving voltage is supplied through the driving voltage. A light emitting display device supplied through a line. According to claim 1,
The voltage supply unit,
a resistance variable unit whose resistance value varies according to a voltage control signal supplied from the control unit; and
A light emitting display device comprising a voltage generator that generates the corrected panel voltage using the resistance value. According to claim 8,
The resistance variable part,
a first resistance variable unit turned on or off according to a first voltage control signal supplied from the control unit;
a second resistance variable unit turned on or off according to a second voltage control signal supplied from the control unit;
a resistor connected to the first resistance variable unit; and
A light emitting display device including a resistor connected to the second resistance variable portion. According to claim 7,
The correction panel voltage includes a voltage corresponding to the driving voltage and a voltage corresponding to the initialization voltage.

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