KR102617812B1 - Organic light emitting display apparatus - Google Patents

Abstract

The organic light emitting display device may include a base layer, a circuit element layer, a display element layer, an encapsulation layer, and a sealing member. The circuit element layer may include a power supply line disposed on the base layer and an auxiliary power supply pattern disposed and connected to the power supply line. The display device layer may include a first electrode, a light emitting layer, and a second electrode sequentially disposed on the circuit device layer. The second electrode may be electrically connected to the auxiliary power supply pattern. The sealing member may be disposed between the circuit element layer and the encapsulation layer and may be disposed to overlap the auxiliary power supply pattern in a plane view.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY APPARATUS}

The present invention relates to an organic light emitting display device, and more specifically to an organic light emitting display device having a sealing member.

Organic light emitting display devices have the advantage of having a wide viewing angle, excellent contrast, and fast response speed, so they have recently been used in various display devices.

Organic light emitting display devices include organic light emitting diodes that emit light, and organic light emitting diodes are vulnerable to moisture and oxygen. To this end, a sealing member is disposed on the outside of the organic light emitting display device to seal the organic light emitting diode.

The sealing member is formed by placing a curable material between the lower substrate and the upper substrate and then curing it. During the curing process, defects may occur in circuit elements around the sealing member.

The purpose of the present invention is to provide an organic light emitting display device that can reduce the non-display area of a display panel.

The purpose of the present invention is to provide an organic light emitting display device that can prevent defects in circuit elements overlapping with a sealing member during the curing process of the sealing member.

An organic light emitting display device according to an embodiment of the present invention may include a base layer, a circuit element layer, a display element layer, an encapsulation layer, and a sealing member.

A display area and a non-display area adjacent to the display area may be defined in the base layer.

The auxiliary power supply pattern may include a power supply line and an auxiliary power supply pattern. The auxiliary power supply pattern may be disposed on the base layer and receive a common voltage. The auxiliary power supply pattern may be disposed to overlap the power supply line and be connected to the power supply line.

The display element layer may include a first electrode, a light emitting layer, and a second electrode. The first electrode may be disposed on the circuit element layer. The light emitting layer may be disposed on the first electrode. The second electrode may be disposed on the light emitting layer and electrically connected to the auxiliary power supply pattern.

The encapsulation layer may be disposed on the display element layer.

The sealing member may be disposed between the circuit element layer and the encapsulation layer, and may be disposed to overlap the auxiliary power supply pattern in the non-display area in a plan view.

The auxiliary power supply pattern may contact the sealing member.

The display element layer may further include an auxiliary pattern disposed in the non-display area, disposed on the same layer as the first electrode, and connected to the auxiliary power supply pattern.

The circuit element layer may further include a first intermediate insulating layer and a second intermediate insulating layer. The first intermediate insulating layer may be disposed between the power supply line and the auxiliary power supply pattern, and may be provided with a contact hole through which the power supply line and the auxiliary power supply pattern are connected. A contact hole may be provided in the second intermediate insulating layer, disposed between the auxiliary power supply pattern and the auxiliary pattern, and connected to the auxiliary power supply pattern and the auxiliary pattern.

The display element layer may further include a pixel definition film disposed between the auxiliary pattern and the second electrode, provided with a contact hole through which the auxiliary pattern and the second electrode are connected, and provided with an opening through which the light emitting layer is disposed. there is.

The circuit element layer may further include a switching transistor, a driving transistor, and a light emission control transistor.

The switching transistor may include a control electrode that receives a scan signal, an input electrode that receives a data signal, and an output electrode.

The driving transistor may have an input electrode connected to the output electrode of the switching transistor.

The light emission control transistor includes a control electrode that receives a light emission signal, and may be connected between a voltage line and the driving transistor, or between the driving transistor and the first electrode.

The circuit element layer may further include a light emitting line driving circuit and a gate driving circuit. The light emission line driving circuit may provide the light emission signal to the light emission control transistor. The gate driving circuit may provide the scanning signal to the switching transistor. On a plane, the light emitting line driving circuit may be disposed farther from the display area than the gate driving circuit.

The auxiliary power supply pattern may overlap the light emitting line driving circuit.

The auxiliary power supply pattern may include a material with a higher melting point than the power supply line.

The circuit element layer may further include a voltage line that receives a power voltage greater than the common voltage and an auxiliary voltage pattern disposed on an upper portion of the voltage line and connected to the voltage line.

The auxiliary voltage pattern may be disposed on the same layer as the auxiliary power supply pattern and may overlap the sealing member.

The auxiliary voltage pattern may contact the sealing member.

The circuit element layer may further include a pad portion disposed in the non-display area. In a plan view, the auxiliary voltage pattern may be disposed between the pad portion and the display area.

The circuit element layer may further include a data line and a demux. The demux may be connected between the pad portion and the data line. On a plane, the auxiliary voltage pattern may cover the demux.

The circuit element layer may further include an anti-static pattern disposed in the non-display area. On a plane, the auxiliary voltage pattern may cover the anti-static pattern.

The circuit element layer may further include an insulating layer disposed below the auxiliary power supply pattern. A hole is provided in the auxiliary power supply pattern, and the sealing member may contact the insulating layer or the base layer through the hole.

An organic light emitting display device according to another embodiment of the present invention may include a base layer, a power supply line, a voltage supply line, an auxiliary power supply pattern, an auxiliary voltage pattern, an organic light emitting element, an encapsulation layer, and a sealing member.

The power supply line may be disposed on the base layer and receive a common voltage.

The voltage supply line is disposed on the base layer and may receive a power voltage greater than the common voltage.

The auxiliary power supply pattern may be disposed to overlap the power supply line and be connected to the power supply line.

The auxiliary voltage pattern may be disposed to overlap the voltage supply line and be connected to the voltage supply line.

The organic light emitting device may be disposed on the auxiliary power supply pattern and the auxiliary voltage pattern.

The encapsulation layer may be disposed on the organic light emitting device.

The sealing member may be disposed between the base layer and the encapsulation layer to seal the organic light emitting device, and may overlap the auxiliary power supply pattern and the auxiliary voltage pattern.

The auxiliary power supply pattern may be disposed on the same layer as the auxiliary voltage pattern.

Each of the auxiliary power supply pattern and the auxiliary voltage pattern may include a material having a higher melting point than each of the power supply line and the voltage supply line.

Each of the auxiliary power supply pattern and the auxiliary voltage pattern may contact the sealing member.

An organic light emitting display device according to another embodiment of the present invention may include a base layer, a transistor, an organic light emitting element, a power supply line, an auxiliary power supply pattern, an encapsulation layer, and a sealing member.

The transistor is disposed on the base layer and may include a control electrode, an input electrode, and an output electrode.

The organic light emitting device may be disposed on top of the transistor and connected to the transistor.

The power supply line is disposed on the base layer and receives a constant voltage, and may be disposed on the same layer as any one of the control electrode, the input electrode, and the output electrode of the transistor.

The auxiliary power supply pattern may be disposed above the power supply line and the transistor, below the organic light emitting device, and connected to the power supply line.

The encapsulation layer may be disposed on the organic light emitting device.

The sealing member may be disposed between the base layer and the encapsulation layer to seal the organic light emitting device, and may overlap the auxiliary power supply pattern and the auxiliary voltage pattern.

In an embodiment of the present invention, the non-display area of the display panel can be reduced.

In an embodiment of the present invention, defects in circuit elements overlapping with the sealing member can be prevented during the curing process of the sealing member.

1 is a perspective view of a display device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view of the display module of FIG. 1.
Figure 3 is a plan view of a display panel according to an embodiment of the present invention.
Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.
FIG. 5 is a cross-sectional view taken along line II′ of FIG. 3.
FIG. 6 is a diagram illustrating area AA of FIG. 3.
FIG. 7 is a cross-sectional view taken along line II-II′ of FIG. 3.
8 is a cross-sectional view of a portion of a display panel in a display device according to another embodiment of the present invention.
FIG. 9 is a circuit diagram illustrating a portion of a display panel in a display device according to another embodiment of the present invention.
FIG. 10 is a cross-sectional view illustrating a portion of the display panel according to the embodiment of FIG. 9 .

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In this specification, when a component (or region, layer, part, etc.) is referred to as being “on,” “connected to,” or “coupled to” another component, it is directly connected/connected to another component. This means that they can be combined or a third component can be placed between them.

Like reference numerals refer to like elements. Additionally, in the drawings, the thickness, proportions, and dimensions of components are exaggerated for effective explanation of technical content. “And/or” includes all combinations of one or more of the associated configurations that can be defined.

Terms such as first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be named a second component, and similarly, the second component may also be named a first component without departing from the scope of the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

Additionally, terms such as “below,” “on the lower side,” “above,” and “on the upper side” are used to describe the relationships between the components shown in the drawings. The above terms are relative concepts and are explained based on the direction indicated in the drawings.

Terms such as “include” or “have” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but do not include one or more other features, numbers, or steps. , it should be understood that it does not exclude in advance the possibility of the existence or addition of operations, components, parts, or combinations thereof.

FIG. 1 is a perspective view of a display device 1000 according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the display module DM of FIG. 1 .

The display device 1000 according to this embodiment can be applied to large electronic devices such as televisions and monitors, as well as small and medium-sized electronic devices such as mobile phones, tablets, car navigation systems, game consoles, and smart watches.

Referring to FIG. 1 , the display device 1000 may include a display module (DM), a window member (WM), and a housing member (HM).

The display surface IS on which the image IM of the display module DM is displayed is parallel to the plane defined by the first direction axis DR1 and the second direction axis DR2. The normal direction of the display surface IS, that is, the thickness direction of the display module DM, is indicated by the third direction axis DR3. The front (or upper) and back (or lower) surfaces of each member are separated by the third direction DR3. However, the direction indicated by the first to third direction axes DR1, DR2, and DR3 is a relative concept and can be converted to another direction. Hereinafter, the first to third directions refer to the same reference numerals as the directions indicated by the first to third direction axes DR1, DR2, and DR3, respectively.

The display module (DM) may be a flat rigid display module. However, the present invention is not limited thereto, and the display module (DM) according to the present invention may be a flexible display module.

As shown in FIG. 1, the display module DM includes a display area DM-DA where the image IM is displayed and a non-display area DM-NDA adjacent to the display area DM-DA. The non-display area (DM-NDA) is an area where images are not displayed. Figure 1 shows a vase as an example of an image (IM). As an example, the display area (DM-DA) may have a rectangular shape. The non-display area (DM-NDA) may surround the display area (DM-DA). However, the present invention is not limited to this, and the shape of the display area (DM-DA) and the shape of the non-display area (DM-NDA) may be designed relatively.

A window member WM is disposed on the display module DM. A window member (WM) protects the display module (DM). The window member WM may be combined with the housing member HM to form an internal space. The window member WM and the housing member HM may define the appearance of the display device 1000.

The window member WM may be divided into a transmission area (TA) and a bezel area (BA) on a plane. The transmission area (TA) may be an area that transmits most of the incident light. The transmission area (TA) is optically transparent. The transmission area (TA) may have a light transmittance of about 90% or more. Transmissive area TA may correspond to display area DM-DA of display module DM.

The bezel area BA may be an area that blocks most of the incident light. The bezel area BA prevents components placed below the window member WM from being visible from the outside. Additionally, the bezel area BA may reduce reflection of light incident from outside the window member WM. The bezel area BA may correspond to the non-display area DM-NDA of the display module DM.

The bezel area (BA) may be adjacent to the transmission area (TA). The shape of the transmission area (TA) on a plane may be defined by the bezel area (BA).

The housing member HM provides a predetermined internal space. The display module (DM) is accommodated in the internal space. In addition to the display module DM, various electronic components, such as a power supply, a storage device, an audio input/output module, and a camera, may be mounted in the internal space of the housing member HM.

Figure 2 is a cross-sectional view of the display module DM according to an embodiment of the present invention. FIG. 2 shows a cross section defined by the first direction DR1 and the third direction DR3.

As shown in FIG. 2, the display module DM includes a display panel DP and a touch sensing unit (TS, or touch sensing layer). Although not separately shown, the display module DM according to an embodiment of the present invention may further include a protection member disposed on the lower surface of the display panel DP.

The display panel DP may be an emissive display panel and is not particularly limited. For example, the display panel DP may be an organic light emitting display panel or a quantum dot light emitting display panel. In an organic light emitting display panel, the light emitting layer includes an organic light emitting material. The emitting layer of a quantum dot light emitting display panel includes quantum dots, or quantum rods. Hereinafter, the display panel DP will be described as an organic light emitting display panel.

The display panel DP includes a base layer SUB, a circuit element layer DP-CL disposed on the base layer SUB, a display element layer DP-OLED, and an encapsulation layer ENP. Although not separately shown, the display panel DP may further include functional layers such as a refractive index adjustment layer.

The base layer (SUB) may include at least one plastic film. The base layer (SUB) is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic/inorganic composite material substrate. The display area (DM-DA) and the non-display area (DM-NDA) described with reference to FIG. 1 may be defined identically in the base layer (SUB).

The circuit element layer (DP-CL) includes at least one intermediate insulating layer and a circuit element. The intermediate insulating layer includes at least one intermediate inorganic layer and at least one intermediate organic layer. The circuit elements include signal lines, pixel driving circuits, etc. A detailed description of this will be provided later.

The display element layer (DP-OLED) includes at least organic light emitting diodes. The display device layer (DP-OLED) may further include an organic layer such as a pixel defining layer.

The encapsulation layer (ENP) is disposed on the display device layer (DP-OLED) and seals the display device layer (DP-OLED).

The display panel DP may further include a sealing member SL disposed between the circuit element layer DP-CL and the encapsulation layer ENP. The sealing member SL may be disposed between the circuit element layer DP-CL and the encapsulation layer ENP to bond the circuit element layer DP-CL and the encapsulation layer ENP. The sealing member (SL), together with the circuit element layer (DP-CL) and the encapsulation layer (ENP), may serve to block the display element layer (DP-OLED) from external moisture, air, etc.

The touch detection unit (TS) acquires coordinate information of external input. The touch sensing unit TS may be disposed on the encapsulation layer ENP. The touch sensing unit TS may be attached to the encapsulation layer ENP through an adhesive layer and may be formed on the encapsulation layer ENP through a thin film process.

The touch detection unit (TS) can detect external input using, for example, a capacitance method. In the present invention, the operation method of the touch sensing unit (TS) is not particularly limited, and in one embodiment of the present invention, the touch sensing unit (TS) may sense an external input using an electromagnetic induction method or a pressure sensing method.

Figure 3 is a plan view of the display panel DP according to an embodiment of the present invention.

As shown in FIG. 3, the display panel DP includes a display area DA and a non-display area NDA on a plane surface. In this embodiment, the non-display area NDA may be defined along the border of the display area DA. The display area (DA) and non-display area (NDA) of the display panel (DP) correspond to the display area (DM-DA) and non-display area (DM-NDA) of the display module (DM) shown in FIG. 1, respectively. . The display area (DA) and non-display area (NDA) of the display panel (DP) do not necessarily have to be the same as the display area (DM-DA) and non-display area (DM-NDA) of the display module (DM). It may change depending on the structure/design of the panel (DP).

The display panel DP includes a plurality of pixels PX. A plurality of pixels PX may be arranged in the display area DA. Each of the pixels PX includes an organic light emitting diode and a pixel driving circuit connected thereto.

The display panel DP may include a plurality of signal lines and a pad portion PD. The plurality of signal lines include scan lines (GL), data lines (DL), light emission lines (EL), control signal lines (SL-D), initialization lines (SL-Vint), and voltage lines (SL-VDD). , and a power supply line (E-VSS). A plurality of signal lines and a pad portion (PD) may be included in the circuit element layer (DP-CL) shown in FIG. 2 .

Scan lines (GL), data lines (DL), light emission lines (EL), control signal line (SL-D), initialization line (SL-Vint), voltage line (SL-VDD) and power supply line ( Some of the E-VSS) are placed on the same floor, and some are placed on different floors.

The scan lines GL are each connected to a corresponding pixel PX among the plurality of pixels PX, and the data lines DL are respectively connected to the corresponding pixel PX among the plurality of pixels PX. do. Each of the light emission lines EL may be arranged in parallel with a corresponding scan line among the scan lines GL. The control signal line (SL-D) can provide control signals to the pixel driving circuit (GDC). The initialization line SL-Vint may provide an initialization voltage to the plurality of pixels PX. The voltage line SL-VDD is connected to a plurality of pixels PX and may provide a power supply voltage (eg, first voltage) to the plurality of pixels PX. The voltage line SL-VDD may include a plurality of lines extending in the first direction DR1 and a plurality of lines extending in the second direction DR2. The power supply line (E-VSS) may be arranged in the non-display area (NDA) surrounding three sides of the display area (DA). The power supply line E-VSS may provide a common voltage (eg, a second voltage) to the plurality of pixels PX. The common voltage may be a voltage at a lower level than the power voltage.

The display panel DP may further include a pixel driving circuit (GDC). The pixel driving circuit (GDC) may be disposed on one side of the non-display area (NDA) and connected to the scan lines (GL) and the emission lines (EL).

The pixel driving circuit (GDC) may include a gate driving circuit (not shown) and a light emission line driving circuit (not shown). A gate driving circuit (not shown) may provide a signal to the scan lines GL, and an emission line driving circuit (not shown) may provide a signal to the emission lines EL.

The pixel driving circuit (GDC) may be included in the circuit element layer (DP-CL) shown in FIG. 2. The pixel driving circuit (GDC) may include a plurality of thin film transistors formed through the same process as the driving circuit of the pixels (PX), for example, a low temperature polycrystaline silicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process.

The pad portion PD includes a plurality of pads. A portion of the pad portion PD may be connected to ends of the data lines DL, the control signal line SL-D, the initialization line SL-Vint, and the voltage line SL-VDD. Another part of the pad portion PD may be connected to touch signal lines of the touch sensing unit TS.

Although not shown, the display panel DP may further include a bank (not shown) disposed between the display area DA and the pad portion PD. Additionally, the display panel DP may further include a dam portion (not shown) surrounding the edge of the display area DA. When the bank and dam are formed by printing a specific layer when forming the display panel DP, it is possible to prevent the specific layer from overflowing outside the bank or dam.

In plan view, the sealing member SL may be disposed in the non-display area NDA of the display panel DP and may be arranged to surround the display area DA. The sealing member (SL) may be arranged to overlap the power supply line (E-VSS). The sealing member SL may overlap a portion of the pixel driving circuit GDC.

The display panel DP may further include an auxiliary power supply pattern (VSSP) and an auxiliary voltage pattern (VDDP).

On a plane, the auxiliary power supply pattern (VSSP) is electrically connected to the power supply line (E-VSS) and may overlap the sealing member (SL).

On a plane, the auxiliary voltage pattern (VDDP) is electrically connected to the voltage line (SL-VDD) and may overlap the sealing member (SL). On a plane, the auxiliary voltage pattern VDDP may be disposed between the pad portion PD and the display area DA.

FIG. 4 is an equivalent circuit diagram of one pixel of FIG. 3.

One pixel (PX) according to an embodiment of the present invention may include a plurality of transistors (T1 to T7), a storage capacitor (Cst), and an organic light emitting diode (OLED).

The thin film transistors (T1 to T7) include a driving transistor (T1), a switching transistor (T2), a compensation transistor (T3), an initialization transistor (T4), a first emission control transistor (T5), and a second emission control transistor (T6). , and a bypass transistor (T7).

The pixel PX has a first scan line 14 that transmits the nth scan signal (Sn) to the switching transistor (T2) and the compensation transistor (T3), and an n-1th scan signal (Sn-) to the initialization transistor (T4). 1), a second scan line 24 transmitting the n+1th scan signal (Sn+1) to the bypass transistor T7, a third scan line 34 transmitting the n+1th scan signal (Sn+1), and a first light emission control transistor T5. and a light emission line 15 that delivers the light emission control signal (En) to the second light emission control transistor (T6), a data line 16 that delivers the data signal (Dm), and a voltage line that delivers the power supply voltage (ELVDD) ( 26), and includes an initialization line 22 that transmits an initialization voltage (Vint) that initializes the driving transistor (T1).

The gate electrode (G1) of the driving transistor (T1) is connected to the first electrode (C1) of the storage capacitor (Cst). The source electrode S1 of the driving transistor T1 is connected to the voltage line 26 via the first emission control transistor T5. The drain electrode (D1) of the driving transistor (T1) is electrically connected to the anode of the organic light emitting device (OLED) via the second emission control transistor (T6). The driving transistor (T1) receives the data signal (Dm) according to the switching operation of the switching transistor (T2) and supplies the driving current (Id) to the organic light emitting device (OLED).

The gate electrode (G2) of the switching transistor (T2) is connected to the first scan line (14). The source electrode (S2) of the switching transistor (T2) is connected to the data line (16). The drain electrode D2 of the switching transistor T2 is connected to the source electrode S1 of the driving transistor T1, and is connected to the voltage line 26 via the first emission control transistor T5. The switching transistor (T2) is turned on according to the nth scan signal (Sn) received through the first scan line 14 and sends the data signal (Dm) transmitted to the data line 16 to the source of the driving transistor (T1). A switching operation is performed to transmit the signal to the electrode S1.

The gate electrode G3 of the compensation transistor T3 is connected to the first scan line 14. The source electrode (S3) of the compensation transistor (T3) is connected to the drain electrode (D1) of the driving transistor (T1) and the anode of the organic light emitting device (OLED) via the second emission control transistor (T6). The drain electrode (D3) of the compensation transistor (T3) is connected to the first electrode (C1) of the storage capacitor (Cst), the source electrode (S4) of the initialization transistor (T4), and the gate electrode (G1) of the driving transistor (T1). It is done. The compensation transistor T3 is turned on according to the nth scan signal Sn received through the first scan line 14 and connects the gate electrode G1 and the drain electrode D1 of the driving transistor T1 to each other. The driving transistor (T1) is connected to a diode.

The gate electrode (G4) of the initialization transistor (T4) is connected to the second scan line (24). The drain electrode (D4) of the initialization transistor (T4) is connected to the initialization line (22). The source electrode (S4) of the initialization transistor (T4) is connected to the first electrode (C1) of the storage capacitor (Cst), the drain electrode (D3) of the compensation transistor (T3), and the gate electrode (G1) of the driving transistor (T1). do. The initialization transistor (T4) is turned on according to the n-1th scan signal (Sn-1) received through the second scan line 24 to apply the initialization voltage (Vint) to the gate electrode (G1) of the driving transistor (T1). is transmitted to initialize the voltage of the gate electrode (G1) of the driving transistor (T1).

The gate electrode (G5) of the first emission control transistor (T5) is connected to the emission line (15). The first light emission control transistor T5 may be connected between the voltage line 26 and the driving transistor T1. The source electrode S5 of the first light emission control transistor T5 is connected to the voltage line 26. The drain electrode D5 of the first emission control transistor T5 is connected to the source electrode S1 of the driving transistor T1 and the drain electrode D2 of the switching transistor T2. As the emission control signal En is applied to the gate electrode G5 of the first emission control transistor T5, the first emission control transistor T5 is turned on and the driving current Id is supplied to the organic light emitting device OLED. It flows. The first light emission control transistor T5 can determine the timing at which the driving current Id flows through the organic light emitting diode (OLED).

The gate electrode (G6) of the second light emission control transistor (T6) is connected to the light emission line (15). The second light emission control transistor T6 may be connected between the driving transistor T1 and the organic light emitting diode (OLED). The source electrode (S6) of the second light emission control transistor (T6) is connected to the drain electrode (D1) of the driving transistor (T1) and the source electrode (S3) of the compensation transistor (T3). The drain electrode (D6) of the second light emission control transistor (T6) is electrically connected to the anode of the organic light emitting device (OLED). The first emission control transistor T5 and the second emission control transistor T6 are turned on according to the emission control signal En received through the emission line 15. As the emission control signal (En) is applied to the gate electrode (G6) of the second emission control transistor (T6), the second emission control transistor (T6) is turned on and the driving current (Id) is supplied to the organic light emitting device (OLED). It flows. The second light emission control transistor T6 can determine the timing at which the driving current Id flows through the organic light emitting diode (OLED).

The gate electrode (G7) of the bypass transistor (T7) is connected to the third scan line (34). The source electrode (S7) of the bypass transistor (T7) is connected to the anode of the organic light emitting device (OLED). The drain electrode (D7) of the bypass transistor (T7) is connected to the initialization line (22). The bypass transistor T7 is turned on according to the n+1th scan signal (Sn+1) received through the third scan line 34 to initialize the anode of the organic light emitting device (OLED).

The second electrode C2 of the storage capacitor Cst is connected to the voltage line 26. The first electrode (C1) of the storage capacitor (Cst) is connected to the gate electrode (G1) of the driving transistor (T1), the drain electrode (D3) of the compensation transistor (T3), and the source electrode (S4) of the initialization transistor (T4). do.

The cathode of an organic light emitting device (OLED) receives a reference voltage (ELVSS). The organic light emitting device (OLED) receives the driving current (Id) from the driving transistor (T1) and emits light.

In the pixel PX according to an embodiment of the present invention, the switching transistor T2, compensation transistor T3, initialization transistor T4, and bypass transistor T7 each have gate electrodes G2, G3, G4, G5) may receive a signal from the gate driving circuit (not shown) of the pixel driving circuit (GDC) described with reference to FIG. 3.

In the pixel PX according to an embodiment of the present invention, the first light emission control transistor T5 and the second light emission control transistor T6 are the light emission line driving circuit (not shown) of the pixel driving circuit GDC described with reference to FIG. 3. signal can be received from the city).

In another embodiment of the present invention, the number and connection relationship of the transistors T1 to T7 constituting the pixel PX may be changed in various ways.

FIG. 5 is a cross-sectional view taken along line II′ of FIG. 3. FIG. 6 is a diagram illustrating area AA of FIG. 3.

Referring to FIGS. 2 and 5 , the base layer (SUB) may be formed of various materials such as glass, metal, or plastic. Plastics include polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate, polycarbonate (PC), and polyetherimide. : PEI) or polyethersulfone (PES).

In the base layer SUB, the display area DA and the non-display area NDA of the display panel DP may be defined to be substantially the same.

The circuit element layer (DP-CL) is disposed on the base substrate (SUB).

The circuit element layer (DP-CL) includes the pixel driving circuit (GDC) described with reference to FIG. 3, a plurality of signal lines, the pad portion (PD), and the transistor (T1) of the pixel (PX) described with reference to FIG. 4. ~T7) may be included.

Referring to FIGS. 3 and 6 , the light emission line driving circuit (ETC) of the pixel driving circuit (GDC) is disposed farther from the display area (DA) of the display panel (DP) than the gate driving circuit (GTC) on a plane. . Each of the gate driving circuit (GTC) and the emission line driving circuit (ETC) may include a plurality of transistors and electronic devices.

In FIG. 5 , an emission line driving circuit area (ETCA) in which an emission line driving circuit (ETC) is disposed and a gate driving circuit area (GTCA) in which a gate driving circuit (GTC) is disposed are shown. In FIG. 5 , the first transistor (TFT1) included in the emission line driving circuit (ETC) is shown as an example, and the second transistor (TFT2) included in the gate driving circuit (GTC) is shown as an example. Additionally, in FIG. 5 , the third transistor TFT3 included in the pixel PX is shown as an example.

The first transistor TFT1 includes a first semiconductor pattern SM1, a first control electrode CE1, a first input electrode IE1, and a first output electrode OE1.

The second transistor TFT2 includes a second semiconductor pattern SM2, a second control electrode CE2, a second input electrode IE2, and a second output electrode OE2.

The third transistor TFT3 includes a third semiconductor pattern SM3, a third control electrode CE3, a third input electrode IE3, and a third output electrode OE3.

The circuit element layer DP-CL may include a buffer layer 110 and first to fourth insulating layers 120, 130, 140, and 150.

The buffer layer 110 is disposed on the base layer (SUB). The buffer layer 110 is used to flatten the surface of the base layer (SUB) or to remove impurities, etc. from the first to third semiconductor patterns (SM1, SM2, SM3) of the first to third transistors (TFT1, TFT2, TFT3). It is placed to prevent penetration. The buffer layer 110 may be formed of silicon oxide or silicon nitride.

The first to third semiconductor patterns SM1, SM2, and SM3 may be disposed on the buffer layer 110.

The first insulating layer 120 may be disposed on the first to third semiconductor patterns SM1, SM2, and SM3. The first insulating layer 120 may be made of an organic or inorganic insulating film.

The first to third control electrodes CE1 , CE2 , and CE3 may be disposed on the first insulating layer 120 .

The second insulating layer 130 may be disposed on the first to third control electrodes CE1, CE2, and CE3. The second insulating layer 130 may be made of an organic or inorganic insulating film.

The first to third input electrodes (IE1, IE2, IE3) and the first to third output electrodes (OE1, OE2, OE3) may be disposed on the second insulating layer 130.

The first input electrode IE1 and the first output electrode OE1 are spaced apart from each other and connected to the first semiconductor pattern SM1 through a contact hole (not shown) formed in the second insulating layer 130.

The second input electrode IE2 and the second output electrode OE2 are spaced apart from each other and connected to the second semiconductor pattern SM2 through a contact hole (not shown) formed in the second insulating layer 130.

The third input electrode IE3 and the third output electrode OE3 are spaced apart from each other and connected to the third semiconductor pattern SM3 through a contact hole (not shown) formed in the second insulating layer 130.

In another embodiment of the present invention, unlike the structure of each of the first to third transistors (TFT1, TFT2, and TFT3) shown in FIG. 5, the first to third semiconductor patterns (SM1, SM2, SM3), the first The positions of the first to third control electrodes (CE1, CE2, CE3), first to third input electrodes (IE1, IE2, IE3), and first to fourth output electrodes (OE1, OE2, OE3) can be changed. You can.

In another embodiment of the present invention, some layers of the first to third transistors TFT1, TFT2, and TFT3 may be formed on the same layer and using the same material as the auxiliary power supply pattern VSSP. For example, the third input electrode (IE3) and the third output electrode (OE3) of the third transistor (TFT3) are shown as being disposed on the same layer as the power supply line (E-VSS), but in other embodiments , may be disposed on the same layer as the auxiliary power supply pattern (VSSP) and connected to the third semiconductor pattern (SM3) through contact holes formed in the second and third insulating layers 130 and 140.

Therefore, according to another embodiment of the present invention, when forming the auxiliary power supply pattern (VSSP), the metal layer constituting the first to third transistors (TFT1, TFT2, and TFT3) can be formed, so that the first to third transistors (TFT1, TFT2, TFT3) can be formed. The design freedom of the three transistors (TFT1, TFT2, and TFT3) is improved, and as a result, display quality can be improved.

Referring again to FIG. 5 , the power supply line (E-VSS) may be disposed on the second insulating layer 130. In an embodiment of the present invention, the power supply line (E-VSS) is on the same layer as the first to third input electrodes (IE1, IE2, IE3) and the first to third output electrodes (OE1, OE2, OE3) can be placed in In an embodiment of the present invention, the initialization line (SL-Vint) and the voltage line (SL-VDD) may be placed on the same layer as the power supply line (E-VSS).

The power supply line (E-VSS) may include a single layer or multiple layers. For example, the power supply line (E-VSS) may have a structure in which Ti/Al/Ti are sequentially stacked.

The third insulating layer 140 may be disposed on the power supply line (E-VSS) and the first to third transistors (TFT1, TFT2, and TFT3). The third insulating layer 140 may be made of an organic or inorganic insulating film. The third insulating layer 140 may be defined as a first intermediate insulating layer.

The auxiliary power supply pattern (VSSP) may be disposed on the third insulating layer 140. The auxiliary power supply pattern (VSSP) can overlap the power supply line (E-VSS). The auxiliary power supply pattern (VSSP) may be electrically connected to the power supply line (E-VSS) through a contact hole (not shown) formed in the third insulating layer 140.

The auxiliary power supply pattern (VSSP) may be formed of a material having a higher melting point than the first control electrode (CE1), the first input electrode (IE1), and the first output electrode (OE1).

The auxiliary power supply pattern (VSSP) may include a metal, for example, molybdenum (Mo).

The fourth insulating layer 150 may be disposed on the auxiliary power supply pattern (VSSP). The fourth insulating layer 150 may overlap a portion of the auxiliary power supply pattern (VSSP). The fourth insulating layer 150 may be made of an organic or inorganic insulating film. The fourth insulating layer 150 may be defined as a second intermediate insulating layer.

The display device layer (DP-OLED) may include a pixel defining layer (PDL) and an organic light emitting device (OD).

The pixel defining layer (PDL) is disposed on the fourth insulating layer 150. A plurality of openings may be defined in the pixel definition layer (PDL). An organic light emitting device (OD) may be provided in each of the openings.

The organic light emitting device (OD) includes a first electrode (E1), a second electrode (E2), and an emitting layer (EML). The first electrode E1 may be disposed on the circuit element layer DP-CL. The first electrode E1 may penetrate the third and fourth insulating layers 140 and 150 and be electrically connected to the third transistor TFT3. A plurality of first electrodes E1 may be provided. At least a portion of each of the plurality of first electrodes E1 may be exposed through each of the openings.

The second electrode E2 is disposed on the first electrode E1. The second electrode E2 may overlap the plurality of first electrodes E1 and the pixel defining layer (PDL). When a plurality of organic light emitting devices (OD) are provided, the same voltage may be applied to the second electrode (E2) of the plurality of organic light emitting devices (OD). Accordingly, a separate patterning process to form the second electrode E2 may be omitted. Meanwhile, this is shown as an example, and a plurality of second electrodes E2 may be provided to correspond to each of the openings.

The light emitting layer (EML) is disposed between the first electrode (E1) and the second electrode (E2). A plurality of light emitting layers (EML) may be provided and disposed in each of the openings. The organic light emitting device (OD) can generate light by activating the light emitting layer (EML) according to the potential difference between the first electrode (E1) and the second electrode (E2).

Although not shown, the organic light emitting device (OD) further includes an electronic control layer disposed between the first electrode (E1) and the light emitting layer (EML) and a hole control layer disposed between the light emitting layer (EML) and the second electrode (E2). It can be included.

The display device layer (DP-OLED) may further include an auxiliary pattern (VSP) disposed on the fourth insulating layer 150. The auxiliary pattern (VSP) may be disposed on the same layer as the first electrode (E1).

The auxiliary pattern (VSP) may be disposed in the non-display area (NDA) of the display panel (DP). The auxiliary pattern (VSP) may be connected to the auxiliary power supply pattern (VSSP) through a contact hole (not shown) formed in the fourth insulating layer 150.

The second electrode E2 may be connected to the auxiliary pattern VSP through a contact hole (not shown) formed in the pixel defining layer PDL in the non-display area NDA.

The power supply line (E-VSS) may provide a common voltage to the second electrode (E2) through the auxiliary power supply pattern (VSSP) and the auxiliary pattern (VSP).

The sealing member (SL) may overlap the auxiliary power supply pattern (VSSP). The sealing member (SL) is disposed between the auxiliary power supply pattern (VSSP) and the encapsulation layer (ENP) and may contact the auxiliary power supply pattern (VSSP).

The sealing member (SL) may include a photo-curable resin or a thermo-curable resin to be bonded to the auxiliary power supply pattern (VSSP), the third insulating layer 140, and the encapsulation layer (ENP).

The sealing member SL may overlap a portion of the pixel driving circuit GDC of FIG. 3, that is, the emission line driving circuit ETC. Accordingly, the non-display area (NDA) of the display panel (DP) can be reduced.

The auxiliary power supply pattern (VSSP) may cover metal layers of the circuit element layer (DP-CL) that overlap the sealing member (SL). Specifically, the auxiliary power supply pattern (VSSP) may cover the components of the power supply line (E-VSS) and the light emission line driving circuit (ETC), that is, the first transistor (TFT1).

The sealing member SL may be formed by applying a curable material between the auxiliary power supply pattern VSSP and the encapsulation layer ENP and irradiating a laser from the top to the bottom of the encapsulation layer ENP. When a laser is irradiated to a curable material, the temperature of the metal layer disposed in the area overlapped with the curable material, for example, the elements of the pixel driving circuit (GDC) and the power supply line (E-VSS), rises above the melting point. Defects may occur.

According to the display device according to an embodiment of the present invention, the auxiliary power supply pattern (VSSP) is arranged to overlap the sealing member (SL) on the pixel driving circuit (GDC) and the power supply line (E-VSS), and laser irradiation is performed. This can prevent defects in the pixel driving circuit (GDC) and power supply line (E-VSS). To this end, the auxiliary power supply pattern (VSSP) can be formed of a material with a higher melting point than the metal layer constituting the power supply line (E-VSS). When the metal layer constituting the power supply line (E-VSS) is composed of multiple layers, the auxiliary power supply pattern (VSSP) has a melting point greater than that of the metal with the lowest melting point among the plurality of layers constituting the power supply line (E-VSS). It may contain substances having dots.

In addition, the auxiliary power supply pattern (VSSP) is connected to the power supply line (E-VSS) to reduce the resistance of the wiring that supplies the common voltage, and to uniformly provide the common voltage to the second electrode (E2). .

The emission line driving circuit (ETC) is turned on during most of the pixel operation period, thereby minimizing the influence of the parasitic capacitor formed between the auxiliary power supply pattern (VSSP) and the auxiliary power supply pattern (VSSP). Accordingly, the non-display area (NDA) of the display panel (DP) can be reduced by forming the emission line driving circuit (ETC) and the power supply pattern (VSSP) to overlap.

The gate driving circuit (GTC) operates off during most of the pixel operation period and is relatively affected by parasitic capacitors formed between other elements. In other words, the pulse signal output from the gate driving circuit (GTC) has a pulse width corresponding to a very small section (less than 1%) compared to the pixel operation section, so waveform damage due to delay due to the parasitic capacitor causes defective circuit operation. do. Accordingly, in an embodiment of the present invention, the gate driving circuit (GTC) may not be arranged to overlap the power supply pattern (VSSP).

FIG. 7 is a cross-sectional view taken along line II-II′ of FIG. 3.

The pad portion PD may include a first pad layer PD1 and a second pad layer PD2.

The first pad layer PD1 may be disposed on the same layer as the first to third control electrodes CE1, CE2, and CE3. The second pad layer PD2 may be disposed on the same layer as the voltage line SL-VDD. The second pad layer PD2 may contact the first pad layer PD1 through a contact hole (not shown) formed in the second insulating layer 130.

The display panel DP may further include a flexible printed circuit board (FPC). The flexible printed circuit board (FPC) is attached to the display panel DP and can be bent toward the back of the display panel DP.

The flexible printed circuit board (FPC) may be connected to the pad portion (PD) through a conductive adhesive member (ACF). A flexible printed circuit board (FPC) may include a flexible base film (BF), circuit board pad (CPD), and integrated circuit chip (IC). The circuit board pad (CPD) is formed on the base film (BF) and may be in contact with the conductive adhesive member (ACF). The integrated circuit chip (IC) is mounted on the base film (BF) and can provide signals required to drive the display panel (DP) through the circuit board pad (CPD).

The voltage line (SL-VDD) may be placed on the same layer as the power supply line (E-VSS).

The auxiliary voltage pattern VDDP may be disposed on the third insulating layer 140. The auxiliary voltage pattern (VDDP) may overlap the voltage line (SL-VDD). The auxiliary voltage pattern VDDP may be electrically connected to the voltage line SL-VDD through a contact hole (not shown) formed in the third insulating layer 140.

The auxiliary voltage pattern VDDP may be disposed on the same layer as the auxiliary power supply pattern VSSP described with reference to FIG. 5 and may be formed of the same material.

The sealing member SL may overlap the auxiliary voltage pattern VDDP. The sealing member SL may be disposed between the auxiliary voltage pattern VDDP and the encapsulation layer ENP and may contact the auxiliary voltage pattern VDDP.

The auxiliary voltage pattern (VDDP) is connected to the voltage line (SL-VDD) to reduce the resistance of the wiring that supplies the power voltage, and uniformly distributes the power supply voltage to the first light emission control transistor (T5) described with reference to FIG. 4. can be provided.

8 is a cross-sectional view of a portion of a display panel in a display device according to another embodiment of the present invention. FIG. 8 is a cross-sectional view showing a position corresponding to line II′ of FIG. 3 in a display panel according to another embodiment of the present invention.

The auxiliary voltage supply pattern (VSSP1) of the display panel (DP1) described with reference to FIG. 8 is provided with one or more holes (HL1, HL2) compared to the auxiliary voltage supply pattern (VSSP) described with reference to FIG. 5, but the difference is that and the rest is substantially similar.

FIG. 8 exemplarily shows that a first hole (HL1) and a second hole (HL2) are provided in the auxiliary voltage supply pattern (VSSP1). However, the auxiliary voltage supply pattern VSSP1 may be provided with a plurality of first holes HL1 and a plurality of second holes HL2, and the first hole HL1 and the second hole HL2 may be provided in a plurality. ) Only one of the holes may be provided.

The first hole HL1 and the second hole HL2 may be provided to overlap the sealing member SL. The first hole HL1 and the second hole HL2 may penetrate the auxiliary voltage supply pattern VSSP1.

The first hole HL1 may further penetrate at least one of the buffer layer 110 and the first to third insulating layers 120, 130, and 140 in reverse order. In FIG. 8 , the first hole HL1 is illustratively shown to pass through the buffer layer 110 and the first to third insulating layers 120, 130, and 140.

The second hole HL2 may penetrate the auxiliary voltage supply pattern VSSP1 and may not penetrate the buffer layer 110 and the first to fourth insulating layers 120, 130, 140, and 150.

Additionally, a third hole HL3 may be provided in the third insulating layer 140. The third hole HL3 may overlap the sealing member SL and may not overlap the auxiliary voltage supply pattern VSSP1. The third hole HL3 may further penetrate at least one of the buffer layer 110 and the first and second insulating layers 120 and 130 in reverse order. In FIG. 8 , the third hole HL3 is exemplarily shown as penetrating both the buffer layer 110 and the first and second insulating layers 120 and 130.

The sealing member SL may be formed of a material mixed with a hardenable material and glass raw material. The sealing member (SL) adheres more firmly to the base layer (SUB) made of an insulating layer and glass than to a metal one.

According to the display device according to an embodiment of the present invention, the sealing member SL is connected to the insulating layers 110, 120, 130, 140 and the like by at least one of the first to third holes HL1, HL2, and HL3. The mechanical strength of the display panel DP1 can be improved by increasing the area in contact with the base layer SUB.

FIG. 9 is a circuit diagram showing a portion of a display panel in a display device according to another embodiment of the present invention, and FIG. 10 is a cross-sectional view showing a portion of the display panel according to the embodiment of FIG. 9 . FIG. 10 is a cross-sectional view showing a position corresponding to line II-II′ of FIG. 3 in a display panel according to another embodiment of the present invention.

Referring to FIG. 9 , one pad portion PD may be connected to at least two data lines DL1 and DL2 through a demux (DX). FIG. 9 exemplarily shows one pad portion PD connected to the first and second data lines DL1 and DL2.

The demux (DX) may include a first switch element (SW1) and a second switch element (SW2).

The first switch element SW1 may be turned on by the first control signal CS1, and the second switch element SW2 may be turned on by the second control signal CS2. The first and second switch elements SW1 and SW2 may be turned on at different timings.

The signal applied to the pad portion PD provides different data to the first and second data lines DL1 and DL2 by the first and second switch elements SW1 and SW2 that are turned on at different timings. can do.

Referring to FIG. 10 , the demux (DX) of the display panel (DP2) according to another embodiment of the present invention may be provided in the circuit element layer (DP-CL). The first and second switch elements SW1 and SW2 included in the demux (DX) may have the same structure as the third transistor (TFT3). Figure 10 shows the first switch element (SW1) as an example.

The first switch element SW1 may include a fourth semiconductor pattern SM4, a fourth control electrode CE4, a fourth input electrode IE4, and a fourth output electrode OE4.

Additionally, the circuit element layer (DP-CL) may further include an anti-static pattern (ESD). A plurality of anti-static patterns (ESD) may be provided, each having an island shape. The anti-static patterns (ESD) are provided floating and spaced apart from each other. Anti-static patterns (ESD) may be formed in various layers and may include metallic materials. In an embodiment of the present invention, the anti-static pattern (ESD) is exemplarily shown to be disposed on the same layer as the third control electrode (CE3) of the third transistor (TFT3). The anti-static pattern (ESD) can prevent externally generated static electricity from flowing into devices provided in the display area (DA).

The auxiliary voltage pattern VDDP may cover the demux (DX), that is, the first switch element (SW1), on top of the demux (DX). The first switch element SW1 may overlap the sealing member SL.

Additionally, the auxiliary voltage pattern (VDDP) may cover the anti-static pattern (ESD). The anti-static pattern (ESD) may overlap the sealing member (SL).

When forming the sealing member (SL), when a laser is irradiated to a curable material, the temperature of the first switch element (SW1) and the anti-static pattern (ESD) disposed in the area overlapped with the curable material rises above the melting point. Defects may occur.

According to the display device according to an embodiment of the present invention, the auxiliary voltage pattern (VDDP) is formed of a material having a melting point greater than that of the fourth control electrode (CE4), the fourth input electrode (IE4), and the fourth output electrode (OE4). It is formed by

By arranging the auxiliary voltage pattern (VDDP) to overlap the first switch element (SW1) and the anti-static pattern (ESD), defects in the first switch element (SW1) and the anti-static pattern (ESD) can be prevented by laser irradiation. You can.

Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or have ordinary knowledge in the relevant technical field should not deviate from the spirit and technical scope of the present invention as set forth in the claims to be described later. It will be understood that the present invention can be modified and changed in various ways within the scope of the present invention.

Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

SUB: Base layer DP-CL: Circuit element layer
DP-OLED: Display element layer ENP: Encapsulation layer
E-VSS: Power supply line VSSP: Secondary power supply pattern
SL-VDD: Voltage line VDDP: Secondary voltage pattern
SL: Sealing member DP: Display panel

Claims (20)

a base layer in which a display area and a non-display area adjacent to the display area are defined;
a circuit element layer including a data line disposed on the base layer, a power supply line receiving a common voltage, and an auxiliary power supply pattern disposed overlapping on the power supply line and connected to the power supply line;
A first electrode disposed on the circuit element layer, a light-emitting layer disposed on the first electrode, a second electrode disposed on the light-emitting layer and electrically connected to the auxiliary power supply pattern, and disposed in the non-display area and a display element layer including a second electrode and an auxiliary pattern directly connected to the auxiliary power supply pattern; and
Comprising an encapsulation layer disposed on the display element layer,
The data line is disposed on the same layer as the power supply line,
The first electrode and the auxiliary pattern are disposed on the same layer. According to claim 1,
Further comprising a sealing member disposed between the circuit element layer and the encapsulation layer and disposed to overlap the auxiliary power supply pattern in the non-display area in a plan view,
The auxiliary power supply pattern is in contact with the sealing member.
delete According to claim 1,
The circuit element layer is,
a first intermediate insulating layer disposed between the power supply line and the auxiliary power supply pattern and provided with a contact hole through which the power supply line and the auxiliary power supply pattern are connected; and
It further includes a second intermediate insulating layer disposed between the auxiliary power supply pattern and the auxiliary pattern and provided with a contact hole through which the auxiliary power supply pattern and the auxiliary pattern are connected,
The display element layer further includes a pixel defining layer disposed between the auxiliary pattern and the second electrode, provided with a contact hole through which the auxiliary pattern and the second electrode are connected, and provided with an opening through which the light emitting layer is disposed. Luminous display device. According to claim 1,
The circuit element layer is
A switching transistor including a control electrode for receiving a scan signal, an input electrode for receiving a data signal, and an output electrode;
a driving transistor having an input electrode connected to the output electrode of the switching transistor; and
An organic light emitting display device including a control electrode that receives a light emission signal, and further comprising a light emission control transistor connected between a voltage line and the driving transistor or between the driving transistor and the first electrode. According to clause 5,
The circuit element layer is
a light emission line driving circuit that provides the light emission signal to the light emission control transistor; and
Further comprising a gate driving circuit that provides the scanning signal to the switching transistor,
An organic light emitting display device in which the light emitting line driving circuit is disposed farther from the display area than the gate driving circuit in a plan view. According to clause 6,
The organic light emitting display device wherein the auxiliary power supply pattern overlaps the light emitting line driving circuit. According to claim 1,
The organic light emitting display device wherein the auxiliary power supply pattern includes a material with a higher melting point than the power supply line. According to claim 1,
The circuit element layer further includes a voltage line that receives a power voltage greater than the common voltage and an auxiliary voltage pattern disposed on an upper portion of the voltage line and connected to the voltage line. According to clause 9,
Further comprising a sealing member disposed between the circuit element layer and the encapsulation layer and disposed to overlap the auxiliary power supply pattern in the non-display area in a plan view,
The auxiliary voltage pattern is disposed on the same layer as the auxiliary power supply pattern and overlaps the sealing member. According to clause 9,
Further comprising a sealing member disposed between the circuit element layer and the encapsulation layer and disposed to overlap the auxiliary power supply pattern in the non-display area in a plan view,
The auxiliary voltage pattern is in contact with the sealing member. According to clause 9,
The circuit element layer further includes a pad portion disposed in the non-display area,
In a plan view, the auxiliary voltage pattern is disposed between the pad portion and the display area. According to claim 12,
The circuit element layer is
data line; and
Further comprising a demux connected between the pad portion and the data line,
The organic light emitting display device wherein the auxiliary voltage pattern covers the demux on a plane. According to claim 12,
The circuit element layer further includes an anti-static pattern disposed in the non-display area,
The organic light emitting display device wherein the auxiliary voltage pattern covers the anti-static pattern on a plane. According to claim 1,
Further comprising a sealing member disposed between the circuit element layer and the encapsulation layer and disposed to overlap the auxiliary power supply pattern in the non-display area in a plan view,
The circuit element layer further includes an insulating layer disposed below the auxiliary power supply pattern,
An organic light emitting display device wherein a hole is provided in the auxiliary power supply pattern, and the sealing member contacts the insulating layer or the base layer through the hole. base layer;
a power supply line disposed on the base layer and receiving a common voltage;
a voltage supply line disposed on the base layer and receiving a power voltage greater than the common voltage;
an auxiliary power supply pattern disposed to overlap the power supply line and connected to the power supply line;
an auxiliary voltage pattern disposed to overlap the voltage supply line and connected to the voltage supply line;
an organic light emitting device disposed on the auxiliary power supply pattern and the auxiliary voltage pattern;
an encapsulation layer disposed on the organic light emitting device; and
A sealing member disposed between the base layer and the encapsulation layer to seal the organic light emitting device and overlapping the auxiliary power supply pattern and the auxiliary voltage pattern,
The organic light emitting display device wherein the auxiliary power supply pattern includes a material having a higher melting point than the power supply line. According to claim 16,
The auxiliary power supply pattern is disposed on the same layer as the auxiliary voltage pattern. According to claim 16,
Each of the auxiliary power supply pattern and the auxiliary voltage pattern includes a material having a higher melting point than each of the power supply line and the voltage supply line. According to claim 16,
Each of the auxiliary power supply pattern and the auxiliary voltage pattern is in contact with the sealing member. base layer;
a transistor disposed on the base layer and including a control electrode, an input electrode, and an output electrode;
an organic light emitting device disposed on top of the transistor and connected to the transistor;
a power supply line disposed on the base layer and receiving a constant voltage, the power supply line disposed on the same layer as any one of the control electrode, the input electrode, and the output electrode of the transistor;
an auxiliary power supply pattern disposed above the power supply line and the transistor, disposed below the organic light emitting element, and connected to the power supply line;
an encapsulation layer disposed on the organic light emitting device; and
An organic light emitting display device comprising a sealing member disposed between the base layer and the encapsulation layer to seal the organic light emitting element and overlapping the auxiliary power supply pattern and the transistor.

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