KR102615884B1 - Array substrate for display device - Google Patents

Abstract

The present invention is intended to provide an array substrate for a display device that can minimize the inflow of light into the active layer of a thin film transistor, thereby minimizing the shortening of the lifespan of the device due to degradation and the NBTiS phenomenon of the threshold voltage.
To this end, the present invention includes a substrate having a plurality of light-emitting regions and device regions, and buffer layers each disposed on the device regions of the substrate with a buffer layer disconnection region in between.
Due to the structure of the buffer layer having such a disconnected island structure, light incident into the buffer layer disposed below the active layer is minimized, and thus light influx into the active layer can also be minimized.

Description

Array substrate for display device {ARRAY SUBSTRATE FOR DISPLAY DEVICE}

The present invention relates to the structure of an array substrate using thin film transistors used in display devices.

As modern society develops into an information society, the demand for various display devices is also increasing. Recently, liquid crystal displays (LCD), plasma display panels (PDP), and organic light emitting diodes (OLED) have been widely used.

Generally, a thin film transistor (TFT) is used as a switching element to independently drive each pixel of a display device. Specifically, thin film transistors are classified into amorphous silicon thin film transistors, polycrystalline silicon thin film transistors, and oxide semiconductor thin film transistors based on the material that makes up the active layer (semiconductor layer).

Amorphous silicon thin film transistors (a-Si TFTs) have the advantage of short processing time and low production costs because amorphous silicon can be deposited within a short period of time. However, there is a disadvantage in that the mobility of carriers within the active layer is low, which reduces current driving ability and causes changes in threshold voltage.

Polycrystalline silicon thin film transistors (poly-Si TFTs) require an additional crystallization process after amorphous silicon deposition, which increases production costs due to an increase in the number of processes. In addition, it has the disadvantage of being difficult to apply to large areas and making it difficult to secure device uniformity due to its polycrystalline nature.

On the other hand, oxide semiconductor thin film transistors (Oxide Semiconductor TFT) can be processed at low temperatures and can achieve high carrier mobility within the active layer.

In addition, the change in resistance of the oxide depending on the oxygen content is large, making it easy to obtain the desired physical properties, and the nature of the oxide is transparent, making it easy to implement a transparent display, so it has been widely used in thin film transistors in recent years.

Figure 1 is a cross-sectional view showing an array substrate to which a conventional oxide semiconductor thin film transistor substrate is applied.

When light is incident on the active layer 17, a change in the threshold voltage (Vth) may occur. In particular, when the active layer 17 is made of an oxide semiconductor, the change in the threshold voltage (Vth) becomes severe. Accordingly, in general, a light-shielding film 13 is disposed on the lower surface of the active layer 17 to correspond to the active layer 17 to prevent incident of external light.

However, in the case of this light shielding film 13, although it has the effect of blocking external light from entering, it does not effectively block the internal light of the display device, that is, the light emitted from the light source.

Specifically, in the case of Figure 1, the bottom emitting method in the organic light emitting diode display device is used as an example. The organic light-emitting device including the organic material layer 37 emits light 50 toward the bottom of the display device. At this time, some of the light 51 among the emitted light does not completely pass through the substrate and does not exit to the outside, but is exposed to the buffer layer 15. become trapped inside.

At this time, the light trapped in the buffer layer 15 is totally reflected and reaches the lower surface of the active layer 17 disposed on the buffer layer 15, and the light 53 thus arrived flows into the interior of the active layer 17.

When internal light flows into the active layer 17 of the thin film transistor, degradation occurs in the active layer 17, shortening the lifespan of the active layer 17, which ultimately shortens the lifespan of the entire device and causes failure. do.

In particular, such deterioration changes the threshold voltage (Vth) of the thin film transistor and causes negative shift (NBTiS), so a solution to the above problems is required.

The present invention is intended to solve the above-described problems, and seeks to provide an array substrate for a display device that minimizes the inflow of light into the active layer of a thin film transistor, thereby minimizing shortened lifespan and failure problems due to device deterioration.

The present invention also seeks to provide an array substrate for a display device that can minimize the negative shift (NBTiS) phenomenon of the threshold voltage (Vth) caused by light entering the active layer of a thin film transistor.

In order to achieve the above object, the present invention provides an array substrate for a display device according to the following embodiment.

It includes a substrate having a plurality of light-emitting regions and device regions, and buffer layers each disposed on the device regions of the substrate with a buffer layer disconnection region interposed therebetween. An active layer is disposed on the buffer layer, and an intermediate insulating layer is additionally disposed to cover the substrate including the buffer layer and the active layer.

At this time, due to the structure of the buffer layer having a disconnected island structure, light incident on the buffer layer disposed below the active layer is minimized, and thus light incident on the active layer can also be minimized, thereby minimizing deterioration and negative shift in the active layer. .

In addition, in order to achieve the above object, the present invention provides an array substrate for a display device of another embodiment as follows.

It includes a substrate having a plurality of light-emitting regions and device regions, and buffer layers each disposed on the device regions of the substrate with a buffer layer disconnection region interposed therebetween. An active layer is disposed on the buffer layer, and an intermediate insulating layer is disposed so as to cover the substrate including the buffer layer and the active layer in the device region with the intermediate insulating layer disconnection region interposed therebetween. In addition, a protective layer is additionally disposed to cover the substrate, including the intermediate insulating layer.

At this time, due to the double disconnected structure of the buffer layer and the intermediate insulating layer having a disconnected island structure, light incident on the buffer layer disposed below the active layer can be minimized, and light incident on the active layer can also be minimized, causing deterioration and negative effects in the active layer. Shifts can be minimized.

The array substrate for a display device according to the present invention has the effect of minimizing the deterioration of the active layer by minimizing the influx of internal light into the active layer of the thin film transistor.

In addition, the array substrate for a display device according to the present invention has the effect of minimizing the inflow of internal light into the active layer of the thin film transistor, thereby minimizing failure of the thin film transistor device due to shortening the lifespan of the active layer.

In addition, the array substrate for a display device according to the present invention has the effect of minimizing the negative shift (NBTiS) phenomenon of the threshold voltage occurring in the active layer.

In addition, the array substrate for a display device according to the present invention can create a structure that minimizes the influx of internal light into the active layer of a thin film transistor without an additional mask process, thereby minimizing the increase in production costs.

Figure 1 is a cross-sectional view showing an array substrate to which a conventional oxide semiconductor thin film transistor substrate is applied.
Figure 2 shows a cross-sectional view of an array substrate for a display device according to an embodiment of the present invention.
Figure 3 shows a cross-sectional view of an array substrate for a display device according to another embodiment of the present invention.
Figures 4 to 6 show simulation results for a comparative example in which the conventional buffer layer is not disconnected and is disposed on the entire surface of the substrate.
Figures 7 to 9 show simulation results for an embodiment in which the buffer layer according to the present invention is disconnected and has an island structure.
Figures 10 and 11 are graphs showing changes in threshold voltage (Vth) according to comparative examples and embodiments under the same NBTiS conditions.

The above-mentioned objects, features, and advantages will be described in detail later with reference to the attached drawings, so that those skilled in the art will be able to easily implement the technical idea of the present invention. In describing the present invention, if it is determined that a detailed description of known technologies related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

Hereinafter, the “top (or bottom)” of the substrate or the provision or arrangement of any component on the “top (or bottom)” of the substrate means that any component is provided or disposed in contact with the upper (or lower) surface of the substrate. In addition, it is not limited to not including other components between the substrate and any components provided or disposed on (or under) the substrate.

The array substrate for a display device according to the present invention can be applied to various gate methods, such as a top gate method and a bottom gate method. It can also be applied to various electronic devices, such as driving devices, switching devices, and other circuit components used in flat panel displays such as liquid crystal displays and organic light-emitting diode displays.

Hereinafter, a bottom emission type organic light emitting diode display device will be described as an example, but the present invention is not limited thereto.

In addition, an organic light emitting diode display panel generally includes an array substrate on which a plurality of organic light emitting diodes (OLEDs), pixel circuits that emit light, etc. are formed, and an encapsulation substrate that encapsulates the organic light emitting diodes. The present invention is particularly related to an array substrate, and the array substrate will be described in detail below.

Figure 2 shows a cross-sectional view of an array substrate for a display device according to an embodiment of the present invention.

An array substrate for a display device according to an embodiment of the present invention includes a substrate having a plurality of light emitting regions and a device region, and a buffer layer each disposed on the device region of the substrate with a buffer layer disconnection region interposed therebetween.

At this time, an active layer is disposed on the buffer layer, and a gate insulating layer and a gate electrode are sequentially stacked on the active layer. In addition, a light blocking layer is further included between the buffer layer and the substrate. At this time, an intermediate insulating layer is disposed to cover the substrate including the light blocking layer, buffer layer, active layer, gate insulating layer, and gate electrode.

Below, each component will be described in detail.

The array substrate 100 includes a substrate 111 having a plurality of light emitting areas (EA) and device areas (DA). Here, it does not mean that the light emitting area (EA) and the device area (DA) exist only on the substrate 111, and the area corresponding to the light emitting area (EA) and the device area (DA) defined on the front surface of the array substrate 100. This means that it also exists on the substrate 111.

The light emitting area EA is an area where an organic light emitting diode (OLED), which will be described later, is disposed, that is, an area where the first electrode layer 133, the organic material layer 137, and the second electrode layer 139 are stacked, and the organic material layer 137 ) refers to the area where light is emitted.

The device area (DA) refers to an area other than the light emitting area (EA), that is, an area where an organic light emitting diode (OLED) is not disposed, and is an area where various electronic devices such as driving transistors, capacitors, and circuit wiring are disposed.

Light emitted from the light emitting area (EA) may pass through the device area (DA), and the light emitting area (EA) and the device area (DA) are not distinguished by whether or not light passes through them.

In addition, the light emitting area (EA) and the device area (DA) are formed to correspond to one sub-pixel, and are arranged in a matrix form on the array substrate 100.

The substrate 111 may be made of various materials such as glass, silicon, and plastic. In the present invention using a bottom emission method, it is preferable to use a transparent glass substrate.

A light blocking layer 113 is disposed on the device area DA of the substrate 111. The light blocking layer 113 serves to block light from entering the active layer 117.

Specifically, it blocks external light incident from the bottom of the substrate 111. The light blocking layer 113 has an area equal to or larger than that of the active layer 117 to minimize the area where the active layer 117 is directly exposed to external light. It is desirable to form

The light blocking layer 113 may be made of any material that can block light, and is preferably made of a material other than an opaque metal or a metal with excellent electrical conductivity.

A buffer layer 115 is disposed on the light blocking layer 113.

The buffer layers 115 are disposed on a plurality of device areas DA. Specifically, they are disposed on the device area DA with the buffer layer disconnection area BNA interposed therebetween.

That is, the area where the buffer layer is placed (BA) and the buffer layer disconnected area (BNA) are alternately divided, so that the respective buffer layers 115 are not connected to each other and are spaced apart.

In this way, the buffer layer 115 is disposed in the device area (DA) rather than the emission area (EA), and is not disposed on the entire surface of the substrate 111, but because the multiple buffer layers 115 are disposed in a disconnected state from each other. Direct incident of light emitted from the emission area EA into the buffer layer 115 can be minimized.

Conventionally, the buffer layer 115 is also disposed in the light-emitting area EA, so that the light emitted from the light-emitting area EA is incident on the buffer layer 115, and the incident light undergoes total reflection within the buffer layer 115, ultimately forming the active layer 117. ), there were many cases where employees were hired. In addition, since the buffer layer 115 is connected as one layer, the light incident from the light emitting area EA to the buffer layer 115 has a structure in which continuous total reflection is more likely to occur.

However, in the embodiment according to the present invention, the buffer layer 115 is arranged in a disconnected form, that is, an island structure, in the device area DA, which is an area other than the light emitting area EA, so that the light emitting area (EA) Light directly incident from EA) to the buffer layer 115 can be minimized.

The buffer layer 115 serves to prevent external moisture or moisture from penetrating into the display device, and is preferably made of silicon oxide or silicon nitride.

Comparing the patterns of the buffer layer 115 and the light blocking layer 113, it is preferable that the light blocking layer 113 is patterned to have an area that is the same as or larger than the buffer layer 115.

First, in order for the buffer layer 115 and the light blocking layer 113 to have the same pattern (area), it is preferable to form the buffer layer 115 and the light blocking layer 113 through simultaneous etching.

When forming a pattern by simultaneously etching the buffer layer 115 and the light blocking layer 113, there is an advantage that a separate mask process is not required and additional costs for the bar production process are not incurred.

To this end, it is desirable that the buffer layer 115 and the light blocking layer 113 be made of materials with etch rates that are as similar as possible. In addition, the same area or same pattern here does not only mean completely physically identical, but also includes the range of errors in the tapered sides of each layer that may occur during the etching process or the range of minute errors in the overall area. It means to do.

Additionally, when the light blocking layer 113 is to have a larger area than the buffer layer 115, it is preferable to use a material whose etch rate of the buffer layer 115 is faster than that of the light blocking layer 113.

As described above, when the light blocking layer 113 is the same as the buffer layer 115 or has a larger area than the buffer layer 115, the surface of the buffer layer 115 exposed to the outside can be minimized, allowing light to enter the buffer layer 115. This can be minimized. If the surface on which light enters the buffer layer 115 is minimized in this way, the light incident on the active layer 117 can also be minimized.

The active layer 117 is disposed on the buffer layer 115.

The active layer 117 is a layer for forming a channel through which electrons move between a source electrode (not shown) and a drain electrode (not shown). In the present invention, the active layer 117 includes an oxide semiconductor.

Comparing the patterns of the active layer 117 and the buffer layer 115, it is preferable that the buffer layer 115 is patterned to have the same area as the active layer 117 or a larger area than the active layer 117.

First, in order for the active layer 117 and the buffer layer 115 to have the same pattern (area), it is preferable to form the active layer 117 and the buffer layer 115 through simultaneous etching. When forming a pattern by simultaneously etching the active layer 117 and the buffer layer 115, there is an advantage that a separate mask process is not required and additional costs for the production process are not incurred.

To this end, it is desirable that the active layer 117 and the buffer layer 115 be made of materials with etch rates that are as similar as possible. However, the meaning of the same pattern here does not only mean that it is completely physically identical, but also includes the error range on the tapered sides of each layer or the minute error range in the overall area that may occur during the etching process. do.

Additionally, when the buffer layer 115 is to have a larger area than the active layer 117, it is preferable to use a material whose etching rate of the active layer 117 is faster than that of the buffer layer 115.

As described above, when the buffer layer 115 is the same as the active layer 117 or has a larger area than the active layer 117, the surface of the active layer 117 exposed to the outside can be minimized, preventing light incident on the active layer 117. It can be minimized.

The gate insulating layer 119 and the gate electrode layer 121 are sequentially stacked on some areas of the active layer 117, and some areas of the active layer 117 are connected to the wiring electrodes 125 (S/D electrodes). At this time, the active layer 117, gate insulating layer 119, gate electrode layer 121, and wiring electrode 125 (S/D electrode) constitute a thin film transistor (Tr).

Specifically, the gate insulating layer 119 is disposed on the active layer 117, and the gate electrode layer 121 is disposed on the gate insulating layer 119.

The gate insulating layer 119 is disposed on the active layer 117 and has a smaller area than the active layer 117. The gate insulating layer 119 is also disposed in the device area DA like the buffer layer 115 and is formed in a disconnected state from the gate insulating layer 119 in another device area DA. In this way, the gate insulating layer 119 also has an island structure in a disconnected state, so that light that can be incident through the gate insulating layer 119 is minimized, thereby minimizing light incident on the lower active layer 117.

In this way, the buffer layer 115 is placed below the active layer 117 and the gate insulating layer 119 is arranged in an island structure on the top to minimize the possibility of light entering the layers to prevent deterioration of the active layer 117. It can be minimized.

The gate insulating layer 119 may be made of various materials, such as a silicon (Si)-based oxide film, a nitride film, or a compound containing the same, or a metal oxide film containing Al ₂ O ₃ .

An intermediate insulating layer 123 is disposed to cover the substrate 111 including the previously described light blocking layer 113, buffer layer 115, active layer 117, gate insulating layer 119, and gate electrode 121. The electrode wire 125 is disposed on the middle insulating layer 123 and is directly connected to the active layer 117 through the middle insulating layer 123.

Specifically, the middle insulating layer 123 covers all layers in contact with the externally exposed surfaces of the light blocking layer 113, buffer layer 115, active layer 117, gate insulating layer 119, and gate electrode 121. It is arranged so that However, as described above, through holes for connecting the electrode wiring 125 to the active layer 117 are excluded.

At this time, the middle insulating layer 123 and the buffer layer 115 are preferably made of different materials, and the middle insulating layer 123 and the gate insulating layer 119 are also preferably made of different materials.

This is explained in detail as follows. As shown in FIG. 2, the intermediate insulating layer 123 is disposed to cover the substrate 111, so a portion of the intermediate insulating layer 123 is disposed in the light emitting area EA. At this time, some of the light 161 emitted from the light emitting area EA is incident on the middle insulating layer 123 and continues to propagate within the middle insulating layer 123 through total reflection.

At this time, the light trapped in the middle insulating layer 123 may eventually reach the buffer layer 115 and the gate insulating layer 119, etc., which are in contact with the middle insulating layer 123. In this case, the layers form disconnected layers from each other. Because of this, most of the light does not pass through the layers and is reflected again.

That is, the middle insulating layer 123, buffer layer 115, and gate insulating layer 119 have different interfaces and hardly transmit light. Accordingly, light incident on the active layer 117 through the buffer layer 115 and the gate insulating layer 119 can be minimized, thereby minimizing deterioration of the active layer 117.

In addition, when the intermediate insulating layer 123, the buffer layer 115, and the gate insulating layer 119 are made of different materials, light does not transmit easily at the boundary surface of materials with different media and reflection occurs, thereby forming the active layer 117. ) can be minimized.

That is, the intermediate insulating layer 123, the buffer layer 115, and the gate insulating layer 119 form a disconnected interface between each other, and if they are formed of different materials, the reflectance of light at the interface is further increased to form the active layer 117. It is effective in minimizing the incidence of light into.

Additional layers will be briefly explained. A protective layer 127 is disposed on the intermediate insulating layer 123, and color filters 129r, 129g, and 129b are disposed in the protective layer 127 to correspond to the light emitting area EA.

The overcoat layer 131 is disposed to cover the protective layer 127 and the color filters 129r, 129g, and 129b, and the protective layer 127 and the overcoat layer are placed on the overcoat layer 131 to be directly connected to the wiring electrode 125. A first electrode layer 133 penetrating 131 is disposed. In the first electrode layer 133, a bank layer 135 is disposed on the device area DA, and an organic material layer 137 is disposed on the emission area EA.

A second electrode layer 139 connected by one electrode is disposed on the bank layer 135 and the organic material layer 137 over the entire surface of the array substrate 100. At this time, the first electrode layer 133, the organic material layer 137, and the second electrode layer 139 constitute an organic light emitting diode (OLED) that emits light.

Figure 3 shows a cross-sectional view of an array substrate for a display device according to another embodiment of the present invention.

In the description of the embodiment according to FIG. 3, additional description will be omitted for parts that are the same as the embodiment according to FIG. 2, and the description will focus on the differences.

The array substrate for a display device according to an embodiment of FIG. 3 includes a substrate having a plurality of light-emitting regions and device regions, and buffer layers respectively disposed on the device regions of the substrate with a buffer layer disconnection region interposed therebetween. An active layer is disposed on the buffer layer. At this time, the intermediate insulating layer is disposed in the device area with the intermediate insulating layer disconnection region in between, and is disposed to cover the substrate including the buffer layer and the active layer. In addition, the protective layer is disposed to cover the substrate, including the intermediate insulating layer.

The intermediate insulating layers 123 according to FIG. 3 are disposed on a plurality of device areas DA. Specifically, they are disposed on the device area DA with the intermediate insulating layer disconnection area INA interposed therebetween. That is, the area (IA) where the intermediate insulating layer is disposed and the intermediate insulating layer disconnection area (INA) are alternately divided, so that the intermediate insulating layers 123 are not connected to each other but are spaced apart.

In this way, the intermediate insulating layer 123 is disposed in the device area (DA) rather than the light emitting area (EA), so that rather than being disposed on the entire surface of the substrate 111, the plurality of intermediate insulating layers 123 are disposed in a disconnected state from each other. Therefore, direct incident of light emitted from the light emitting area EA into the intermediate insulating layer 123 can be minimized.

In the case of the present embodiment according to FIG. 3, the buffer layer 115 disposed below the active layer 115 and the gate insulating layer 119 disposed above both have a disconnected island structure, and the middle insulating layer 123 covers them. In addition, it has a disconnected island structure, allowing light incident on the active layer 115 to be further minimized.

Moreover, since the middle insulating layer 123 is disposed only in the device area DA, it is possible to minimize light directly emitted from the light emitting area EA from being incident on the middle insulating layer 123.

The protective layer 127 is disposed to cover the substrate 111 including the intermediate insulating layer 123. At this time, a portion of the protective layer 127 is disposed in the light emitting area (EA) so that the emitted light can be directly incident. This incident light 171 is totally reflected inside the protective layer 127, and a portion of the light is reflected in the intermediate insulating layer. It meets the interface of (123).

At this time, the protective layer 127 and the intermediate insulating layer 123 are preferably made of different materials to further increase the reflectance of light at different interfaces.

If the middle insulating layer 123 is disconnected and is made of a different medium from the protective layer 127, most of the light is reflected at the interface with the middle insulating layer 123. Even if some of the light enters the intermediate insulating layer 123, it again encounters the interface between the buffer layer 115 and the gate insulating layer 119, so the light directly incident to the active layer 117 can be further minimized. there is.

Figures 4 to 6 show results obtained through a simulation program for a comparative example in which the conventional buffer layer was not cut off but was disposed on the front surface of the substrate.

Specifically, Figure 4 shows the results of a simulation program showing the light intensity distribution for a comparative example in which the conventional buffer layer is not disconnected and the buffer layer is disposed on the entire surface of the substrate. An OLED light source was used as the light source, and the intensity of light in area A where the active layer was placed was measured.

FIG. 5 is an enlarged view of area A in FIG. 4 where the active layer is disposed. As shown in the figure, it can be seen that the brightness of the light of the active layer 217 disposed on the buffer layer 215 is measured to be relatively very bright compared to the surrounding area.

In particular, the buffer layer 215 also appears bright, showing that the light emitted from the light source is reflected within the buffer layer 215.

Figure 6 shows the intensity of light according to the distance from the active layer 217 using the detector 210. It can be seen that the closer the light is to the active layer 217, the brighter the light is, and the brightest intensity of the light is 0.000073. . For reference, the unit of distance here is nm. The detector 201 is used to measure the amount of light at a specific point, and the simulation program causes the detector 210 to measure the amount of light at the designated point.

Figures 7 to 9 show results obtained through a simulation program for an embodiment in which the buffer layer is disconnected and has an island structure, as in the present invention.

Specifically, Figure 7 shows the results of a simulation program showing the light intensity distribution for an embodiment in which the buffer layer is disconnected and has an island structure. An OLED light source was used as the light source, and the intensity of light in area B where the active layer was placed was measured.

FIG. 8 is an enlarged view of area B in FIG. 7 where the active layer is disposed. As shown in the figure, it can be seen that the brightness of the light of the active layer 217 disposed on the buffer layer 215 is measured to be relatively very dark compared to the surrounding area.

In particular, the buffer layer 215 also appears very dark, and it can be seen that almost no light emitted from the light source enters the disconnected buffer layer 215. Accordingly, it can be directly confirmed that the light incident on the active layer 217 through the buffer layer 215 can be minimized.

Figure 9 shows the intensity of light measured according to the distance from the active layer 217 using the detector 210. It can be seen that the brightest intensity according to the distance from the active layer 217 is 0.000034. In other words, it can be directly confirmed that the brightness is less than half compared to 0.000073, which is the intensity of light confirmed in Figure 6 above.

Figures 10 and 11 are graphs showing changes in threshold voltage (Vth) for the comparative example shown in Figure 4 and the example shown in Figure 7, respectively, under the same NBTiS conditions.

In the case of the comparative example according to FIG. 10, the threshold voltage (Vth) is measured as -3.84V, and in the case of the embodiment according to FIG. 11, the threshold voltage (Vth) is measured as 0.80V.

That is, in the case of the comparative example, it can be confirmed that a negative shift occurred from 0.80V to -3.84V when compared to the example.

Although the above description focuses on the embodiments of the present invention, various changes and modifications can be made at the level of those skilled in the art. Accordingly, it will be understood that such changes and modifications are included within the scope of the present invention as long as they do not depart from the scope of the present invention.

EA: Emission area DA: Device area
BNA: Buffer layer disconnection area INA: Intermediate insulating layer disconnection area
10, 100: array substrate 11, 111: substrate
13, 113: light shielding film 15, 115: buffer layer
17, 117: active layer 19, 119: gate insulating layer
21, 121: gate electrode 23, 123: intermediate insulating layer
25, 125: wiring electrode 27, 127: protective layer
29, 129b, 129r, 129g: color filter 31, 131: overcoat layer
33, 133: first electrode 35, 135: bank layer
37, 137: organic material layer 39, 139: second electrode

Claims (9)

delete A substrate having multiple light emitting areas and device areas;
a buffer layer disposed in the device region with a buffer layer disconnection region therebetween;
an active layer disposed on the buffer layer;
a gate insulating layer disposed on the active layer;
a gate electrode layer disposed on the gate insulating layer;
an intermediate insulating layer located in the device region with an intermediate insulating layer disconnection region in between, and disposed to cover the buffer layer, the active layer, the gate insulating layer, and the gate electrode layer;
a protective layer disposed to cover the intermediate insulating layer and the substrate; and
a bottom-emitting organic light-emitting diode disposed in the light-emitting area on the protective layer and irradiating light in the direction of the protective layer; Including,
The intermediate insulating layer is disposed so as not to overlap the light emitting area.
delete According to paragraph 2,
The display device further includes a light blocking layer disposed between the buffer layer and the substrate.
According to paragraph 4,
The light blocking layer is disposed in the device area of the substrate,
A display device having an area equal to or larger than that of the buffer layer.
According to paragraph 2,
A display device wherein the buffer layer has an area equal to or larger than that of the active layer.
According to paragraph 2,
A display device wherein the active layer includes an oxide semiconductor.
According to paragraph 2,
The display device wherein the buffer layer and the intermediate insulating layer are made of different materials.
According to paragraph 2,
The display device wherein the gate insulating layer and the intermediate insulating layer are made of different materials.

Images