KR102615808B1 - Gruop 3 nitride semiconductor template manufacturing method and manufactured semiconductor template thereof - Google Patents

Abstract

The present invention relates to a method for manufacturing a group III nitride semiconductor template, comprising: a first step of preparing a growth substrate and a support substrate; A second step of growing a semiconductor layer on the growth substrate; A third step of forming a first bonding layer on the semiconductor layer; A fourth step of forming a second bonding layer on the support substrate; A fifth step of forming a bonding layer by bonding the first bonding layer and the second bonding layer to each other; A sixth step of separating the growth substrate from the semiconductor layer; and a seventh step of forming a conversion layer on the semiconductor layer to change the surface polarity of the semiconductor layer to the Group 3 metal polarity.
According to the present invention, a high heat dissipation support substrate having the same or similar coefficient of thermal expansion (CTE) as the group 3 nitride semiconductor layer and a single crystal growth layer for forming the group 3 nitride semiconductor layer can be combined through a high heat-resistant bonding layer. Therefore, it is possible to form a high-quality Group 3 nitride semiconductor layer at a high temperature of 700°C or higher. In other words, the Group 3 nitride semiconductor layer and the support substrate can have the same or similar lattice constant and coefficient of thermal expansion (CTE), so structural and thermo-mechanical stress that occurs during growth can be minimized. .

Description

Group 3 nitride semiconductor template manufacturing method and semiconductor template manufactured thereby {GRUOP 3 NITRIDE SEMICONDUCTOR TEMPLATE MANUFACTURING METHOD AND MANUFACTURED SEMICONDUCTOR TEMPLATE THEREOF}

The present invention relates to a method for manufacturing a group 3 nitride semiconductor template and a semiconductor template manufactured thereby. More specifically, the present invention relates to a method of manufacturing a group 3 nitride semiconductor template, and more specifically, to a high-quality semiconductor layer using a laser lift off (LLO) technique. It relates to a method for manufacturing a group III nitride semiconductor template that can be formed on an equal or similar high heat dissipation support substrate and a semiconductor template manufactured thereby.

Conventional group III nitride semiconductor thin film materials and their power semiconductor device structures are grown and formed on top of Si single crystal wafers for growth substrates. In this case, AlN suppresses re-melting through reaction with the Si single crystal wafer surface layer. Si re-melting prevention film area containing material system (nitride or nitride oxide with Al composition), transition area for tensile stress relief including AlGaN material system (Group 3 nitride with Al or Ga composition), and GaN material system (group containing Ga composition) It has a structure in which the active regions of a power semiconductor containing group 3 nitrides are stacked in order. Here, the (111) plane, which has the densest Si atomic bonds, is preferentially used as the crystal plane of the Si single crystal wafer, but the (110) or (100) plane can also be used depending on the application product.

Typically, MOCVD (Metal Organic Chemical Vapor Deposition) equipment is used to grow and form GaN material-based single crystal thin films and power semiconductor device structures on Si single crystal wafers for Group 3 nitride power semiconductor growth substrates. At this time, high temperatures around 1000°C and reduction are used. Basically, the GaN material-based single crystal thin film growth (film formation) process containing gallium (Ga) atoms is carried out in an atmosphere (H ₂ , H ⁺ , NH ₃ , radical ions), and the relatively thin film between the surface layer of the Si single crystal wafer and the gallium (Ga) atoms is performed. A Si re-melting prevention film area that blocks active Si-Ga metallic eutectic reactions with small energy is absolutely necessary. The Si re-melting area described above is representative of the AlN material layer grown through an in-situ process within the MOCVD chamber, but in addition, other external film formation (growth) process equipment (Sputter, PLD, ALD) is used. Before loading into the MOCVD chamber, an AlN or AlNO material layer can be formed on the Si single crystal wafer for a group III nitride power semiconductor growth substrate through an ex-situ process. On the other hand, when growing (film forming) an AlN material system, the surface of the Si single crystal wafer is damaged to create an electrically conductive interface through a Si-Al metallic process reaction, or the AlN material system is grown to a thickness of around 50 nm. If the crystal quality deteriorates during (film formation) and growth of the active region of a GaN material-based power semiconductor, adverse effects may occur that may promote leakage current and dielectric breakdown in the vertical direction of the Si single crystal wafer, so special caution is required.

In addition, when growing (or forming a film) a material, the process must be carried out by considering the lattice constant (LC) and the coefficient of thermal expansion (CTE), which are the material's intrinsic values between different heterogeneous materials. When the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between two materials is large, microscopic particles are formed within the thin film of the grown material due to structural and thermo-mechanical stress during or after the growth (film formation) process. Alternatively, macro cracks inevitably occur or crystal quality deteriorates. In particular, when growing (filming) a GaN material system directly on top of a Si single crystal wafer for a Group 3 nitride power semiconductor growth substrate, large tensile stress is simultaneously generated in terms of lattice constant and thermal expansion coefficient, making it easy to observe cracking. You can. Several technologies have been disclosed as a method of relieving the above-mentioned tensile stress or suppressing cracks, but this is a method of introducing materials and processes that artificially generate compressive stress to compensate for the tensile stress, as described above. A transition area for relieving tensile stress that suppresses cracking is being introduced and used by stacking AlGaN material containing Al or Ga composition in a multi-layer structure on a Si re-melting prevention film area. However, when introducing and using the AlGaN material system for relieving tensile stress described above, there is still a limit to sufficient thickness increase, and it is still insufficient to improve the performance and quality of group 3 nitride power semiconductors.

In addition, the active area of a GaN material-based power semiconductor typically consists of 1) GaN buffer layer (horizontal and vertical transistor), 2) GaN channel layer (horizontal transistor) or drift layer (vertical transistor). ), 3) AlGaN Barrier Layer (horizontal transistor) or p-type Nitride Semiconductor Layer (vertical transistor), 4) Capping Passivation Layer (horizontal transistor) or p It is formed by stacking four regions of a nitride semiconductor layer (horizontal transistor) or a capping passivation layer (vertical transistor). However, it is desirable to make the areas 2) and 3) as thick as possible, with a thickness of 3㎛ or more, in order to reduce crystal defects such as threading dislocations, but the Si re-melting prevention film area and the transition area for tensile stress relief are Even if it is grown (film formed), the difference in thermal expansion coefficient between the Si single crystal wafer for the Group 3 nitride power semiconductor growth substrate and the GaN material system is so large that it is difficult to grow (film formed) to a certain thickness indefinitely due to strong tensile stress.

Next, conventional group III nitride semiconductor thin film materials and their power semiconductor device structures are grown and formed on the AlN ceramic template for the growth substrate. In this case, a polycrystalline AlN ceramic substrate, an oxide bonding layer, and a transfer layer are formed. It has a structure in which a single crystal Si thin film (or thick film) layer, a Si re-melting prevention film region containing AlN material, a transition region for relieving condensation stress, and a GaN material-based power semiconductor active region are stacked in that order. Here, the polycrystalline AlN ceramic substrate uses polycrystalline AlN (4.5ppm) ceramic, which has a thermal expansion coefficient similar to that of GaN, to overcome the large difference in thermal expansion coefficient between the Si single crystal wafer (2.8ppm) and the GaN (5.6ppm) material system. In addition, the oxide bonding layer uses a SiO ₂ material system that does not change in physical properties and external shape for a long time in a MOCVD film formation or growth process chamber (high temperature reducing atmosphere) as a bonding layer between wafer substrates.

In addition, the single-crystal Si thin film (or thick film) transferred onto the polycrystalline AlN ceramic substrate serves as a growth substrate for growing the active region of the GaN material-based power semiconductor. The Si single crystal wafer is sliced and transferred to a thinner thickness, which is generally known as Smart-cut technology, and is a heterogeneous material using Hydrogen Ion Implant & SiO ₂ wafer bonding layer. It is the same technology as SOI (Si on Insulator) and POI (Piezoelectric on Insulator) using wafer bonding technology.

The above-described GaN material-based thin film material and the AlN ceramic template used as a growth substrate wafer for power semiconductor device structure have a structure with a Si single crystal thin film (or thick film) transferred to the uppermost layer, and ultimately form the Group 3 nitride power semiconductor described in detail previously. As with Si single crystal wafers for growth substrates, before growing GaN thin film materials and their power semiconductor device structures, a Si re-melting prevention film area and a transition area for tensile stress relief are basically required. However, although the material type, composition, and thickness may be somewhat different in each area, major technical issues such as remelting and tensile stress generated from differences in lattice constants on the upper part of the transferred Si single crystal thin film (or thick film) are discussed in Group 3 above. It is the same as Si single crystal wafer for nitride power semiconductor growth substrate. In other words, by using a polycrystalline AlN ceramic substrate with a thermal expansion coefficient similar to that of the GaN material system, the disadvantages (maximization of thickness, cracks) caused by the difference in thermal expansion coefficient described in the existing Si wafer-based GaN material-based power semiconductor device for growth substrates (maximization of thickness, cracks) are partially overcome. Although it is possible, as in the case of Si single crystal wafers for Group 3 nitride power semiconductor growth substrates, high-density crystal defects resulting from the difference in lattice constants between Si and GaN material systems and residual stress existing in the active region of GaN material-based power semiconductor systems cannot be resolved. Quality problems are still serious.

Republic of Korea Patent Publication No. 10-2122846

The purpose of the present invention is to solve the above-described conventional problems, by using the Laser Lift Off (LLO) technique to form a high-quality Group III nitride semiconductor layer with the same or similar lattice constant and thermal expansion coefficient. The present invention provides a method for manufacturing a Group 3 semiconductor template that can be formed on an upper part of a heat dissipation support substrate and a semiconductor template manufactured thereby.

The above object is, according to the present invention, a first step of preparing a growth substrate and a support substrate; A second step of growing a semiconductor layer on the growth substrate; A third step of forming a first bonding layer on the semiconductor layer; A fourth step of forming a second bonding layer on the support substrate; A fifth step of forming a bonding layer by bonding the first bonding layer and the second bonding layer to each other; A sixth step of separating the growth substrate from the semiconductor layer; and a seventh step of forming a conversion layer on the semiconductor layer to change the surface polarity of the semiconductor layer to the Group 3 metal polarity.

Additionally, in the sixth step, the growth substrate can be separated from the semiconductor layer using a laser lift off (LLO) technique.

Additionally, the present invention may further include an eighth step of growing a device active layer on the conversion layer.

Additionally, in the seventh step, a plurality of patterns may be etched into the conversion layer.

Additionally, in the seventh step, a plurality of regular patterns may be etched on the semiconductor layer, and the transition layer may be formed along the pattern of the semiconductor layer.

Additionally, in the seventh step, a plurality of irregular patterns may be etched on the semiconductor layer, each end of the pattern may be flattened, and then the transition layer may be formed along the pattern of the semiconductor layer.

In addition, the first bonding layer and the second bonding layer each include a bonding reinforcement layer for strengthening the bond with the support substrate or the semiconductor layer, and a bonding reinforcement layer for alleviating roughness of the surface of the support substrate or the semiconductor layer. It may include a surface planarization layer and a bonding layer for bonding the first bonding layer and the second bonding layer to each other.

Additionally, the support substrate may be a polycrystalline AlN ceramic substrate.

The above object is, according to the present invention, a first step of preparing a growth substrate, a temporary substrate, and a support substrate; A second step of growing a semiconductor layer on the growth substrate; A third step of forming a first adhesive layer on the semiconductor layer; A fourth step of forming a second adhesive layer on the temporary substrate; A fifth step of forming an adhesive layer by adhering the first adhesive layer and the second adhesive layer to each other; A sixth step of separating the growth substrate from the semiconductor layer; A seventh step of converting the rough surface of the semiconductor layer from which the growth substrate is separated into a mirror-like surface; An eighth step of forming a first bonding layer on the semiconductor layer; A ninth step of forming a second bonding layer on the support substrate; A tenth step of forming a bonding layer by bonding the first bonding layer and the second bonding layer to each other; An 11th step of separating the temporary substrate from the adhesive layer; and a twelfth step of separating the adhesive layer from the semiconductor layer.

Additionally, in the sixth step, the growth substrate is separated from the semiconductor layer using a laser lift off (LLO) technique, and in the eleventh step, the temporary substrate is separated using a laser lift off technique. It can be separated from the adhesive layer.

Additionally, the present invention may further include a thirteenth step of growing a device active layer on the semiconductor layer.

Additionally, in the seventh step, the semiconductor layer can be mirror-finished by forming a planarization layer on the semiconductor layer and then planarizing the planarization layer.

Additionally, in the seventh step, the semiconductor layer can be mirror-finished by directly planarizing the upper surface of the semiconductor layer.

In addition, in the seventh step, a plurality of patterns are etched on the upper surface of the semiconductor layer, a first planarization layer is formed according to the pattern of the semiconductor layer, and a second planarization layer is formed on the first planarization layer. , the semiconductor layer can be mirror-finished by planarizing the first planarization layer or the second planarization layer.

In addition, the first bonding layer and the second bonding layer each include a bonding reinforcement layer for strengthening the bond with the support substrate or the semiconductor layer, and a bonding reinforcement layer for alleviating roughness of the surface of the support substrate or the semiconductor layer. It may include a surface planarization layer and a bonding layer for bonding the first bonding layer and the second bonding layer to each other.

Additionally, the support substrate may be a polycrystalline AlN ceramic substrate.

The above object is achieved by a group III nitride semiconductor template manufactured by a group III nitride semiconductor template manufacturing method according to the present invention.

According to the present invention, a high heat dissipation support substrate having the same or similar coefficient of thermal expansion (CTE) as the group 3 nitride semiconductor layer, a high quality group 3 nitride thin film material, and a group 3 nitride for growing a power semiconductor device structure using the same. Since the single crystal growth layer can be bonded through a high heat-resistant bonding layer, it is possible to form a high-quality Group III nitride semiconductor layer at a high temperature of 700°C or higher. In other words, the Group 3 nitride thin film material, the power semiconductor device structure using the same, and the support substrate may have the same or similar lattice constant (LC) and coefficient of thermal expansion (CTE), so the structural and thermo-mechanical factors that occur during growth are affected. Stress (Thermo-mechanical Induced Stress) can be minimized.

In addition, according to the present invention, the high heat dissipation support substrate is made of polycrystalline ceramic, so it has an advantage in terms of cost competitiveness compared to single crystalline ceramic.

Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within the range apparent to those skilled in the art from the contents described below.

1 shows a semiconductor template manufactured by the Group 3 semiconductor template manufacturing method according to the first to fourth embodiments of the present invention;
Figure 2 shows a device active layer grown on a semiconductor template manufactured by the Group 3 semiconductor template manufacturing method according to the first to fourth embodiments of the present invention;
Figure 3 is a flowchart of a method for manufacturing a Group 3 semiconductor template according to the first embodiment of the present invention;
Figure 4 shows the process of manufacturing a semiconductor template according to the Group 3 semiconductor template manufacturing method according to the first embodiment of the present invention;
Figure 5 is a flowchart of a group 3 semiconductor template manufacturing method according to the second embodiment of the present invention;
Figure 6 shows the process of manufacturing a semiconductor template according to the Group 3 semiconductor template manufacturing method according to the second embodiment of the present invention;
Figure 7 is a flow chart of a group 3 semiconductor template manufacturing method according to the third embodiment of the present invention;
Figure 8 is a flow chart of a group 3 semiconductor template manufacturing method according to the fourth embodiment of the present invention;
Figure 9 shows in detail the first bonding layer and the second bonding layer of the semiconductor template manufacturing method according to the first to fourth embodiments of the present invention;
Figure 10 shows the first case of the seventh step of the semiconductor template manufacturing method according to the first or third embodiment of the present invention;
Figure 11 shows the second case of the seventh step of the semiconductor template manufacturing method according to the first or third embodiment of the present invention;
Figure 12 shows the third case of the seventh step of the semiconductor template manufacturing method according to the first or third embodiment of the present invention;
Figure 13 shows the first case of the seventh step of the semiconductor template manufacturing method according to the second or fourth embodiment of the present invention;
Figure 14 shows the second case of the seventh step of the semiconductor template manufacturing method according to the second or fourth embodiment of the present invention;
Figure 15 shows the third case in the seventh step of the semiconductor template manufacturing method according to the second or fourth embodiment of the present invention;
Figure 16 shows that in the third case of the seventh step of the semiconductor template manufacturing method according to the second or fourth embodiment of the present invention, the degree of planarization is adjusted in three cases.

Hereinafter, some embodiments of the present invention will be described in detail through illustrative drawings. When adding reference numerals to components in each drawing, it should be noted that identical components are given the same reference numerals as much as possible even if they are shown in different drawings.

Additionally, when describing embodiments of the present invention, if detailed descriptions of related known configurations or functions are judged to impede understanding of the embodiments of the present invention, the detailed descriptions will be omitted.

Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, or order of the component is not limited by the term.

From now on, with reference to the attached drawings, the group III nitride semiconductor template manufacturing method (S100) according to the first embodiment of the present invention will be described in detail.

Figure 1 shows a semiconductor template manufactured by the group 3 semiconductor template manufacturing method according to the first to fourth embodiments of the present invention, and Figure 2 shows the first to fourth embodiments of the present invention. It shows that a device active layer is grown on a semiconductor template manufactured by a group 3 semiconductor template manufacturing method according to , and Figure 3 is a flowchart of the group 3 semiconductor template manufacturing method according to the first embodiment of the present invention. Figure 4 shows the process of manufacturing a semiconductor template according to the Group 3 semiconductor template manufacturing method according to the first embodiment of the present invention.

As shown in Figures 1 to 4, the group 3 nitride semiconductor template manufacturing method (S100) according to the first embodiment of the present invention is initially grown on the growth substrate (G), the group 3 nitride semiconductor layer (C) ) relates to a semiconductor template manufacturing method in which the polarity of the surface and the surface of the group III nitride semiconductor layer (C) finally formed on the support substrate (S) are different (i.e., opposite), in the first step (S101) , the second step (S102), the third step (S103), the fourth step (S104), the fifth step (S105), the sixth step (S106), and the seventh step (S107), It includes the eighth step (S108).

The first step (S101) is a step of preparing the growth substrate (G) and the support substrate (S).

The growth substrate (G) is an optically transparent substrate through which a laser (single wavelength light) beam is 100% transmitted (in theory) without absorption after the Group 3 nitride semiconductor layer (C) is grown. In the present disclosure, aluminum oxide (Al ₂ It is limited to single crystalline sapphire material (Al ₂ O ₃ , ScAlMgO ₄ ) substrates containing O ₃ ).

After going through each step of the group 3 nitride semiconductor template manufacturing method (S100) according to the first embodiment of the present invention, the support substrate (S) is formed of a group 3 nitride semiconductor layer (C) and a group 3 nitride semiconductor device active layer ( It is a substrate that supports (U), and this support substrate (S) is composed of multiple layers, has high heat dissipation ability (over 60W/mK), and has a group 3 nitride semiconductor layer (C) and coefficient of thermal expansion (CTE, ppm). It can be formed of a material equal to or less than (5.6 ppm), and can be formed with a polycrystalline or single crystalline microstructure.

More specifically, the support substrate S is made of at least one material selected from materials including silicon (Si), silicon carbide (SiC), silicon nitride (SiN _x ), aluminum nitride (AlN), and gallium nitride (GaN). It can be included. Here, the heat dissipation capacity of silicon (Si) is 149 W/mK, the heat dissipation ability of silicon carbide ( _SiC ) is 300~450 W/mK, the heat dissipation ability of silicon nitride (SiN The heat dissipation capacity of gallium nitride (GaN) is 170~210W/mK, the thermal expansion coefficient of silicon (Si) is 2.6ppm, the thermal expansion coefficient of silicon carbide (SiC) is 4.8ppm, and the heat dissipation ability of gallium nitride (GaN) is 170~210W/mK. _x ) has a thermal expansion coefficient of 3.7ppm, aluminum nitride (AlN) has a thermal expansion coefficient of 4.5ppm, and gallium nitride (GaN) has a thermal expansion coefficient of 5.6ppm, each suitable as a material for a high heat dissipation support substrate (S). In addition, silicon (Si), silicon carbide ( _SiC ), silicon nitride (SiN It is desirable to form a coarse polycrystalline microstructure, which has the advantage of securing cost competitiveness.

The second step (S102) is a step of growing the group III nitride semiconductor layer (C) as a single layer or multilayer on the growth substrate (G).

Here, the group 3 nitride semiconductor layer (C) is basically electrically insulating without dopant, but in some cases, it is electrically conductive and contains a dopant as a means to minimize crystal defects. It serves as a seed for growing Group 3 nitride thin film materials and power semiconductor device structures using them.

Here, the surface of the group 3 nitride semiconductor layer (C) formed on the growth substrate (G) and the surface of the group 3 nitride semiconductor layer (C) later transferred to the top of the support substrate (S) are reversed ( Inversion), it is desirable to form a microstructure by treating the surface of the growth substrate (G) so that a desired surface of the semiconductor layer (C) can be formed. For example, in the case of a gallium nitride (GaN) semiconductor layer (C), the gallium polarity (Ga-polarity) or nitrogen polarity (N-polarity) surface can be selectively adjusted depending on the surface treatment and growth conditions of the growth substrate (G). You can. Typically, when a group III nitride semiconductor layer (C) is grown in a MOCVD chamber on a sapphire growth substrate wafer, a surface with a polarity of a metal (M; Ga, Al, In) with three valence electrons is formed. On the other hand, the interface directly contacting the sapphire growth substrate has nitrogen polarity with 5 valence electrons.

The third step (S103) is a step of forming the first bonding layer (B1) on the group 3 nitride semiconductor layer (C). Here, the first bonding layer (B1) is a metal or alloy such as aluminum (Al), tungsten (W), molybdenum (Mo), silicon oxide (SiO _x ), silicon nitride (SiN _x ), or aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon (Si), zinc oxide (ZnO), C ₆₀ (Fullerene), or furthermore, to improve surface roughness _, a flowable oxide (FO In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

The fourth step (S104) is a step of forming the second bonding layer (B2) on the support substrate (S). Here, the second bonding layer (B2) is a metal or alloy such as aluminum (Al), tungsten (W), molybdenum (Mo), silicon oxide (SiO _x ), silicon nitride (SiN _x ), or aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon (Si), zinc oxide (ZnO), C ₆₀ (Fullerene), or furthermore, to improve surface roughness _, a flowable oxide (FO In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

Meanwhile, each of the first bonding layer (B1) and the second bonding layer (B2) may include a bonding reinforcement layer (R), a surface planarization layer (F), and a bonding layer (J).

Figure 9 shows in detail the first bonding layer (B1) and the second bonding layer (B2) of the Group 3 semiconductor template manufacturing method according to the first to fourth embodiments of the present invention.

As shown in Figure 9, the bonding reinforcement layer (R) is a group 3 nitride semiconductor layer (C) (in the case of the first bonding layer (B1)) or a support substrate (S) (in the case of the second bonding layer (B2)). In order to strengthen the bond with each other, this bond reinforcement layer (R) is, for example, silicon oxide (SiO _x ), silicon nitride (SiN _x ), chromium (Cr), titanium (Ti), molybdenum Mo), may include HMDS.

The surface planarization layer (F) is used to alleviate the roughness of the surface of the group 3 nitride semiconductor layer (C) or the support substrate (S), respectively. This surface planarization layer (F) is used, for example, to improve surface roughness. It may include silicon oxide (SiO _x ), silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and amorphous or polycrystalline silicon (Si). Furthermore, it may further include a flowable oxide (FO _x ) such as SOG (Spin On Glass) and HSQ (Hydrogen Silsesquioxane).

The bonding layer (J) is for bonding the first bonding layer (B1) and the second bonding layer (B2) to each other, and may be prepared with a permanent bonding material, such as aluminum (Al) or tungsten (W). ), metals or alloys such as molybdenum (Mo), silicon oxide (SiO _x ), silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon (Si), zinc oxide (ZnO), C ₆₀ (Fullerene), or even SOG (Spin) to improve surface roughness. On Glass), HSQ (Hydrogen Silsesquioxane), etc. may additionally include a flowable oxide (FO _x ). In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

On the other hand, the above-described bonding reinforcement layer (R) and surface planarization layer (F) can be selectively introduced or deleted depending on the process, and when the bonding strengthening layer (R) and surface planarization layer (F) are deleted depending on the process, , the bonding layer (J) can be formed directly with the group 3 nitride semiconductor layer (C) (in the case of the first bonding layer (B1)) or the support substrate (S) (in the case of the second bonding layer (B2)). there is.

The fifth step (S105) is a step of forming a bonding layer (B) by bonding the first bonding layer (B1) and the second bonding layer (B2) to each other. That is, in the fifth step (S105), the growth substrate (G) on which the first bonding layer (B1) is formed is turned over and placed on the support substrate (S) on which the second bonding layer (B2) is formed at a temperature of less than 300°C. This is the step of joining by pressing.

Typically, in order to minimize wafer bow after bonding, it is optimal to select the material of the support substrate (S) so that the difference in coefficient of thermal expansion (CTE) with the growth substrate (G) is less than 2 ppm, but as described above, The support substrate (S) with heat dissipation ability such as Si, _SiC , SiN This exists. In this case, setting the bonding process temperature near room temperature and performing the process can minimize stress and prevent wafer bending.

The sixth step (S106) is a step of separating the optically transparent growth substrate (G) from the group III nitride semiconductor layer (C) using a laser lift off (LLO) technique. Here, the laser lift-off technique refers to irradiating an ultraviolet (UV) laser beam with uniform light output, beam profile, and single wavelength to the back of a transparent growth substrate (G) to form an epitaxy-grown layer on the growth substrate (G). ) is a technique to separate from. Afterwards, the damaged area, contaminated surface residue, and low-quality single crystal thin film area resulting from separation of the growth substrate (G) can be removed as completely as possible.

In the seventh step (S107), before growing the group 3 nitride semiconductor device active layer (U) on the group 3 nitride semiconductor layer (C), the surface polarity of the group 3 nitride semiconductor layer (C) is changed to nitrogen polarity (N). -polarity) to group 3 metal polarity (M(Ga, Al, In)-polarity) to form a transition layer (W) (Polarity Transform Layer), and the group 3 group from which the growth substrate (G) is separated. Annealing the nitride semiconductor layer (C) at a high temperature of 700°C or higher to strengthen the weak bonding layer (B) formed between the first bonding layer (B1) and the second bonding layer (B2). am. In some cases, the order of the process of forming the conversion layer (W) to change the surface polarity and the high-temperature heat treatment process to strengthen the bonding layer (B) may be changed.

As described above, the widely commercialized transparent growth substrate (G) is sapphire. Typically, when grown on the sapphire growth substrate (G) in a MOCVD chamber, metals (M; Ga, Al, In) having three valence electrons are used. ) While the surface has a polarity, the interface directly in contact with the sapphire growth substrate has the polarity of nitrogen with 5 valence electrons. Thus, the polarity of the surface of the group III nitride semiconductor layer (C) finally formed on the support substrate (S) is nitrogen polarity (N-polarity), unlike the metal polarity (M-polarity) surface grown on the sapphire growth substrate (G). polarity) surface. However, there are serious technical difficulties in ensuring high quality when growing a stacked structure of a group III nitride semiconductor device active layer (U) on such a nitrogen polar surface, and furthermore, even if growth is possible, the growth rate is very low. That is, in order to implement a high-quality Group 3 nitride semiconductor device active layer (U), the surface of the Group 3 nitride semiconductor layer (C) formed on the support substrate (S) must be of Group 3 metal polarity (M( A process to convert the surface polarity of the Group 3 nitride semiconductor layer (C) to have Al, Ga, In)-polarity must be introduced.

To this end, in the seventh step (S107), after separating the growth substrate (G) and before loading it into the MOCVD chamber, a Group III nitride semiconductor layer on the nitrogen polar surface is formed through a PVD (sputter, PLD, MBE, Evaporator) process. (C) Deposit or grow a transition layer (W) (Polarity Transform Layer) that promotes the polarity of a group 3 metal (M) such as aluminum (Al), aluminum nitride (AlN), or aluminum nitride oxide (AlNO). do. Thereafter, in the eighth step (S108) described later, the device active layer (U) is grown on the upper surface of the conversion layer (W).

Figure 10 shows the first case of the seventh step of the semiconductor template manufacturing method according to the first or third embodiment of the present invention, and Figure 11 shows the first or third embodiment of the present invention. It shows the second case of the seventh step of the semiconductor template manufacturing method according to the , and Figure 12 shows the third case of the seventh step of the semiconductor template manufacturing method according to the first or third embodiment of the present invention. It shows.

Meanwhile, as shown in FIG. 10, the first case of the seventh step (S107) will now be described. In the first case, after the growth substrate (G) is separated in the sixth step (S106), the upper surface of the group 3 nitride semiconductor layer (C) is selectively (meaning that the process can be omitted if necessary) dry process. After dry etching, the upper surface of the nitride semiconductor layer (C) is selectively planarized through a CMP process. Afterwards, through the PVD (sputter, PLD, MBE, Evaporator) process, aluminum (Al), aluminum nitride (AlN), aluminum nitride oxide (AlNO), and gallium (Ga) are placed on the Group III nitride semiconductor layer (C) on the nitrogen polar surface. ), a transition layer that promotes Group 3 metals such as gallium nitride (GaN), gallium nitride oxide (GaNO), indium (In), indium nitride (InN), and indium nitride oxide (InNO) to have polarity (M-polarity). (W) (Polarity Transform Layer) is deposited or grown. At this time, various patterns may be etched on the deposited or grown transition layer (W), and the etched pattern may be regular or irregular, shape, Size, spacing and height are not limited. Thereafter, in the eighth step (S108) described later, a device active layer (U) is grown on the upper surface of the transition layer (W), and when a pattern is etched on the transition layer (W), the transition layer (W) and the device adjacent to it are grown. A plurality of voids may be formed at the interface of the active layer (U). These voids have the effect of relieving the stress of the regrown Group III nitride semiconductor layer (C).

Meanwhile, as shown in FIG. 11, the second case of the seventh step (S107) will now be described. In the second case, after the growth substrate (G) is separated in the sixth step (S106), the upper surface of the group 3 nitride semiconductor layer (C) is selectively (meaning that the process can be omitted if necessary) dry process. After dry etching, the upper surface of the nitride semiconductor layer (C) is selectively planarized through a CMP process. Thereafter, various patterns may be etched on the upper surface of the group III nitride semiconductor layer (C). The etched pattern may be regular or irregular, and the shape, size, spacing, and height are not limited. Afterwards, aluminum (Al), aluminum nitride (AlN), and aluminum nitride oxide (AlNO) were deposited on the Group 3 nitride semiconductor layer (C) in which the pattern of the nitrogen polar surface was etched through the PVD (sputter, PLD, MBE, Evaporator) process. , Group 3 metals such as gallium (Ga), gallium nitride (GaN), gallium nitride oxide (GaNO), indium (In), indium nitride (InN), and indium nitride oxide (InNO) to have polarity (M-polarity). The promoting transition layer (W) (Polarity Transform Layer) is deposited or grown according to the pattern of the group III nitride semiconductor layer (C). Thereafter, in the eighth step (S108), which will be described later, a device active layer (U) is grown on the upper surface of the conversion layer (W). If necessary, the device active layer (U) is grown to fill the etched pattern to create an internal void. It can be prevented from forming, and the device active layer (U) can be grown so as not to fill the etched pattern so that a void is formed inside. These voids have the effect of relieving the stress of the regrown Group III nitride semiconductor layer (C).

Meanwhile, as shown in FIG. 12, the third case of the seventh step (S107) will now be described. In the third case, after the growth substrate (G) is separated in the sixth step (S106), the upper surface of the group 3 nitride semiconductor layer (C) is selectively (meaning that the process can be omitted if necessary) dry process. Dry etching. Thereafter, various patterns may be etched on the upper surface of the group III nitride semiconductor layer (C). The etched pattern may be regular or irregular, and the shape, size, spacing, and height are not limited. Afterwards, the upper surface of the group 3 nitride semiconductor layer (C) on which the pattern was etched was selectively dry etched, and then the upper surface of the group 3 nitride semiconductor layer (C) on which the pattern was etched was processed using a PR mask or CMP process. Each end of the pattern is flattened through (Peak flattening). For example, a pattern is formed by surface texturing the group 3 nitride semiconductor layer (C) on the nitrogen polar surface with a base solution containing an OH component, and then plasma is applied in a continuous follow-up process. ) On the hexagonal pyramid-shaped surface created by surface texturing through a dry process, sharp parts can be flattened to have a flat plateau shape. Afterwards, the pattern on the nitrogen polar surface is etched through the PVD (sputter, PLD, MBE, Evaporator) process, and then aluminum (Al), aluminum nitride (AlN), and aluminum nitride oxide are placed on the planarized Group III nitride semiconductor layer (C). Group 3 metal polarity (M-polarity) such as (AlNO), gallium (Ga), gallium nitride (GaN), gallium nitride oxide (GaNO), indium (In), indium nitride (InN), and indium nitride oxide (InNO). ) is deposited or grown according to the pattern of the group 3 nitride semiconductor layer (C). Thereafter, in the eighth step (S108), which will be described later, a device active layer (U) is grown on the upper surface of the conversion layer (W). If necessary, the device active layer (U) is grown to fill the etched pattern to create an internal void. It can be prevented from forming, and the device active layer (U) can be grown so as not to fill the etched pattern so that a void is formed inside. These voids have the effect of relieving the stress of the regrown Group III nitride semiconductor layer (C).

The eighth step (S108) is a step of growing a group 3 nitride semiconductor device active layer (U) on the group 3 nitride semiconductor layer (C). That is, through the previous steps, a semiconductor device active layer (U) structure containing a desired compound can be finally grown on the upper surface of the group III nitride semiconductor layer (C) formed on the high heat dissipation support substrate (S). For example, in the case of a GaN material-based power semiconductor structure, the device active layer (U) is typically 1) GaN buffer layer (horizontal and vertical transistor), 2) GaN channel layer (horizontal transistor) or drift layer. Drift Layer (vertical transistor), 3) AlGaN Barrier Layer (horizontal transistor) or p-type Nitride Semiconductor Layer (vertical transistor), 4) Capping Passivation Layer Layer; horizontal transistor), p-type nitride semiconductor layer (horizontal transistor), or capping passivation layer (vertical transistor) can be formed by stacking four areas.

The first step (S101), the second step (S102), the third step (S103), the fourth step (S104), the fifth step (S105), and the sixth step (S106) as described above. and a Group 3 nitride semiconductor template manufacturing method (S100) according to the first embodiment of the present invention including a 7th step (S107) and an 8th step (S108) and a Group 3 nitride semiconductor template manufactured thereby. According to, a high heat dissipation support substrate (S) having the same or similar coefficient of thermal expansion (CTE) as the group 3 nitride semiconductor layer (C), a high quality group 3 nitride thin film material, and a power semiconductor device structure using the same for growth Since the Group 3 nitride single crystal growth layer can be bonded through a highly heat-resistant bonding layer, it is possible to form a high quality Group 3 nitride semiconductor layer at a high temperature of 700°C or higher. In other words, the Group 3 nitride thin film material, the power semiconductor device structure using the same, and the support substrate may have the same or similar lattice constant (LC) and coefficient of thermal expansion (CTE), so the structural and thermo-mechanical factors that occur during growth are affected. Stress (Thermo-mechanical Induced Stress) can be minimized.

In addition, according to the present invention, the pattern (P) can be etched at a preset depth in the group 3 nitride semiconductor layer (C) or bonding layer (B), which is advantageous for the wafer bonding process. In other words, in the case of direct contact wafer bonding, it is quite sensitive to the surface roughness of the wafer bonding surface and the wafer bow, but according to the patterning of the present invention, strict wafer surface roughness It has the advantage of significantly alleviating the and bending issues. In addition, according to the patterning of the present invention, it is possible to facilitate the discharge of gas generated inside the bonding layer (B) during the wafer bonding process, thereby strengthening the bonding strength of the bonding layer (B) in a void-free manner. It can also buffer structural and thermal-mechanical induced stress more effectively.

In addition, according to the present invention, the high heat dissipation support substrate (S) is formed of polycrystalline ceramic, so it has an advantage in terms of cost competitiveness compared to single crystalline ceramic.

In addition, according to the present invention, the polarity of the surface of the group III nitride semiconductor layer (C) initially grown on the growth substrate (G) and the surface of the semiconductor layer (C) finally formed on the support substrate (S) are different ( (i.e., opposite) However, prior to growing the Group 3 nitride semiconductor device active layer (U), a high-quality Group 3 nitride semiconductor device active layer is created by introducing a material layer that promotes Group 3 metal polarity (M-polarity). (U) can grow.

From now on, with reference to the attached drawings, the group III nitride semiconductor template manufacturing method (S200) according to the second embodiment of the present invention will be described in detail.

Figure 1 shows a semiconductor template manufactured by the Group 3 semiconductor template manufacturing method according to the first to fourth embodiments of the present invention, and Figure 2 shows the first to fourth embodiments of the present invention. It shows that a device active layer is grown on a semiconductor template manufactured by a group 3 semiconductor template manufacturing method according to , and Figure 5 is a flowchart of the group 3 semiconductor template manufacturing method according to the second embodiment of the present invention. Figure 6 shows the process of manufacturing a semiconductor template according to the Group 3 semiconductor template manufacturing method according to the second embodiment of the present invention.

As shown in FIGS. 1, 2, 5, and 6, the group 3 nitride semiconductor template manufacturing method (S200) according to the second embodiment of the present invention is initially grown on the growth substrate (G). It relates to a method for manufacturing a group 3 nitride semiconductor template in which the surface of the group 3 nitride semiconductor layer (C) and the surface of the group 3 nitride semiconductor layer (C) finally formed on the support substrate (S) are the same, Step (S201), second step (S202), third step (S203), fourth step (S204), fifth step (S205), sixth step (S206), and seventh step ( S207), the 8th step (S208), the 9th step (S209), the 10th step (S210), the 11th step (S211), the 12th step (S212), and the 13th step (S213) Includes.

The first step (S201) is a step of preparing a growth substrate (G), a temporary substrate (T), and a support substrate (S).

The growth substrate (G) is an optically transparent substrate through which a laser (single wavelength light) beam is 100% transmitted (in theory) without absorption after the Group 3 nitride semiconductor layer (C) is grown. In the present disclosure, aluminum oxide (Al ₂ It is limited to single crystalline sapphire material (Al ₂ O ₃ , ScAlMgO ₄ ) substrates containing O ₃ ).

After going through each step of the group 3 nitride semiconductor template manufacturing method (S200) according to the second embodiment of the present invention, the support substrate (S) is formed of a group 3 nitride semiconductor layer (C) and a group 3 nitride semiconductor device active layer ( It is a substrate that supports (U), and this support substrate (S) is composed of multiple layers, has high heat dissipation ability (over 60W/mK), and has a group 3 nitride semiconductor layer (C) and coefficient of thermal expansion (CTE, ppm). It can be formed of a material equal to or less than (5.6 ppm), and can be formed with a polycrystalline or single crystalline microstructure.

More specifically, the support substrate S is made of at least one material selected from materials including silicon (Si), silicon carbide (SiC), silicon nitride (SiN _x ), aluminum nitride (AlN), and gallium nitride (GaN). It can be included. Here, the heat dissipation capacity of silicon (Si) is 149 W/mK, the heat dissipation ability of silicon carbide ( _SiC ) is 300~450 W/mK, the heat dissipation ability of silicon nitride (SiN is 170~230W/mK, the heat dissipation capacity of gallium nitride (GaN) is 170~210W/mK, the thermal expansion coefficient of silicon (Si) is 2.6ppm, the thermal expansion coefficient of silicon carbide (SiC) is 4.8ppm, and silicon nitride ( The thermal expansion coefficient _of SiN In addition, silicon (Si), silicon carbide ( _SiC ), silicon nitride (SiN It is desirable to form a coarse polycrystalline microstructure, which has the advantage of securing cost competitiveness.

The temporary substrate (T) has a thermal expansion coefficient equal to or similar to that of the growth substrate (G) and is formed of an optically transparent material. It is desirable that the difference in thermal expansion coefficient does not exceed a maximum of 2 ppm. The most desirable temporary substrate (T) material that satisfies this is sapphire, which is used as a Group 3 nitride semiconductor growth substrate (G), or a coefficient of thermal expansion (CTE) that has a difference of 2ppm or less from that of the growth substrate (G). Adjusted glass may be included.

The second step (S202) is a step of growing the group III nitride semiconductor layer (C) in a single layer or multilayer on the growth substrate (G).

Here, it is desirable that the Group 3 nitride semiconductor layer (C) basically has electrical insulation properties that do not contain dopants, but in some cases, it may have electrical conductivity that contains dopants as a means to minimize crystal defects. As such, it serves as a seed for growing Group 3 nitride thin film materials and power semiconductor device structures using them.

Here, the surface of the group 3 nitride semiconductor layer (C) formed on the growth substrate (G) and the surface of the group 3 nitride semiconductor layer (C) later transferred to the top of the temporary substrate (T) are reversed ( Inversion), it is desirable to form a microstructure by treating the surface of the growth substrate (G) so that a desired surface of the semiconductor layer (C) can be formed. For example, in the case of a gallium nitride (GaN) semiconductor layer (C), the gallium polarity (Ga-polarity) or nitrogen polarity (N-polarity) surface can be selectively adjusted depending on the surface treatment and growth conditions of the growth substrate (G). You can. Typically, when a group III nitride semiconductor layer (C) is grown in a MOCVD chamber on a sapphire growth substrate wafer, a surface with a polarity of a metal (M; Ga, Al, In) with three valence electrons is formed. On the other hand, the interface directly contacting the sapphire growth substrate has nitrogen polarity with 5 valence electrons.

The third step (S203) is a step of forming the first adhesive layer (A1) on the group 3 nitride semiconductor layer (C).

Here, before forming the first adhesive layer (A1) on the group 3 nitride semiconductor layer (C), a protective layer is formed to prevent the semiconductor layer (C) from being damaged during the subsequent process. Alternatively, coating is preferable. Materials for this purpose may include, for example, oxides preferentially containing SiO ₂ , nitrides containing SiN _x , etc.

The fourth step (S204) is a step of forming the second adhesive layer (A2) on the temporary substrate (T).

Here, the optically transparent temporary substrate (T) is a substrate that is easily separated by the LLO technique in the subsequent process. Prior to forming the second adhesive layer (A2), the LLO sacrificial layer (Sacrificial LLO) is placed on the temporary substrate (T). The key is to tabernacle the layer. If necessary, a bonding reinforcement layer may be separately provided before the LLO sacrificial layer is deposited so that the LLO sacrificial layer material can be strongly bonded to the upper part of the temporary substrate T. At this time, the bonding reinforcement layer may include an optically transparent material upon laser beam irradiation, such as an oxide preferentially containing SiO ₂ or a nitride containing SiN _x . In addition, the above-described LLO sacrificial layer material may include oxide, nitride, etc., which can be deposited by PVD techniques such as sputter, pulsed laser deposition (PLD), and evaporator.

Here, the first adhesive layer (A1) and the second adhesive layer (A2) are BCB (Benzocyclobuene), SU-8 polymer, or an oxide with fluidity such as SOG (Spin On Glass) and HSQ (Hydrogen Silsesquioxane) to improve surface roughness. Flowable Oxide; FO _x ) may be included.

The fifth step (S205) is a step of forming the adhesive layer (A) by adhering the first adhesive layer (A1) and the second adhesive layer (A2) to each other. That is, the fifth step (S205) is a step of turning over the temporary substrate (T) on which the second adhesive layer (A2) is formed and bonding it to the growth substrate (G) on which the first adhesive layer (A1) is formed by pressing at a temperature of less than 300°C. .

The sixth step (S206) is a step of separating the growth substrate (G) from the group III nitride semiconductor layer (C) using a laser lift off (LLO) technique. Here, the laser lift-off technique refers to irradiating an ultraviolet (UV) laser beam with uniform light output, beam profile, and single wavelength to the back of a transparent growth substrate (G) to form an epitaxy-grown layer on the growth substrate (G). ) is a technique to separate from. Afterwards, the damaged area, contaminated surface residue, and low-quality single crystal thin film area resulting from separation of the growth substrate (G) can be removed as completely as possible.

In the seventh step (S207), prior to forming the first bonding layer (B1) on the group 3 nitride semiconductor layer (C), the laser damage area due to the above-described laser lift-off (LLO) process and the inherently existing This is the step of converting the rough surface caused by the inevitable ID (Inversion Domain, ID) and IDB (Inversion Domain Boundary, IDB) into a mirror-like surface.

The nitrogen polarity (N-polarity) surface from which the growth substrate (G) is separated using the laser lift-off (LLO) technique may be subject to laser damage due to instability of the laser beam and contamination of the rear surface of the growth substrate (G). In addition, when growing the first Group 3 nitride semiconductor layer (C) on the growth substrate (G), the Group 3 metal polarity (M-polarity) is inherent in the area adjacent to the growth substrate (G), although there is a slight difference. The surface area has a sporadic distribution. The dominant polarity in the area adjacent to the growth substrate (G) described above is basically nitrogen (N), but the sporadically distributed group 3 metal (M) polarity area is called the inversion domain (ID). and at the same time, inverts the interface between the nitrogen (N) polarity plane and the Group 3 metal polarity region (ID) plane in the thickness (growth) direction of the Group 3 nitride semiconductor layer (C). It is called domain boundary (Inversion Domain Boundary, IDB). In particular, nitrogen (N) polar surfaces are chemically more unstable than Group 3 metal (M) polar surfaces. This means that the nitrogen (N) polar surface is etched at a much faster rate than in the wet (using a liquid solution) or dry (using plasma) etching process. Etching, which has been researched and developed so far to treat the rough surface due to the laser damage area generated during the above-described laser lift-off (LLO) process and the inherently existing ID and IDB, etc. Even when processes such as CMP (Chemical Mechanical Polishing) are used, the surface roughness of the Group 3 nitride semiconductor layer (C) with a nitrogen (N) polar surface is dramatically improved, allowing direct (Without Interlayer) or indirect (With Interlayer) ), there are technical difficulties in performing wafer bonding, so a process to solve this must be introduced.

Figure 13 shows the first case of the seventh step of the semiconductor template manufacturing method according to the second or fourth embodiment of the present invention, and Figure 14 shows the second or fourth embodiment of the present invention. 15 shows the second case of the seventh step of the semiconductor template manufacturing method according to the present invention, and Figure 15 shows the third case of the seventh step of the semiconductor template manufacturing method according to the second or fourth embodiment of the present invention. 16 shows that in the third case of the seventh step of the semiconductor template manufacturing method according to the second or fourth embodiment of the present invention, the degree of flattening is adjusted in three cases. .

As shown in FIG. 13, the first case of the seventh step (S207) will now be described. In the first case, after the growth substrate (G) is separated in the sixth step (S206), a Group 3 nitride semiconductor with a nitrogen polar surface is formed through processes such as PVD (sputter, PLD, MBE, Evaporator), CVD, and liquid coating. A single or multi-layer thick film of highly heat-resistant ceramic materials such as silicon (Si), silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), aluminum nitride (AIN), and aluminum oxide (Al ₂ O ₃ ) is formed on the layer (C). It is deposited to form a planarization layer (N). Afterwards, the thick-film deposited planarization layer (N) is planarized and mirror-surfaced through a CMP process. At this time, when considering the heat dissipation aspect, aluminum nitride (AlN), which has excellent heat dissipation characteristics, is preferable, and when considering the ease and economic efficiency of the CMP process, silicon (Si) and silicon oxide (SiO ₂ ) are preferable. In addition, the liquid coating process is known to be more economical than PVD and CVD, and silicon oxide (SiO ₂ ) is preferable when using the process (Spin On Glass, SOG). Thereafter, the first bonding layer (B1) is formed on the planarized layer (N) in the eighth step (S208), which will be described later. Meanwhile, in the present invention, if bonding is possible only with the planarization layer (N), direct bonding may be performed without the first bonding layer (B1) or the second bonding layer (B2).

Meanwhile, as shown in FIG. 14, the second case of the seventh step (S207) will now be described. In the second case, after the growth substrate (G) is separated in the sixth step (S206), the upper surface of the group 3 nitride semiconductor layer (C) is directly planarized and mirror-surfaced through a CMP process. In this case, the process has the advantage of being simple, but it is necessary to separately optimize the CMP process (slurry and conditions) for the group III nitride semiconductor layer (C) having a nitrogen polarity (N-polarity) surface. Thereafter, a first bonding layer (B1) is formed on the group III nitride semiconductor layer (C) planarized in the eighth step (S208), which will be described later.

Meanwhile, as shown in FIG. 15, the third case of the seventh step (S207) will now be described. In the third case, after the growth substrate (G) is separated in the sixth step (S206), the upper surface of the group 3 nitride semiconductor layer (C) is selectively (meaning that the process can be omitted if necessary) dry-processed. Dry etching removes areas with high defects in the early stages of growth.

Thereafter, the upper surface of the Group 3 nitride semiconductor layer (C) is etched to form a regular or irregular pattern to expand the surface area. At this time, regular patterns can be formed through general pattern/etching processes such as photo lithography, and the formed pattern is not limited to size, spacing, or height, but the wider the surface area, the better in terms of heat dissipation and bonding properties. do. In addition, the irregular pattern can be formed by, for example, wet etching characteristics of the Group 3 nitride semiconductor layer (C) having a nitrogen polarity (N-polarity) surface with a base solution containing an OH component. After forming a pattern by surface texturing the group 3 nitride semiconductor layer (C), a hexagonal pyramid shape created by surface texturing through a plasma dry process as a selective subsequent process is formed with sharp points on the surface. The part can be flattened to have a flat plateau shape. Meanwhile, the cross section of the formed pattern may be square, trapezoid, curved, etc., but is not limited to the shape.

Afterwards, the upper surface of the group III nitride semiconductor layer (C) with an expanded surface area can be selectively dry-etched again, which can be done to make the depth of the irregularities deeper or to ensure uniformity of the pattern height after texturing. there is.

Thereafter, a single-layer or multi-layer first planarization layer (N1) is deposited or grown on the pattern-etched group 3 nitride semiconductor layer (C) according to the pattern of the group 3 nitride semiconductor layer (C), and then 1 A single-layer or multi-layer second planarization layer (N2) is deposited or grown on the planarization layer (N1). For example, the first planarization layer (N1) may be aluminum nitride (AlN) for high heat dissipation, and the second planarization layer (N2) may be silicon oxide (SiO ₂ ) to facilitate planarization. (N1) may be silicon oxide (SiO ₂ ) to strengthen adhesion, and the second planarization layer (N2) may be aluminum nitride (AlN) for high heat dissipation, but is not limited thereto and various combinations are possible as needed.

Afterwards, the surface on which the first planarization layer (N1) and the second planarization layer (N2) are formed or grown is planarized through a CMP process, and the physical properties of the first planarization layer (N1) or the second planarization layer (N2) are determined. The degree of flattening can be adjusted accordingly. That is, as shown in FIG. 16, when the first planarization layer (N1) is aluminum nitride (AlN) and the second planarization layer (N2) is silicon oxide (SiO ₂ ), the second planarization layer (N2) is used in terms of heat dissipation. ) is preferably etched (case 3 in FIG. 16), and in the case where the first planarization layer (N1) is silicon oxide (SiO ₂ ) and the second planarization layer (N2) is aluminum nitride (AlN), in terms of heat dissipation It is preferable that the second planarization layer (N2) is hardly etched (case 1 in FIG. 16).

The eighth step (S208) is a step of forming the first bonding layer (B1) on the group 3 nitride semiconductor layer (C). Here, the first bonding layer (B1) is a metal or alloy such as aluminum (Al), tungsten (W), molybdenum (Mo), silicon oxide (SiO _x ), silicon nitride (SiN _x ), or aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon (Si), zinc oxide (ZnO), C ₆₀ (Fullerene), or furthermore, to improve surface roughness _, a flowable oxide (FO In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

The ninth step (S209) is a step of forming the second bonding layer (B2) on the support substrate (S). Here, the second bonding layer (B2), like the first bonding layer (B1), is made of a metal or alloy such as aluminum (Al), tungsten (W), molybdenum (Mo), silicon oxide (SiO _x ), or silicon nitride (SiN). _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon ( _Flowable oxides ( _FO Additional information may be included. In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

Meanwhile, each of the first bonding layer (B1) and the second bonding layer (B2) may include a bonding reinforcement layer (R), a surface planarization layer (F), and a bonding layer (J).

Figure 9 shows in detail the first bonding layer (B1) and the second bonding layer (B2) of the semiconductor template manufacturing method according to the first and second embodiments of the present invention.

As shown in Figure 9, the bonding reinforcement layer (R) is a group 3 nitride semiconductor layer (C) (in the case of the first bonding layer (B1)) or a support substrate (S) (in the case of the second bonding layer (B2)). In order to strengthen the bond with each other, this bond reinforcement layer (R) is, for example, silicon oxide (SiO _x ), silicon nitride (SiN _x ), chromium (Cr), titanium (Ti), molybdenum Mo), may include HMDS.

The surface planarization layer (F) is used to alleviate the roughness of the surface of the group 3 nitride semiconductor layer (C) or the support substrate (S), respectively. This surface planarization layer (F) is used, for example, to improve surface roughness. It may include silicon oxide (SiO _x ), silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and amorphous or polycrystalline silicon (Si). Furthermore, it may further include a flowable oxide (FO _x ) such as SOG (Spin On Glass) and HSQ (Hydrogen Silsesquioxane).

The bonding layer (J) is for bonding the first bonding layer (B1) and the second bonding layer (B2) to each other, and may be prepared with a permanent bonding material, such as aluminum (Al) or tungsten (W). ), metals or alloys such as molybdenum (Mo), silicon oxide (SiO _x ), silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon (Si), zinc oxide (ZnO), C ₆₀ (Fullerene), or even SOG (Spin) to improve surface roughness. On Glass), HSQ (Hydrogen Silsesquioxane), etc. may additionally include a flowable oxide (FO _x ). In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

On the other hand, the above-described bonding reinforcement layer (R) and surface planarization layer (F) can be selectively introduced or deleted depending on the process, and when the bonding strengthening layer (R) and surface planarization layer (F) are deleted depending on the process, , the bonding layer (J) can be formed directly with the group 3 nitride semiconductor layer (C) (in the case of the first bonding layer (B1)) or the support substrate (S) (in the case of the second bonding layer (B2)). there is.

The tenth step (S210) is a step of forming a bonding layer (B) by bonding the first bonding layer (B1) and the second bonding layer (B2) to each other. That is, the tenth step is to flip the group III nitride semiconductor layer (C) on which the first bonding layer (B1) is formed (deposited) and the temporary substrate (T) over the support substrate (S) on which the second bonding layer (B2) is formed. This is the step of bonding by pressurizing at a temperature below 300℃.

Typically, in order to minimize wafer bow after bonding, it is optimal to select the material of the support substrate (S) so that the difference in coefficient of thermal expansion (CTE) with the growth substrate (G) is less than 2 ppm, but as described above, The support substrate (S) with heat dissipation ability such as Si, _SiC , SiN This exists. In this case, setting the bonding process temperature near room temperature and performing the process can minimize stress and prevent wafer bending.

The 11th step (S211) is a step of separating the temporary substrate (T) from the adhesive layer (A) using a laser lift off (LLO) technique.

The twelfth step (S212) is a step of separating the adhesive layer (A) from the nitride semiconductor layer (C) having a Group 3 metal polarity (M-polarity) surface. Thereafter, contaminated Group 3 metal (M) polar surface residues can be removed.

In particular, in the twelfth step (S212), prior to the thirteenth step (S213) of growing the device active layer (U) structure, the group III nitride semiconductor layer (C) from which the temporary substrate (T) is separated is grown at a high temperature of 700°C or higher. The weak bonding layer (B) formed between the first bonding layer (B1) and the second bonding layer (B2) can be strengthened by heat treatment (annealing).

The thirteenth step (S213) is a step of growing the device active layer (U) on the nitride semiconductor layer (C) having a Group 3 metal (M) polar surface. That is, through the previous steps, a semiconductor device active layer (U) structure containing a desired compound can be finally grown on the upper surface of the group III nitride semiconductor layer (C) formed on the high heat dissipation support substrate (S). For example, in the case of a GaN material-based power semiconductor structure, the device active layer (U) is typically 1) GaN buffer layer (horizontal and vertical transistor), 2) GaN channel layer (horizontal transistor) or drift layer. Drift Layer (vertical transistor), 3) AlGaN Barrier Layer (horizontal transistor) or p-type Nitride Semiconductor Layer (vertical transistor), 4) Capping Passivation Layer Layer; horizontal transistor), p-type nitride semiconductor layer (horizontal transistor), or capping passivation layer (vertical transistor) can be formed by stacking four areas.

The first step (S201), the second step (S202), the third step (S203), the fourth step (S204), the fifth step (S205), and the sixth step (S206) as described above. , the 7th step (S207), the 8th step (S208), the 9th step (S209), the 10th step (S210), the 11th step (S211), and the 12th step (S212), According to the group 3 nitride semiconductor template manufacturing method (S200) according to the second embodiment of the present invention including the 13th step (S213) and the group 3 nitride semiconductor template manufactured thereby, the group 3 nitride semiconductor layer ( A high heat dissipation support substrate (S) having the same or similar coefficient of thermal expansion (CTE) as C), a high-quality Group 3 nitride thin film material, and a Group 3 nitride single crystal growth layer for the growth of a power semiconductor device structure using the same are highly heat-resistant. Since they can be bonded through a bonding layer, it is possible to form a high-quality Group 3 nitride semiconductor layer at a high temperature of 700°C or higher. In other words, the Group 3 nitride thin film material, the power semiconductor device structure using the same, and the support substrate may have the same or similar lattice constant (LC) and coefficient of thermal expansion (CTE), so the structural and thermo-mechanical factors that occur during growth are affected. Stress (Thermo-mechanical Induced Stress) can be minimized.

In addition, according to the present invention, the pattern (P) can be etched at a preset depth in the group 3 nitride semiconductor layer (C) or bonding layer (B), which is advantageous for the wafer bonding process. In other words, in the case of direct contact wafer bonding, it is quite sensitive to the surface roughness of the wafer bonding surface and the wafer bow, but according to the patterning of the present invention, strict wafer surface roughness It has the advantage of significantly alleviating the and bending issues. In addition, according to the patterning of the present invention, it is possible to facilitate the discharge of gas generated inside the bonding layer (B) during the wafer bonding process, thereby strengthening the bonding strength of the bonding layer (B) in a void-free manner. It can also buffer structural and thermal-mechanical induced stress more effectively.

In addition, according to the present invention, the high heat dissipation support substrate (S) is formed of polycrystalline ceramic, so it has an advantage in terms of cost competitiveness compared to single crystalline ceramic.

In addition, according to the present invention, the polarity of the surface of the semiconductor layer (C) initially grown on the growth substrate (G) and the surface of the semiconductor layer (C) finally formed on the support substrate (S) can be the same. In order to successfully implement this, a process must be introduced, such as the present invention, to turn the rough surface into a mirror-like surface due to the laser damage area generated during the above-described process and the inherently existing ID and IDB. .

From now on, with reference to the attached drawings, the group III nitride semiconductor template manufacturing method (S300) according to the third embodiment of the present invention will be described in detail.

Figure 1 shows a semiconductor template manufactured by the group 3 semiconductor template manufacturing method according to the first to fourth embodiments of the present invention, and Figure 2 shows the first to fourth embodiments of the present invention. It shows that a device active layer is grown on a semiconductor template manufactured by the Group 3 semiconductor template manufacturing method according to , and Figure 7 is a flowchart of the Group 3 semiconductor template manufacturing method according to the third embodiment of the present invention.

As shown in FIGS. 1, 2, and 7, the group 3 nitride semiconductor template manufacturing method (S300) according to the third embodiment of the present invention is a group 3 nitride semiconductor initially grown on a growth substrate (G). It relates to a method of manufacturing a semiconductor template in which the polarity of the surface of the layer (C) and the surface of the group 3 nitride semiconductor layer (C) finally formed on the top of the support substrate (S) are different (i.e., opposite), especially the support substrate. This relates to the case where (S) is a polycrystalline aluminum nitride (AlN) ceramic substrate.

The group III nitride semiconductor template manufacturing method (S300) according to the third embodiment of the present invention includes a first step (S301), a second step (S302), a third step (S303), and a fourth step (S301). It includes the fifth step (S305), the sixth step (S306), the seventh step (S307), and the eighth step (S308).

The first step (S301) is a step of preparing the growth substrate (G) and the support substrate (S).

The growth substrate (G) is an optically transparent substrate through which 100% of the laser (single wavelength light) beam is transmitted (in theory) without absorption after the group 3 nitride semiconductor layer (C) is grown, and the present invention discloses the growth substrate (G). It is limited to single crystalline sapphire material (Al ₂ O _{3 ,} ScAlMgO ₄ ) substrates containing aluminum oxide (Al ₂ O 3 ).

The support substrate (S) is a substrate that supports the semiconductor layer (C) and the device active layer (U) after going through each step of the group III nitride semiconductor template manufacturing method (S300) according to the third embodiment of the present invention. So, this support substrate (S) may be a polycrystalline aluminum nitride (AlN) ceramic substrate (Polycrystalline AlNcera Substrate). This polycrystalline AlN ceramic support substrate (S) is intended to overcome the difference in thermal expansion coefficient between silicon (Si) single crystal wafer (thermal expansion coefficient: 2.8ppm) and GaN (thermal expansion coefficient: 5.6ppm) materials, and polycrystalline AlN ceramic is The thermal expansion coefficient is 4.5ppm, which is similar to that of GaN.

The second step (S302) is a step of growing the group III nitride semiconductor layer (C) as a single layer or multilayer on the growth substrate (G).

Here, it is desirable that the Group 3 nitride semiconductor layer (C) basically has electrical insulation properties that do not contain dopants, but in some cases, it may have electrical conductivity that contains dopants as a means to minimize crystal defects. As such, it serves as a seed for growing Group 3 nitride thin film materials and power semiconductor device structures using them.

Here, the surface of the group 3 nitride semiconductor layer (C) formed on the growth substrate (G) and the surface of the group 3 nitride semiconductor layer (C) later transferred to the top of the support substrate (S) are reversed ( Inversion), it is desirable to form a microstructure by treating the surface of the growth substrate (G) so that a desired surface of the semiconductor layer (C) can be formed. For example, in the case of a gallium nitride (GaN) semiconductor layer (C), the gallium polarity (Ga-polarity) or nitrogen polarity (N-polarity) surface can be selectively adjusted depending on the surface treatment and growth conditions of the growth substrate (G). You can. Typically, when a group III nitride semiconductor layer (C) is grown in a MOCVD chamber on a sapphire growth substrate wafer, a surface with a polarity of a metal (M; Ga, Al, In) with three valence electrons is formed. On the other hand, the interface directly contacting the sapphire growth substrate has nitrogen polarity with 5 valence electrons.

The third step (S303) is a step of forming the first bonding layer (B1) on the group 3 nitride semiconductor layer (C). Here, the first bonding layer (B1) is a metal or alloy such as aluminum (Al), tungsten (W), molybdenum (Mo), silicon oxide (SiO _x ), silicon nitride (SiN _x ), or aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon (Si), zinc oxide (ZnO), C ₆₀ (Fullerene), or furthermore, to improve surface roughness _, a flowable oxide (FO In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

The fourth step (S304) is a step of forming a second bonding layer (B2) on the polycrystalline aluminum nitride (AlN) ceramic support substrate (S). Here, the second bonding layer (B2) is a metal or alloy such as aluminum (Al), tungsten (W), molybdenum (Mo), silicon oxide (SiO _x ), silicon nitride (SiN _x ), or aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon (Si), zinc oxide (ZnO), C ₆₀ (Fullerene), or furthermore, to improve surface roughness _, a flowable oxide (FO In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

Meanwhile, each of the first bonding layer (B1) and the second bonding layer (B2) may include a bonding reinforcement layer (R), a surface planarization layer (F), and a bonding layer (J).

Figure 9 shows in detail the first bonding layer (B1) and the second bonding layer (B2) of the Group 3 semiconductor template manufacturing method according to the first to fourth embodiments of the present invention.

As shown in Figure 9, the bonding reinforcement layer (R) is a group 3 nitride semiconductor layer (C) (in the case of the first bonding layer (B1)) or a support substrate (S) (in the case of the second bonding layer (B2)). In order to strengthen the bond with each other, this bond reinforcement layer (R) is, for example, silicon oxide (SiO _x ), silicon nitride (SiN _x ), chromium (Cr), titanium (Ti), molybdenum Mo), may include HMDS.

The surface planarization layer (F) is used to alleviate the roughness of the surface of the group 3 nitride semiconductor layer (C) or the support substrate (S), respectively. This surface planarization layer (F) is used, for example, to improve surface roughness. It may include silicon oxide (SiO _x ), silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and amorphous or polycrystalline silicon (Si). Furthermore, it may further include a flowable oxide (FO _x ) such as SOG (Spin On Glass) and HSQ (Hydrogen Silsesquioxane).

The bonding layer (J) is for bonding the first bonding layer (B1) and the second bonding layer (B2) to each other, and may be prepared with a permanent bonding material, such as aluminum (Al) or tungsten (W). ), metals or alloys such as molybdenum (Mo), silicon oxide (SiO _x ), silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon (Si), zinc oxide (ZnO), C ₆₀ (Fullerene), or even SOG (Spin) to improve surface roughness. On Glass), HSQ (Hydrogen Silsesquioxane), etc. may additionally include a flowable oxide (FO _x ). In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

On the other hand, the above-described bonding reinforcement layer (R) and surface planarization layer (F) can be selectively introduced or deleted depending on the process, and when the bonding strengthening layer (R) and surface planarization layer (F) are deleted depending on the process, , the bonding layer (J) can be formed directly with the group 3 nitride semiconductor layer (C) (in the case of the first bonding layer (B1)) or the support substrate (S) (in the case of the second bonding layer (B2)). there is.

The fifth step (S305) is a step of forming a bonding layer (B) by bonding the first bonding layer (B1) and the second bonding layer (B2) to each other. That is, in the fifth step (S305), the growth substrate (G) on which the first bonding layer (B1) is formed is turned over and the polycrystalline aluminum nitride (AlN) ceramic support substrate (S) on which the second bonding layer (B2) is formed is formed. ) is a step of joining by pressing at a temperature of less than 300°C.

Typically, in order to minimize wafer bow after bonding, it is optimal to select the material of the support substrate (S) so that the difference in coefficient of thermal expansion (CTE) with the growth substrate (G) is less than 2ppm, but high heat dissipation performance The difference in coefficient of thermal expansion (CTE) between the polycrystalline aluminum nitride (AlN) ceramic support substrate (S) and the sapphire growth substrate (G) is more than 2 ppm, making it realistically difficult to bond wafers at high temperatures. In this case, setting the bonding process temperature near room temperature and performing the process can minimize stress and prevent wafer bending.

The sixth step (S306) is a step of separating the optically transparent growth substrate (G) from the group III nitride semiconductor layer (C) using a laser lift off (LLO) technique. Here, the laser lift-off technique refers to irradiating an ultraviolet (UV) laser beam with uniform light output, beam profile, and single wavelength to the back of a transparent growth substrate (G) to form an epitaxy-grown layer on the growth substrate (G). ) is a technique to separate from. Afterwards, the damaged area, contaminated surface residue, and low-quality single crystal thin film area resulting from separation of the growth substrate (G) can be removed as completely as possible.

In the seventh step (S307), before growing the group 3 nitride semiconductor device active layer (U) on the group 3 nitride semiconductor layer (C), the surface polarity of the group 3 nitride semiconductor layer (C) is changed to nitrogen polarity (N). -polarity) to group 3 metal polarity (M(Ga, Al, In)-polarity) to form a transition layer (W) (Polarity Transform Layer), and the group 3 group from which the growth substrate (G) is separated. Annealing the nitride semiconductor layer (C) at a high temperature of 700°C or higher to strengthen the weak bonding layer (B) formed between the first bonding layer (B1) and the second bonding layer (B2). am. In some cases, the order of the process of forming the conversion layer (W) to change the surface polarity and the high-temperature heat treatment process to strengthen the bonding layer (B) may be changed.

As described above, the widely commercialized transparent growth substrate (G) is sapphire. Typically, when grown on the sapphire growth substrate (G) in a MOCVD chamber, metals (M; Ga, Al, In) having three valence electrons are used. ) While the surface has a polarity, the interface directly in contact with the sapphire growth substrate has the polarity of nitrogen with 5 valence electrons. Thus, the polarity of the surface of the group III nitride semiconductor layer (C) finally formed on the support substrate (S) is nitrogen polarity (N-polarity), unlike the metal polarity (M-polarity) surface grown on the sapphire growth substrate (G). polarity) surface. However, there are serious technical difficulties in ensuring high quality when growing a stacked structure of a group III nitride semiconductor device active layer (U) on such a nitrogen polar surface, and furthermore, even if growth is possible, the growth rate is very low. That is, in order to implement a high-quality Group 3 nitride semiconductor device active layer (U), the surface of the Group 3 nitride semiconductor layer (C) formed on the support substrate (S) must be of Group 3 metal polarity (M( A process to convert the surface polarity of the Group 3 nitride semiconductor layer (C) to have Al, Ga, In)-polarity must be introduced.

To this end, in the seventh step (S307), after separating the growth substrate (G) and before loading it into the MOCVD chamber, a Group III nitride semiconductor layer on the nitrogen polar surface is formed through a PVD (sputter, PLD, MBE, Evaporator) process. (C) Deposit or grow a transition layer (W) (Polarity Transform Layer) that promotes the polarity of a group 3 metal (M) such as aluminum (Al), aluminum nitride (AlN), or aluminum nitride oxide (AlNO). do. Thereafter, in the eighth step (S308) described later, the device active layer (U) is grown on the upper surface of the conversion layer (W).

Figure 10 shows the first case of the seventh step of the semiconductor template manufacturing method according to the first or third embodiment of the present invention, and Figure 11 shows the first or third embodiment of the present invention. It shows the second case of the seventh step of the semiconductor template manufacturing method according to the , and Figure 12 shows the third case of the seventh step of the semiconductor template manufacturing method according to the first or third embodiment of the present invention. It shows.

Meanwhile, as shown in FIG. 10, the first case of the seventh step (S307) will now be described. In the first case, after the growth substrate (G) is separated in the sixth step (S306), the upper surface of the group 3 nitride semiconductor layer (C) is selectively (meaning that the process can be omitted if necessary) dry process. After dry etching, the upper surface of the nitride semiconductor layer (C) is selectively planarized through a CMP process. Afterwards, through the PVD (sputter, PLD, MBE, Evaporator) process, aluminum (Al), aluminum nitride (AlN), aluminum nitride oxide (AlNO), and gallium (Ga) are placed on the Group III nitride semiconductor layer (C) on the nitrogen polar surface. ), a transition layer that promotes Group 3 metals such as gallium nitride (GaN), gallium nitride oxide (GaNO), indium (In), indium nitride (InN), and indium nitride oxide (InNO) to have polarity (M-polarity). (W) (Polarity Transform Layer) is deposited or grown. At this time, various patterns may be etched on the deposited or grown transition layer (W), and the etched pattern may be regular or irregular, shape, Size, spacing and height are not limited. Thereafter, in the eighth step (S308) described later, a device active layer (U) is grown on the upper surface of the transition layer (W), and when a pattern is etched on the transition layer (W), the transition layer (W) and the device adjacent to it are grown. A plurality of voids may be formed at the interface of the active layer (U). These voids have the effect of relieving the stress of the regrown Group III nitride semiconductor layer (C).

Meanwhile, as shown in FIG. 11, the second case of the seventh step (S307) will now be described. In the second case, after the growth substrate (G) is separated in the sixth step (S306), the upper surface of the group 3 nitride semiconductor layer (C) is selectively (meaning that the process can be omitted if necessary) dry-processed. After dry etching, the upper surface of the nitride semiconductor layer (C) is selectively planarized through a CMP process. Thereafter, various patterns may be etched on the upper surface of the group III nitride semiconductor layer (C). The etched pattern may be regular or irregular, and the shape, size, spacing, and height are not limited. Afterwards, aluminum (Al), aluminum nitride (AlN), and aluminum nitride oxide (AlNO) were deposited on the Group 3 nitride semiconductor layer (C) in which the pattern of the nitrogen polar surface was etched through the PVD (sputter, PLD, MBE, Evaporator) process. , Group 3 metals such as gallium (Ga), gallium nitride (GaN), gallium nitride oxide (GaNO), indium (In), indium nitride (InN), and indium nitride oxide (InNO) to have polarity (M-polarity). The promoting transition layer (W) (Polarity Transform Layer) is deposited or grown according to the pattern of the group III nitride semiconductor layer (C). Thereafter, in the eighth step (S308), which will be described later, a device active layer (U) is grown on the upper surface of the conversion layer (W). If necessary, the device active layer (U) is grown to fill the etched pattern to create an internal void. It can be prevented from forming, and the device active layer (U) can be grown so as not to fill the etched pattern so that a void is formed inside. These voids have the effect of relieving the stress of the regrown Group III nitride semiconductor layer (C).

Meanwhile, as shown in FIG. 12, the third case of the seventh step (S307) will now be described. In the third case, after the growth substrate (G) is separated in the sixth step (S306), the upper surface of the group 3 nitride semiconductor layer (C) is selectively (meaning that the process can be omitted if necessary) dry process. Dry etching. Thereafter, various patterns may be etched on the upper surface of the group III nitride semiconductor layer (C). The etched pattern may be regular or irregular, and the shape, size, spacing, and height are not limited. Afterwards, the upper surface of the group 3 nitride semiconductor layer (C) on which the pattern was etched was selectively dry etched, and then the upper surface of the group 3 nitride semiconductor layer (C) on which the pattern was etched was processed using a PR mask or CMP process. Each end of the pattern is flattened (Peak flattening). For example, a pattern is formed by surface texturing the group 3 nitride semiconductor layer (C) on the nitrogen polar surface with a base solution containing an OH component, and then plasma is applied in a continuous follow-up process. ) On the hexagonal pyramid-shaped surface created by surface texturing through a dry process, sharp parts can be flattened to have a flat plateau shape. Afterwards, the pattern on the nitrogen polar surface is etched through the PVD (sputter, PLD, MBE, Evaporator) process, and then aluminum (Al), aluminum nitride (AlN), and aluminum nitride oxide are placed on the planarized Group III nitride semiconductor layer (C). Group 3 metal polarity (M-polarity) such as (AlNO), gallium (Ga), gallium nitride (GaN), gallium nitride oxide (GaNO), indium (In), indium nitride (InN), and indium nitride oxide (InNO). ) is deposited or grown according to the pattern of the group 3 nitride semiconductor layer (C). Thereafter, in the eighth step (S308), which will be described later, a device active layer (U) is grown on the upper surface of the conversion layer (W). If necessary, the device active layer (U) is grown to fill the etched pattern to create an internal void. It can be prevented from forming, and the device active layer (U) can be grown so as not to fill the etched pattern so that a void is formed inside. These voids have the effect of relieving the stress of the regrown Group III nitride semiconductor layer (C).

The eighth step (S308) is a step of growing a group 3 nitride semiconductor device active layer (U) on the group 3 nitride semiconductor layer (C). That is, through the previous steps, a semiconductor device active layer (U) structure containing a desired compound can be finally grown on the upper surface of the group III nitride semiconductor layer (C) formed on the high heat dissipation support substrate (S). For example, in the case of a GaN material-based power semiconductor structure, the device active layer (U) is typically 1) GaN buffer layer (horizontal and vertical transistor), 2) GaN channel layer (horizontal transistor) or drift layer. Drift Layer (vertical transistor), 3) AlGaN Barrier Layer (horizontal transistor) or p-type Nitride Semiconductor Layer (vertical transistor), 4) Capping Passivation Layer Layer; horizontal transistor), p-type nitride semiconductor layer (horizontal transistor), or capping passivation layer (vertical transistor) can be formed by stacking four areas.

The first step (S301), the second step (S302), the third step (S303), the fourth step (S304), the fifth step (S305), and the sixth step (S306) as described above. and a Group 3 nitride semiconductor template manufacturing method (S300) according to the third embodiment of the present invention including a 7th step (S307) and an 8th step (S308) and a Group 3 nitride semiconductor template manufactured thereby. According to, a high heat dissipation support substrate (S) having the same or similar coefficient of thermal expansion (CTE) as the group 3 nitride semiconductor layer (C), a high quality group 3 nitride thin film material, and a power semiconductor device structure using the same for growth Since the Group 3 nitride single crystal growth layer can be bonded through a highly heat-resistant bonding layer, it is possible to form a high quality Group 3 nitride semiconductor layer at a high temperature of 700°C or higher. In other words, the Group 3 nitride thin film material, the power semiconductor device structure using the same, and the support substrate may have the same or similar lattice constant (LC) and coefficient of thermal expansion (CTE), so the structural and thermo-mechanical factors that occur during growth are affected. Stress (Thermo-mechanical Induced Stress) can be minimized.

In addition, according to the present invention, the pattern (P) can be etched at a preset depth in the group 3 nitride semiconductor layer (C) or bonding layer (B), which is advantageous for the wafer bonding process. In other words, in the case of direct contact wafer bonding, it is quite sensitive to the surface roughness of the wafer bonding surface and the wafer bow, but according to the patterning of the present invention, strict wafer surface roughness It has the advantage of significantly alleviating the and bending issues. In addition, according to the patterning of the present invention, it is possible to facilitate the discharge of gas generated inside the bonding layer (B) during the wafer bonding process, thereby strengthening the bonding strength of the bonding layer (B) in a void-free manner. It can also buffer structural and thermal-mechanical induced stress more effectively.

In addition, according to the present invention, the high heat dissipation support substrate (S) is formed of polycrystalline ceramic, so it has an advantage in terms of cost competitiveness compared to single crystalline ceramic.

In addition, according to the present invention, the polarity of the surface of the group III nitride semiconductor layer (C) initially grown on the growth substrate (G) and the surface of the semiconductor layer (C) finally formed on the support substrate (S) are different ( (i.e., opposite) However, prior to growing the Group 3 nitride semiconductor device active layer (U), a high-quality Group 3 nitride semiconductor device active layer is created by introducing a material layer that promotes Group 3 metal polarity (M-polarity). (U) can grow.

From now on, with reference to the attached drawings, the group III nitride semiconductor template manufacturing method (S400) according to the fourth embodiment of the present invention will be described in detail.

Figure 1 shows a semiconductor template manufactured by the group 3 semiconductor template manufacturing method according to the first to fourth embodiments of the present invention, and Figure 2 shows the first to fourth embodiments of the present invention. It shows that a device active layer is grown on a semiconductor template manufactured by the Group 3 semiconductor template manufacturing method according to , and Figure 8 is a flowchart of the Group 3 semiconductor template manufacturing method according to the fourth embodiment of the present invention.

As shown in FIGS. 1, 2, and 8, the group 3 nitride semiconductor template manufacturing method (S400) according to the fourth embodiment of the present invention initially grows the group 3 nitride semiconductor on the growth substrate (G). It relates to a method of manufacturing a group 3 nitride semiconductor template in which the surface of the layer (C) and the surface of the group 3 nitride semiconductor layer (C) ultimately formed on the support substrate (S) are the same, and in particular, the support substrate (S) ) is a polycrystalline aluminum nitride (AlN) ceramic substrate.

The group III nitride semiconductor template manufacturing method (S400) according to the fourth embodiment of the present invention includes a first step (S401), a second step (S402), a third step (S403), and a fourth step ( S404), the fifth step (S405), the sixth step (S406), the seventh step (S407), the eighth step (S408), the ninth step (S409), and the tenth step (S410) and the 11th step (S411), the 12th step (S412), and the 13th step (S413).

The first step (S401) is a step of preparing a growth substrate (G), a temporary substrate (T), and a support substrate (S).

The growth substrate (G) is an optically transparent substrate through which a laser (single wavelength light) beam is 100% transmitted (in theory) without absorption after the Group 3 nitride semiconductor layer (C) is grown. In the present disclosure, aluminum oxide (Al ₂ It is limited to single crystalline sapphire material (Al ₂ O ₃ , ScAlMgO ₄ ) substrates containing O ₃ ).

The support substrate (S) is a substrate that supports the semiconductor layer (C) and the device active layer (U) after going through each step of the group III nitride semiconductor template manufacturing method (S400) according to the fourth embodiment of the present invention. So, this support substrate (S) may be a polycrystalline aluminum nitride (AlN) ceramic substrate (Polycrystalline AlNcera Substrate). This polycrystalline AlN ceramic support substrate (S) is intended to overcome the difference in thermal expansion coefficient between silicon (Si) single crystal wafer (thermal expansion coefficient: 2.8ppm) and GaN (thermal expansion coefficient: 5.6ppm) materials, and polycrystalline AlN ceramic is The thermal expansion coefficient is 4.5ppm, which is similar to that of GaN.

The temporary substrate (T) has a thermal expansion coefficient equal to or similar to that of the growth substrate (G) and is formed of an optically transparent material. It is desirable that the difference in thermal expansion coefficient does not exceed a maximum of 2 ppm. The most desirable temporary substrate (T) material that satisfies this is sapphire, which is used as a group III nitride semiconductor growth substrate (G), or glass (CTE adjusted to have a difference of less than 2 ppm from the growth substrate (G)). Glass) may be included.

The second step (S402) is a step of growing the group III nitride semiconductor layer (C) as a single layer or multilayer on the growth substrate (G).

Here, it is desirable that the Group 3 nitride semiconductor layer (C) basically has electrical insulation properties that do not contain dopants, but in some cases, it may have electrical conductivity that contains dopants as a means to minimize crystal defects. As such, it serves as a seed for growing Group 3 nitride thin film materials and power semiconductor device structures using them.

Here, the surface of the group 3 nitride semiconductor layer (C) formed on the growth substrate (G) and the surface of the group 3 nitride semiconductor layer (C) later transferred to the top of the temporary substrate (T) are reversed ( Inversion), it is desirable to form a microstructure by treating the surface of the growth substrate (G) so that a desired surface of the semiconductor layer (C) can be formed. For example, in the case of a gallium nitride (GaN) semiconductor layer (C), the gallium polarity (Ga-polarity) or nitrogen polarity (N-polarity) surface can be selectively adjusted depending on the surface treatment and growth conditions of the growth substrate (G). You can. Typically, when a group III nitride semiconductor layer (C) is grown in a MOCVD chamber on a sapphire growth substrate wafer, a surface with a polarity of a metal (M; Ga, Al, In) with three valence electrons is formed. On the other hand, the interface directly contacting the sapphire growth substrate has nitrogen polarity with 5 valence electrons.

The third step (S403) is a step of forming the first adhesive layer (A1) on the group 3 nitride semiconductor layer (C).

Here, before forming the first adhesive layer (A1) on the group 3 nitride semiconductor layer (C), a protective layer is formed to prevent the semiconductor layer (C) from being damaged during the subsequent process. Alternatively, coating is preferable. Materials for this purpose may include, for example, oxides preferentially containing SiO ₂ , nitrides containing SiN _x , etc.

The fourth step (S404) is a step of forming the second adhesive layer (A2) on the temporary substrate (T).

Here, the optically transparent temporary substrate (T) is a substrate that is easily separated by the LLO technique in the subsequent process. Prior to forming the second adhesive layer (A2), the LLO sacrificial layer (Sacrificial LLO) is placed on the temporary substrate (T). The key is to tabernacle the layer. If necessary, a bonding reinforcement layer may be separately provided before the LLO sacrificial layer is deposited so that the LLO sacrificial layer material can be strongly bonded to the upper part of the temporary substrate T. At this time, the bonding reinforcement layer may include an optically transparent material upon laser beam irradiation, such as an oxide preferentially containing SiO ₂ or a nitride containing SiN _x . In addition, the above-described LLO sacrificial layer material may include oxide, nitride, etc., which can be deposited by PVD techniques such as sputter, pulsed laser deposition (PLD), and evaporator.

Here, the first adhesive layer (A1) and the second adhesive layer (A2) are BCB (Benzocyclobuene), SU-8 polymer, or an oxide with fluidity such as SOG (Spin On Glass) and HSQ (Hydrogen Silsesquioxane) to improve surface roughness. Flowable Oxide; FO _x ) may be included.

The fifth step (S405) is a step of forming the adhesive layer (A) by adhering the first adhesive layer (A1) and the second adhesive layer (A2) to each other. That is, the fifth step (S405) is a step of turning over the temporary substrate (T) on which the second adhesive layer (A2) is formed and bonding it to the growth substrate (G) on which the first adhesive layer (A1) is formed by pressing at a temperature of less than 300°C. .

The sixth step (S406) is a step of separating the growth substrate (G) from the group III nitride semiconductor layer (C) using a laser lift off (LLO) technique. Here, the laser lift-off technique refers to irradiating an ultraviolet (UV) laser beam with uniform light output, beam profile, and single wavelength to the back of a transparent growth substrate (G) to form an epitaxy-grown layer on the growth substrate (G). ) is a technique to separate from. Afterwards, the damaged areas resulting from separation of the growth substrate (G), contaminated surface residues, and low-quality single crystal thin film areas can be removed as completely as possible.

In the seventh step (S407), prior to forming the first bonding layer (B1) on the group 3 nitride semiconductor layer (C), the laser damage area due to the above-described laser lift-off (LLO) process and the inherently existing This is the step of converting the rough surface caused by the inevitable ID (Inversion Domain, ID) and IDB (Inversion Domain Boundary, IDB) into a mirror-like surface.

The nitrogen polarity (N-polarity) surface from which the growth substrate (G) is separated using the laser lift-off (LLO) technique may be subject to laser damage due to instability of the laser beam and contamination of the rear surface of the growth substrate (G). In addition, when growing the first Group 3 nitride semiconductor layer (C) on the growth substrate (G), the Group 3 metal polarity (M-polarity) is inherent in the area adjacent to the growth substrate (G), although there is a slight difference. The surface area has a sporadic distribution. The dominant polarity in the area adjacent to the growth substrate (G) described above is basically nitrogen (N), but the sporadically distributed group 3 metal (M) polarity area is called the inversion domain (ID). and at the same time, inverts the interface between the nitrogen (N) polarity plane and the Group 3 metal polarity region (ID) plane in the thickness (growth) direction of the Group 3 nitride semiconductor layer (C). It is called domain boundary (Inversion Domain Boundary, IDB). In particular, nitrogen (N) polar surfaces are chemically more unstable than Group 3 metal (M) polar surfaces. This means that the nitrogen (N) polar surface is etched at a much faster rate than in the wet (using a liquid solution) or dry (using plasma) etching process. Etching, which has been researched and developed so far to treat the rough surface due to the laser damage area generated during the above-described laser lift-off (LLO) process and the inherently existing ID and IDB, etc. Even when processes such as CMP (Chemical Mechanical Polishing) are used, the surface roughness of the Group 3 nitride semiconductor layer (C) with a nitrogen (N) polar surface is dramatically improved, allowing direct (Without Interlayer) or indirect (With Interlayer) ), there are technical difficulties in performing wafer bonding, so a process to solve this must be introduced.

Figure 13 shows the first case of the seventh step of the semiconductor template manufacturing method according to the second or fourth embodiment of the present invention, and Figure 14 shows the second or fourth embodiment of the present invention. 15 shows the second case of the seventh step of the semiconductor template manufacturing method according to the present invention, and Figure 15 shows the third case of the seventh step of the semiconductor template manufacturing method according to the second or fourth embodiment of the present invention. 16 shows that in the third case of the seventh step of the semiconductor template manufacturing method according to the second or fourth embodiment of the present invention, the degree of flattening is adjusted in three cases. .

As shown in FIG. 13, the first case of the seventh step (S407) will now be described. In the first case, after the growth substrate (G) is separated in the sixth step (S406), a Group 3 nitride semiconductor with a nitrogen polar surface is formed through processes such as PVD (sputter, PLD, MBE, Evaporator), CVD, and liquid coating. A single or multi-layer thick film of highly heat-resistant ceramic materials such as silicon (Si), silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), aluminum nitride (AIN), and aluminum oxide (Al ₂ O ₃ ) is formed on the layer (C). It is deposited to form a planarization layer (N). Afterwards, the thick-film deposited planarization layer (N) is planarized and mirror-surfaced through a CMP process. At this time, when considering the heat dissipation aspect, aluminum nitride (AlN), which has excellent heat dissipation characteristics, is preferable, and when considering the ease and economic efficiency of the CMP process, silicon (Si) and silicon oxide (SiO ₂ ) are preferable. In addition, the liquid coating process is known to be more economical than PVD and CVD, and silicon oxide (SiO ₂ ) is preferable when using the process (Spin On Glass, SOG). Thereafter, the first bonding layer (B1) is formed on the planarized layer (N) in the eighth step (S408), which will be described later. Meanwhile, in the present invention, if bonding is possible only with the planarization layer (N), direct bonding may be performed without the first bonding layer (B1) or the second bonding layer (B2).

Meanwhile, as shown in FIG. 14, the second case of the seventh step (S407) will now be described. In the second case, after the growth substrate (G) is separated in the sixth step (S406), the upper surface of the group 3 nitride semiconductor layer (C) is directly planarized and mirror-surfaced through a CMP process. In this case, the process has the advantage of being simple, but it is necessary to separately optimize the CMP process (slurry and conditions) for the group III nitride semiconductor layer (C) having a nitrogen polarity (N-polarity) surface. Thereafter, a first bonding layer (B1) is formed on the planarized group 3 nitride semiconductor layer (C) in the eighth step (S408), which will be described later.

Meanwhile, as shown in FIG. 15, the third case of the seventh step (S407) will now be described. In the third case, after the growth substrate (G) is separated in the sixth step (S406), the upper surface of the group 3 nitride semiconductor layer (C) is selectively (meaning that the process can be omitted if necessary) dry-processed. Dry etching removes areas with high defects in the early stages of growth.

Thereafter, the upper surface of the Group 3 nitride semiconductor layer (C) is etched to form a regular or irregular pattern to expand the surface area. At this time, regular patterns can be formed through general pattern/etching processes such as photo lithography, and the formed pattern is not limited to size, spacing, or height, but the wider the surface area, the better in terms of heat dissipation and bonding properties. do. In addition, the irregular pattern can be formed by, for example, wet etching characteristics of the Group 3 nitride semiconductor layer (C) having a nitrogen polarity (N-polarity) surface with a base solution containing an OH component. After forming a pattern by surface texturing the group 3 nitride semiconductor layer (C), a hexagonal pyramid shape created by surface texturing through a plasma dry process as a selective subsequent process is formed with sharp points on the surface. The part can be flattened to have a flat plateau shape. Meanwhile, the cross section of the formed pattern may be square, trapezoid, curved, etc., but is not limited to the shape.

Afterwards, the upper surface of the group III nitride semiconductor layer (C) with an expanded surface area can be selectively dry-etched again, which can be done to make the depth of the irregularities deeper or to ensure uniformity of the pattern height after texturing. there is.

Thereafter, a single-layer or multi-layer first planarization layer (N1) is deposited or grown on the pattern-etched group 3 nitride semiconductor layer (C) according to the pattern of the group 3 nitride semiconductor layer (C), and then 1 A single-layer or multi-layer second planarization layer (N2) is deposited or grown on the planarization layer (N1). For example, the first planarization layer (N1) may be aluminum nitride (AlN) for high heat dissipation, and the second planarization layer (N2) may be silicon oxide (SiO ₂ ) to facilitate planarization. (N1) may be silicon oxide (SiO ₂ ) to strengthen adhesion, and the second planarization layer (N2) may be aluminum nitride (AlN) for high heat dissipation, but is not limited thereto and various combinations are possible as needed.

Afterwards, the surface on which the first planarization layer (N1) and the second planarization layer (N2) were formed or grown is planarized through a CMP process, and the physical properties of the first planarization layer (N1) or the second planarization layer (N2) are The degree of flattening can be adjusted accordingly. That is, as shown in FIG. 16, when the first planarization layer (N1) is aluminum nitride (AlN) and the second planarization layer (N2) is silicon oxide (SiO ₂ ), the second planarization layer (N2) is used in terms of heat dissipation. ) is preferably etched (case 3 in FIG. 16), and in the case where the first planarization layer (N1) is silicon oxide (SiO ₂ ) and the second planarization layer (N2) is aluminum nitride (AlN), in terms of heat dissipation It is preferable that the second planarization layer (N2) is hardly etched (case 1 in FIG. 16).

The eighth step (S408) is a step of forming the first bonding layer (B1) on the group 3 nitride semiconductor layer (C). Here, the first bonding layer (B1) is a metal or alloy such as aluminum (Al), tungsten (W), molybdenum (Mo), silicon oxide (SiO _x ), silicon nitride (SiN _x ), or aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon (Si), zinc oxide (ZnO), C ₆₀ (Fullerene), or furthermore, to improve surface roughness _, a flowable oxide (FO In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

The ninth step (S409) is a step of forming the second bonding layer (B2) on the support substrate (S). Here, the second bonding layer (B2), like the first bonding layer (B1), is made of a metal or alloy such as aluminum (Al), tungsten (W), molybdenum (Mo), silicon oxide (SiO _x ), or silicon nitride (SiN). _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon ( _Flowable oxides ( _FO Additional information may be included. In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

Meanwhile, each of the first bonding layer (B1) and the second bonding layer (B2) may include a bonding reinforcement layer (R), a surface planarization layer (F), and a bonding layer (J).

Figure 9 shows in detail the first bonding layer (B1) and the second bonding layer (B2) of the semiconductor template manufacturing method according to the first and second embodiments of the present invention.

As shown in Figure 9, the bonding reinforcement layer (R) is a group 3 nitride semiconductor layer (C) (in the case of the first bonding layer (B1)) or a support substrate (S) (in the case of the second bonding layer (B2)). In order to strengthen the bond with each other, this bond reinforcement layer (R) is, for example, silicon oxide (SiO _x ), silicon nitride (SiN _x ), chromium (Cr), titanium (Ti), molybdenum Mo), may include HMDS.

The surface planarization layer (F) is used to alleviate the roughness of the surface of the group 3 nitride semiconductor layer (C) or the support substrate (S), respectively. This surface planarization layer (F) is used, for example, to improve surface roughness. It may include silicon oxide (SiO _x ), silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), and amorphous or polycrystalline silicon (Si). Furthermore, it may further include a flowable oxide (FO _x ) such as SOG (Spin On Glass) and HSQ (Hydrogen Silsesquioxane).

The bonding layer (J) is for bonding the first bonding layer (B1) and the second bonding layer (B2) to each other, and may be prepared with a permanent bonding material, such as aluminum (Al) or tungsten (W). ), metals or alloys such as molybdenum (Mo), silicon oxide (SiO _x ), silicon nitride (SiN _x ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), indium nitride (InN), amorphous or polycrystalline silicon (Si), zinc oxide (ZnO), C ₆₀ (Fullerene), or even SOG (Spin) to improve surface roughness. On Glass), HSQ (Hydrogen Silsesquioxane), etc. may additionally include a flowable oxide (FO _x ). In particular, it is preferable to use a chemical vapor deposition (CVD) process such as MOCVD or ALD for aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), gallium indium nitride (GaInN), and indium nitride (InN) materials. do.

On the other hand, the above-described bonding reinforcement layer (R) and surface planarization layer (F) can be selectively introduced or deleted depending on the process, and when the bonding strengthening layer (R) and surface planarization layer (F) are deleted depending on the process, , the bonding layer (J) can be formed directly with the group 3 nitride semiconductor layer (C) (in the case of the first bonding layer (B1)) or the support substrate (S) (in the case of the second bonding layer (B2)). there is.

The tenth step (S410) is a step of forming a bonding layer (B) by bonding the first bonding layer (B1) and the second bonding layer (B2) to each other. That is, the tenth step is to flip the group III nitride semiconductor layer (C) on which the first bonding layer (B1) is formed (deposited) and the temporary substrate (T) over the support substrate (S) on which the second bonding layer (B2) is formed. This is the step of bonding by pressurizing at a temperature below 300℃.

Typically, in order to minimize wafer bow after bonding, it is optimal to select the material of the support substrate (S) so that the difference in coefficient of thermal expansion (CTE) from the temporary substrate (T) is less than 2ppm, but high heat dissipation ability The difference in coefficient of thermal expansion (CTE) between the polycrystalline aluminum nitride (AlN) ceramic support substrate (S) and the temporary substrate (T) is more than 2 ppm, making it realistically difficult to bond wafers at high temperatures. In this case, setting the bonding process temperature near room temperature and performing the process can minimize stress and prevent wafer bending.

The 11th step (S411) is a step of separating the temporary substrate (T) from the adhesive layer (A) using a laser lift off (LLO) technique.

The twelfth step (S412) is a step of separating the adhesive layer (A) from the nitride semiconductor layer (C) having a Group 3 metal polarity (M-polarity) surface. Thereafter, contaminated Group 3 metal (M) polar surface residues can be removed.

In particular, in the twelfth step (S412), prior to the thirteenth step (S413) of growing the device active layer (U) structure, the group III nitride semiconductor layer (C) from which the temporary substrate (T) is separated is grown at a high temperature of 700°C or higher. The weak bonding layer (B) formed between the first bonding layer (B1) and the second bonding layer (B2) can be strengthened by heat treatment (annealing).

The thirteenth step (S413) is a step of growing the device active layer (U) on the nitride semiconductor layer (C) having a Group 3 metal (M) polar surface. That is, through the previous steps, a semiconductor device active layer (U) structure containing a desired compound can be finally grown on the upper surface of the group III nitride semiconductor layer (C) formed on the high heat dissipation support substrate (S). For example, in the case of a GaN material-based power semiconductor structure, the device active layer (U) is typically 1) GaN buffer layer (horizontal and vertical transistor), 2) GaN channel layer (horizontal transistor) or drift layer. Drift Layer (vertical transistor), 3) AlGaN Barrier Layer (horizontal transistor) or p-type Nitride Semiconductor Layer (vertical transistor), 4) Capping Passivation Layer Layer; horizontal transistor), p-type nitride semiconductor layer (horizontal transistor), or capping passivation layer (vertical transistor) can be formed by stacking four areas.

The first step (S401), the second step (S402), the third step (S403), the fourth step (S404), the fifth step (S405), and the sixth step (S406) as described above. , the 7th step (S407), the 8th step (S408), the 9th step (S409), the 10th step (S410), the 11th step (S411), and the 12th step (S412), According to the group 3 nitride semiconductor template manufacturing method (S400) according to the fourth embodiment of the present invention including the 13th step (S413) and the group 3 nitride semiconductor template manufactured thereby, the group 3 nitride semiconductor layer ( A high heat dissipation support substrate (S) having the same or similar coefficient of thermal expansion (CTE) as C), a high-quality Group 3 nitride thin film material, and a Group 3 nitride single crystal growth layer for the growth of a power semiconductor device structure using the same are highly heat-resistant. Since they can be bonded through a bonding layer, it is possible to form a high-quality Group 3 nitride semiconductor layer at a high temperature of 700°C or higher. In other words, the Group 3 nitride thin film material, the power semiconductor device structure using the same, and the support substrate may have the same or similar lattice constant (LC) and coefficient of thermal expansion (CTE), so the structural and thermo-mechanical factors that occur during growth are affected. Stress (Thermo-mechanical Induced Stress) can be minimized.

In addition, according to the present invention, the pattern (P) can be etched at a preset depth in the group 3 nitride semiconductor layer (C) or bonding layer (B), which is advantageous for the wafer bonding process. In other words, in the case of direct contact wafer bonding, it is quite sensitive to the surface roughness of the wafer bonding surface and the wafer bow, but according to the patterning of the present invention, strict wafer surface roughness It has the advantage of significantly alleviating the and bending issues. In addition, according to the patterning of the present invention, it is possible to facilitate the discharge of gas generated inside the bonding layer (B) during the wafer bonding process, thereby strengthening the bonding strength of the bonding layer (B) in a void-free manner. It can also buffer structural and thermal-mechanical induced stress more effectively.

In addition, according to the present invention, the high heat dissipation support substrate (S) is formed of polycrystalline ceramic, so it has an advantage in terms of cost competitiveness compared to single crystalline ceramic.

In addition, according to the present invention, the polarity of the surface of the semiconductor layer (C) initially grown on the growth substrate (G) and the surface of the semiconductor layer (C) finally formed on the support substrate (S) can be the same. In order to successfully implement this, a process must be introduced, such as the present invention, to turn the rough surface into a mirror-like surface due to the laser damage area generated during the above-described process and the inherently existing ID and IDB. .

In the above, just because all the components constituting the embodiment of the present invention have been described as being combined or operated in combination, the present invention is not necessarily limited to this embodiment. That is, as long as it is within the scope of the purpose of the present invention, all of the components may be operated by selectively combining one or more of them.

In addition, terms such as “include,” “comprise,” or “have” described above mean that the corresponding component may be present, unless specifically stated to the contrary, and thus do not exclude other components. Rather, it should be interpreted as being able to include other components. All terms, including technical or scientific terms, unless otherwise defined, have the same meaning as generally understood by a person of ordinary skill in the technical field to which the present invention pertains. Commonly used terms, such as terms defined in a dictionary, should be interpreted as consistent with the contextual meaning of the related technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the present invention.

The above description is merely an illustrative explanation of the technical idea of the present invention, and those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of the present invention.

Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

S100: Group III nitride semiconductor template manufacturing method according to the first embodiment of the present invention
S101: Step 1
S102: Second stage
S103: Step 3
S104: Step 4
S105: Step 5
S106: Step 6
S107: Step 7
S108: Step 8
S200: Group 3 nitride semiconductor template manufacturing method according to the second embodiment of the present invention
S201: Step 1
S202: Second stage
S203: Step 3
S204: Step 4
S205: Step 5
S206: Step 6
S207: Step 7
S208: Step 8
S209: Step 9
S210: Step 10
S211: Step 11
S212: Step 12
S213: Step 13
S300: Group 3 nitride semiconductor template manufacturing method according to the third embodiment of the present invention
S301: Step 1
S302: Second stage
S303: Third stage
S304: Step 4
S305: Step 5
S306: Step 6
S307: Step 7
S308: Step 8
S400: Group 3 nitride semiconductor template manufacturing method according to the fourth embodiment of the present invention
S401: Step 1
S402: Second stage
S403: Step 3
S404: Step 4
S405: Step 5
S406: Step 6
S407: Step 7
S408: Step 8
S409: Step 9
S410: Step 10
S411: Step 11
S412: Step 12
S413: Step 13
G: growth substrate
T: Temporary board
S: Support substrate
C: semiconductor layer
A: Adhesive layer
A1: first adhesive layer
A2: Second adhesive layer
N: Flattening layer
N1: first planarization layer
N2: second planarization layer
B: bonding layer
B1: first bonding layer
B2: second bonding layer
R: bond reinforcement layer
F: Surface flattening layer
J: bonding layer
W: transition layer
U: device active layer

Claims (17)

In the method of manufacturing a group III nitride semiconductor template for power semiconductor devices,
A first step of preparing a growth substrate and a support substrate;
A second step of growing a semiconductor layer on the growth substrate;
A third step of forming a first bonding layer on the semiconductor layer;
A fourth step of forming a second bonding layer on the support substrate;
A fifth step of forming a bonding layer by bonding the first bonding layer and the second bonding layer to each other;
A sixth step of separating the growth substrate from the semiconductor layer; and
A group 3 nitride semiconductor template manufacturing method comprising a seventh step of forming a conversion layer on the semiconductor layer for converting the surface polarity of the semiconductor layer to the group 3 metal polarity. In claim 1,
The sixth step is,
A method of manufacturing a group III nitride semiconductor template, in which the growth substrate is separated from the semiconductor layer using a laser lift off (LLO) technique. In claim 1,
A method for manufacturing a Group III nitride semiconductor template, further comprising an eighth step of growing a device active layer on the conversion layer. In claim 1,
The seventh step is,
A method of manufacturing a Group 3 nitride semiconductor template by etching a plurality of patterns on the conversion layer. In claim 1,
The seventh step is,
A method of manufacturing a Group III nitride semiconductor template, wherein a plurality of regular patterns are etched on the semiconductor layer, and the transition layer is formed according to the pattern of the semiconductor layer. In claim 1,
The seventh step is,
A method of manufacturing a group III nitride semiconductor template, comprising etching a plurality of irregular patterns on the semiconductor layer, flattening each end of the pattern, and then forming the transition layer along the pattern of the semiconductor layer. In claim 1,
Each of the first bonding layer and the second bonding layer,
A bonding reinforcement layer to strengthen bonding with the support substrate or the semiconductor layer,
a surface planarization layer to alleviate surface roughness of the support substrate or the semiconductor layer;
A method for manufacturing a Group III nitride semiconductor template, comprising a bonding layer for bonding the first bonding layer and the second bonding layer to each other. In claim 1,
The support substrate is,
Method for manufacturing a Group 3 nitride semiconductor template, which is a polycrystalline AlN ceramic substrate. In the method of manufacturing a group III nitride semiconductor template for power semiconductor devices,
A first step of preparing a growth substrate, temporary substrate, and support substrate;
A second step of growing a semiconductor layer on the growth substrate;
A third step of forming a first adhesive layer on the semiconductor layer;
A fourth step of forming a second adhesive layer on the temporary substrate;
A fifth step of forming an adhesive layer by adhering the first adhesive layer and the second adhesive layer to each other;
A sixth step of separating the growth substrate from the semiconductor layer;
A seventh step of converting the rough surface of the semiconductor layer from which the growth substrate is separated into a mirror-like surface;
An eighth step of forming a first bonding layer on the semiconductor layer;
A ninth step of forming a second bonding layer on the support substrate;
A tenth step of forming a bonding layer by bonding the first bonding layer and the second bonding layer to each other;
An 11th step of separating the temporary substrate from the adhesive layer;
A twelfth step of separating the adhesive layer from the semiconductor layer; and
A group 3 nitride semiconductor template manufacturing method comprising a 13th step of growing a device active layer on the semiconductor layer. In claim 9,
The sixth step is,
Separating the growth substrate from the semiconductor layer using a laser lift off (LLO) technique,
The 11th step is,
A method of manufacturing a Group III nitride semiconductor template, wherein the temporary substrate is separated from the adhesive layer using a laser lift-off technique. delete In claim 9,
The seventh step is,
A method of manufacturing a Group III nitride semiconductor template, in which a planarization layer is formed on the semiconductor layer, and then the semiconductor layer is mirror-surfaced by planarizing the planarization layer. In claim 9,
The seventh step is,
A method of manufacturing a group III nitride semiconductor template, wherein the semiconductor layer is mirror-surfaced by directly planarizing the upper surface of the semiconductor layer. In claim 9,
The seventh step is,
Etching a plurality of patterns on the upper surface of the semiconductor layer, forming a first planarization layer according to the pattern of the semiconductor layer, forming a second planarization layer on the first planarization layer, and forming the first planarization layer or the A method of manufacturing a Group III nitride semiconductor template, wherein the semiconductor layer is mirror-surfaced by planarizing a second planarization layer. In claim 9,
Each of the first bonding layer and the second bonding layer,
A bonding reinforcement layer to strengthen bonding with the support substrate or the semiconductor layer,
a surface planarization layer to alleviate surface roughness of the support substrate or the semiconductor layer;
A method for manufacturing a Group III nitride semiconductor template, comprising a bonding layer for bonding the first bonding layer and the second bonding layer to each other. In claim 9,
The support substrate is,
Method for manufacturing a Group 3 nitride semiconductor template, which is a polycrystalline AlN ceramic substrate. delete