KR102615811B1 - Method for manufacturing group 3 nitride semiconductor template using chemical lift off and group 3 nitride semiconductor template manufactured by the same - Google Patents

Abstract

The present invention relates to a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique, comprising: a first step of preparing a growth substrate, a temporary substrate, and a support substrate; a second step of forming a first sacrificial layer on the growth substrate, growing a first buffer layer on the first sacrificial layer, and then growing a channel layer on the first buffer layer; A third step of forming an epitaxial protective layer on the channel layer and then forming a first adhesive layer on the epitaxial protective layer; A fourth step of forming a second sacrificial layer on the temporary substrate and then forming a second adhesive layer on the second sacrificial layer; A fifth step of forming an adhesive layer by adhering the first adhesive layer and the second adhesive layer to each other; A sixth step of separating the growth substrate from the first sacrificial layer using a chemical lift off (CLO) technique; A seventh step of etching and removing the first sacrificial layer, or etching and removing the first sacrificial layer and the first buffer layer; An eighth step of forming a first bonding layer on the first buffer layer or forming the first bonding layer on the channel layer; A ninth step of forming a second bonding layer on the support substrate; A tenth step of forming a bonding layer by bonding the first bonding layer and the second bonding layer to each other; An 11th step of separating the temporary substrate from the second sacrificial layer using a chemical lift off (CLO) technique; and a twelfth step of etching and removing the second sacrificial layer, the adhesive layer, and the epitaxial protective layer.
According to the present invention, a reinforcing layer including a bonding reinforcing layer with high-resistance insulating properties and a condensation stress layer is formed on the upper surface (lower part of the group 3 nitride semiconductor layer) or lower surface (upper part of the support substrate) of the bonding layer. Since leakage current to the support substrate (or in the vertical direction) can be effectively blocked, there is no need for a low-quality, high-resistance gallium nitride (GaN) buffer layer doped with iron (Fe) or carbon (C). . Accordingly, by removing the low-quality, high-resistance gallium nitride (GaN) buffer layer, it is possible to secure a HEMT active region such as a high-quality gallium nitride (GaN) channel layer and aluminum gallium nitride (AlGaN) barrier layer, thereby enabling power generation. The reliability and performance of semiconductor devices can be dramatically improved.

Description

Method for manufacturing a group 3 nitride semiconductor template using a chemical lift-off technique and a group 3 nitride semiconductor template manufactured thereby

The present invention relates to a method for manufacturing a Group 3 nitride semiconductor template using a chemical lift-off technique and a Group 3 nitride semiconductor template manufactured thereby, and more specifically, using a Chemical Lift Off (CLO) technique. A group 3 nitride semiconductor template using a chemical lift-off technique allows a high-quality group 3 nitride semiconductor layer to be formed on the top of a high heat dissipation support substrate having an epitaxial growth surface with the same or similar lattice constant. It relates to a manufacturing method and a group 3 nitride semiconductor template manufactured thereby.

In a GaN material-based power semiconductor (HEMT, High Electron Mobility Transistor) device with a horizontal channel structure based on technology that grows GaN material directly on top of a conventional Si single crystal growth substrate wafer, the device is operated at high temperature. In order to be stably driven with high voltage and/or high-speed switching functions, a design that suppresses leakage current of power semiconductor devices through high-quality epitaxial thin film growth technology with high breakdown voltage and high reliability characteristics is essential.

To this end, conventional group III nitride semiconductor thin film materials and their power semiconductor device structures are 1) equipped with a Si single crystal growth substrate wafer with high electrical resistance characteristics, and 2) through reaction at high temperature with the surface layer of the Si single crystal growth substrate wafer. 3) Growth of a melt-back etching prevention layer containing an AlN material system (nitride or nitride oxide containing Al composition) to suppress the melt-back etching phenomenon, and 3) AlGaN material system (Group 3 nitride with Al or Ga composition). It has a structure in which the growth of a condensed stress layer for crack prevention and 4) the growth of a power semiconductor active layer containing GaN material (group 3 nitride containing Ga composition) are sequentially stacked.

And the power semiconductor active layer (HEMT, High Electron Mobility Transistor) of the horizontal channel structure containing the above-mentioned GaN material system is usually composed of 1) GaN buffer layer, 2) GaN channel layer. ; Horizontal Transistor), 3) AlGaN Barrier Layer, 4) Capping Passivation Layer (Depletion Mode) or p-type Nitride Semiconductor Layer (Enhancement Mode). It is formed by layering.

That is, in the Group III nitride power semiconductor HEMT device structure in which the GaN material system is grown directly on the top of the conventional Si single crystal growth substrate wafer, a GaN buffer layer with high resistance is formed under the GaN channel layer and a Si single crystal growth substrate with high resistance is formed. Although wafers are always used, there are the following problems.

First, in the conventional Group 3 nitride (GaN material-based) power semiconductor HEMT device structure, MOCVD (Metal Organic Chemical Vapor Deposition) equipment is used to form a GaN material-based single crystal thin film on the top of the Si single crystal wafer for the Group 3 nitride power semiconductor growth substrate. and perform a process to directly grow the power semiconductor device structure. At this time, a GaN material-based single crystal thin film growth (film formation) process containing Ga atoms is basically performed at a high temperature of around 1000°C and in a reducing atmosphere (H ₂ , H ⁺ , NH ₃ , radical ions), between the surface layer of the Si single crystal wafer and the Ga atoms. A melt-back etching prevention film area that blocks active Si-Ga metallic eutectic reactions with relatively small energy is absolutely necessary.

This melt-back etching prevention film area typically has a thickness of around 100 nm, and the representative example is the AlN material layer grown through an in-situ process within the MOCVD chamber, but it can also be used on other external film formation (deposition) process equipment. Before loading into the MOCVD chamber using (sputter, PLD, ALD), a layer of AlN (aluminum nitride) or AlNO (aluminium nitride oxide) material is spread on the top of a Si single crystal wafer for a Group 3 nitride power semiconductor growth substrate. It can also be formed (deposited) through an ex-situ process.

However, when forming a melt-back etching prevention film area with the above-described AlN material layer on the top of a Si single crystal wafer for a growth substrate with high electrical resistance characteristics, the level of damage to the surface of the Si growth substrate during AlN growth is less, but still Si There is a problem in that a Si-Al metallic process reaction occurs entirely or locally on the surface of the growth substrate, forming a conductive interface material layer, which causes a decrease in the crystal quality of the GaN material system grown in a continuous process. In addition, damage to the surface of the Si growth substrate causes a decrease in crystal quality (reduced crystallinity) due to the formation of a conductive interface material (disordered SiAlN), and as a result, the density of “dislocations”, which are major crystal defects, increases, resulting in an increase in leakage current, which ultimately leads to an increase in leakage current. There is a problem that promotes insulation breakdown.

Second, in the above-described conventional Group III nitride (GaN material-based) power semiconductor HEMT device structure, when growing (or forming a film) a material, the lattice constant (LC), which is the material intrinsic value between different heterogeneous materials, The process must be carried out considering the coefficient of thermal expansion (CTE). Typically, when the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between two materials is large, during or after the growth (film formation) process. Due to structural and thermo-mechanical stress, micro (fine) or macro (macro) cracks inevitably occur within the grown (film-formed) material thin film or crystal quality deteriorates. In particular, when directly growing (or forming a film) a gallium nitride (GaN) material system or aluminum nitride (AlN) material system on the top of a Si single crystal wafer for a Group 3 nitride power semiconductor growth substrate, the coefficient of thermal expansion (CTE) and/or lattice constant In terms of (LC), tensile stress is generated strongly, so not only can the crack phenomenon be easily observed, but it can also grow beyond a certain thickness to realize a high breakdown voltage and high reliability device. Due to the tensile stress, group 3 The thickness of the nitride power semiconductor device structure cannot be increased.

Several technologies have been devised as a way to relieve the above-described tensile stress or suppress cracks, but it is difficult to introduce materials and processes that artificially generate compressive stress to compensate and buffer the tensile stress. As a solution, a crack-prevention condensation stress layer that suppresses the crack phenomenon is introduced and used by laminating AlGaN material containing Al or Ga composition on the melt-back etching prevention film area in a known multi-layer structure.

However, the condensation stress layer for crack prevention in the above-described conventional Group 3 nitride (GaN material system) power semiconductor HEMT device structure is difficult to grow a thick layer with high quality when forming an AlGaN material system with a high Al ratio, and dislocations occur due to a decrease in crystal quality. There is a problem that occurs and promotes an increase in leakage current.

Third, in the conventional Group 3 nitride (GaN material-based) power semiconductor HEMT device structure, impurities such as Fe (iron) or C (carbon) are usually added to have high resistance to suppress leakage current under the GaN channel layer. An excessively doped GaN buffer layer is formed.

However, according to the conventional Group 3 nitride (GaN material system) power semiconductor HEMT device structure, the crystal quality of the GaN material system is greatly reduced due to impurities such as excessively doped Fe or C, and fatal crystal defects, i.e. dislocations, occur. There is a problem in that an increase in density promotes an increase in leakage current. Additionally, due to the low crystal quality of the GaN buffer layer, there is a problem in that the GaN channel layer and AlGaN barrier layer grown thereon in a continuous process also have low crystal quality.

Republic of Korea Patent Publication No. 10-2122846

The purpose of the present invention is to solve the above-described conventional problems, and by using the Chemical Lift Off (CLO) technique, a high-quality Group III nitride semiconductor layer has an equal or similar lattice constant. The present invention provides a method for manufacturing a Group 3 nitride semiconductor template using a chemical lift-off technique that can be formed on a high heat dissipation support substrate having an epitaxial growth surface, and a Group 3 nitride semiconductor template manufactured thereby.

The above object is, according to the present invention, a first step of preparing a growth substrate, a temporary substrate, and a support substrate; a second step of forming a first sacrificial layer on the growth substrate, growing a first buffer layer on the first sacrificial layer, and then growing a channel layer on the first buffer layer; A third step of forming an epitaxial protective layer on the channel layer and then forming a first adhesive layer on the epitaxial protective layer; A fourth step of forming a second sacrificial layer on the temporary substrate and then forming a second adhesive layer on the second sacrificial layer; A fifth step of forming an adhesive layer by adhering the first adhesive layer and the second adhesive layer to each other; A sixth step of separating the growth substrate from the first sacrificial layer using a chemical lift off (CLO) technique; A seventh step of etching and removing the first sacrificial layer, or etching and removing the first sacrificial layer and the first buffer layer; An eighth step of forming a first bonding layer on the first buffer layer or forming the first bonding layer on the channel layer; A ninth step of forming a second bonding layer on the support substrate; A tenth step of forming a bonding layer by bonding the first bonding layer and the second bonding layer to each other; An 11th step of separating the temporary substrate from the second sacrificial layer using a chemical lift off (CLO) technique; and a twelfth step of etching and removing the second sacrificial layer, the adhesive layer, and the epitaxial protective layer.

Additionally, in the ninth step, a reinforcing layer may be formed on the support substrate, and then the second bonding layer may be formed on the reinforcing layer.

Additionally, in the seventh step, the first sacrificial layer and the first buffer layer may be removed by etching, and in the eighth step, the first bonding layer may be formed on the channel layer.

Additionally, in the eighth step, a reinforcing layer may be formed on the channel layer, and then the first bonding layer may be formed on the reinforcing layer.

Additionally, in the seventh step, the first sacrificial layer may be removed by etching, and in the eighth step, the first bonding layer may be formed on the first buffer layer.

Additionally, in the eighth step, a reinforcement layer may be formed on the first buffer layer, and then the first bonding layer may be formed on the reinforcement layer.

Additionally, in the eighth step, a second buffer layer may be deposited on the channel layer, and then the first bonding layer may be formed on the second buffer layer.

Additionally, in the eighth step, a second buffer layer may be deposited on the first buffer layer, and then the first bonding layer may be formed on the second buffer layer.

Additionally, in the eighth step, a reinforcing layer may be formed on the formed second buffer layer, and then the first bonding layer may be formed on the reinforcing layer.

Additionally, the growth substrate may be a silicon (Si) growth substrate, and the support substrate may be a silicon (Si) support substrate.

Additionally, the first buffer layer may include a gallium nitride (GaN) material.

Additionally, the second buffer layer may include nitride or oxide containing aluminum.

The above object is, according to the present invention, a first step of preparing a growth substrate, a temporary substrate, and a support substrate; a second step of forming a first sacrificial layer on the growth substrate and growing a buffer layer on the first sacrificial layer; A third step of forming an epitaxial protective layer on the buffer layer and then forming a first adhesive layer on the epitaxial protective layer; A fourth step of forming a second sacrificial layer on the temporary substrate and then forming a second adhesive layer on the second sacrificial layer; A fifth step of forming an adhesive layer by adhering the first adhesive layer and the second adhesive layer to each other; A sixth step of separating the growth substrate from the first sacrificial layer using a chemical lift off (CLO) technique; A seventh step of etching and removing the first sacrificial layer; An eighth step of forming a first bonding layer on the buffer layer; A ninth step of forming a second bonding layer on the support substrate; A tenth step of forming a bonding layer by bonding the first bonding layer and the second bonding layer to each other; An 11th step of separating the temporary substrate from the second sacrificial layer using a chemical lift off (CLO) technique; and a twelfth step of etching and removing the second sacrificial layer, the adhesive layer, and the epitaxial protective layer.

Additionally, in the ninth step, a reinforcing layer may be formed on the support substrate, and then the second bonding layer may be formed on the reinforcing layer.

Additionally, in the eighth step, a reinforcing layer may be formed on the buffer layer, and then the first bonding layer may be formed on the reinforcing layer.

Additionally, the buffer layer may include a gallium nitride (GaN) material.

Additionally, the buffer layer may include nitride or oxide containing aluminum.

The above object is achieved by a group III nitride semiconductor template manufactured by a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique, according to the present invention.

According to the present invention, a reinforcing layer including a bonding reinforcing layer with high-resistance insulating properties and a condensation stress layer is formed on the upper surface (lower part of the group 3 nitride semiconductor layer) or lower surface (upper part of the support substrate) of the bonding layer. Since leakage current to the support substrate (or in the vertical direction) can be effectively blocked, there is no need for a low-quality, high-resistance gallium nitride (GaN) buffer layer doped with iron (Fe) or carbon (C). . Accordingly, by removing the low-quality, high-resistance gallium nitride (GaN) buffer layer, it is possible to secure a HEMT active region such as a high-quality gallium nitride (GaN) channel layer and aluminum gallium nitride (AlGaN) barrier layer, thereby enabling power generation. The reliability and performance of semiconductor devices can be dramatically improved.

In addition, according to the present invention, there is no need for direct growth of the melt-back etching prevention layer and condensation stress layer, which were essential for the growth substrate of the prior art, and thus a high-quality aluminum gallium nitride (AlGaN) barrier is formed on the high-quality Group III nitride semiconductor layer. Layers can grow. Additionally, compared to the conventional method of growing directly on top of a silicon (Si) growth substrate, a high-quality Group III nitride semiconductor layer with low defects can be grown. In addition, as the growth of the melt-back etching prevention layer and the condensation stress layer is excluded, it is possible to implement a Group 3 nitride power semiconductor structure (particularly HEMT) with a thinner thickness than before, and material costs and yield can be improved. .

In addition, according to the present invention, a condensation stress layer is introduced between the gallium nitride (GaN) material system (gallium nitride (GaN) buffer or gallium nitride (GaN) channel) and the silicon (Si) growth substrate through an external deposition (film formation) process. In other words, it can be used as a condensed stress layer such as aluminum gallium nitride (AlGaN) or superlattice structured aluminum/gallium nitride (AlN/GaN SLs) grown through an in-situ process in a MOCVD chamber. It is possible to grow a thick-film gallium nitride (GaN) material system with a predetermined thickness or more without cracks. In addition, instead of the gallium nitride (GaN) buffer layer and the gallium nitride (GaN) channel layer, aluminum nitride (AlN) and aluminum oxide (Al ₂ O) are used, which have a leakage current blocking function and a thermal expansion coefficient greater than that of the silicon (Si) support substrate. ₃ ) etc. can be grown thickly, and it is possible to implement power semiconductor devices using this.

In addition, through two chemical lift off (CLO) processes, a surface with intact group 3 metal polarity (a structure where the polarity of the growth substrate separation surface and the final support substrate bonding surface is the same) is created. ), so it is possible to re-grow a high-quality Group III nitride semiconductor thin film.

Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within the range apparent to those skilled in the art from the contents described below.

1 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to a first embodiment of the present invention;
Figure 2 shows the process of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the first embodiment of the present invention;
Figure 3 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to a second embodiment of the present invention;
Figure 4 shows the process of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the second embodiment of the present invention.
Figure 5 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to a third embodiment of the present invention;
Figure 6 shows the process of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the third embodiment of the present invention.
Figure 7 shows another process of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the third embodiment of the present invention.
Figure 8 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the fourth embodiment of the present invention;
Figure 9 shows the process of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the fourth embodiment of the present invention.
Figure 10 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the fifth embodiment of the present invention;
Figure 11 shows the process of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the fifth embodiment of the present invention.
Figure 12 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the sixth embodiment of the present invention;
Figure 13 shows the process of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the sixth embodiment of the present invention.
Figure 14 shows various forms of reinforcement layers disposed on a group III nitride semiconductor template manufactured according to the first to sixth embodiments of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail through illustrative drawings. When adding reference numerals to components in each drawing, it should be noted that identical components are given the same reference numerals as much as possible even if they are shown in different drawings.

Additionally, when describing embodiments of the present invention, if detailed descriptions of related known configurations or functions are judged to impede understanding of the embodiments of the present invention, the detailed descriptions will be omitted.

Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, or order of the component is not limited by the term.

From now on, with reference to the attached drawings, a method (S100) for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the first embodiment of the present invention will be described in detail.

Figure 1 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the first embodiment of the present invention, and Figure 2 is a group using the chemical lift-off technique according to the first embodiment of the present invention. This shows the process of manufacturing a group III nitride semiconductor template.

As shown in Figures 1 and 2, the method (S100) for manufacturing a group 3 nitride semiconductor template using a chemical lift-off technique according to the first embodiment of the present invention includes a first step (S101) and a second step. Step (S102), third step (S103), fourth step (S104), fifth step (S105), sixth step (S106), seventh step (S107), and eighth step ( It includes the ninth step (S109), the tenth step (S110), the eleventh step (S111), the twelfth step (S112), and the thirteenth step (S113).

The first step (S101) is a step of preparing a growth substrate (G), a temporary substrate (T), and a support substrate (110).

The growth substrate (G) is prepared as a silicon (Si) growth substrate (G) capable of mechanical polishing and selective etching, and the silicon (Si) growth substrate (G) is used to enable the growth of a high-quality group III nitride semiconductor thin film (G). 111) It is preferable that it is made of silicon (Si) with a crystal plane.

The temporary substrate (T) is prepared as a silicon (Si) substrate to minimize the difference in coefficient of thermal expansion (CTE) between the growth substrate (G) described above as well as the support substrate 110 described later, and is temporarily bonded during the manufacturing process. Since it is a low-cost silicon (Si) substrate, it is desirable to prepare it as a low-cost silicon (Si) substrate to ensure cost competitiveness.

The support substrate 110 is formed into a channel layer 150 and a re-growth layer 160 after going through each step of the method (S100) of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the first embodiment of the present invention. It is a substrate that supports.

This support substrate 110 is preferably provided as a silicon (Si) support substrate 110 with high heat dissipation ability, and the silicon (Si) support substrate 110 may be single crystalline, polycrystalline, or amorphous, ( It may be formed of silicon (Si) with a 111) crystal plane, a (110) crystal plane, or a (100) crystal plane.

Furthermore, in addition to the above-described silicon (Si), it may include at least one material selected from materials including silicon carbide (SiC), aluminum nitride (AlN), and sapphire. In particular, silicon carbide (SiC) and aluminum nitride (AlN) may be single crystalline or polycrystalline.

In the second step (S102), a first sacrificial layer (N1) is formed on the growth substrate (G), and then a high-quality group 3 nitride semiconductor layer (group 3 nitride semiconductor buffer layer and channel) is formed on the first sacrificial layer (N1). A step of growing a high-quality first buffer layer 140 as a single-layer or multi-layer layer on the first sacrificial layer (N1), and growing a high-quality first buffer layer 140 on the first buffer layer 140. This is the step of growing the channel layer 150 into a single layer or multiple layers.

At this time, a layer other than the high-quality first buffer layer 140 and the high-quality channel layer 150 on the first sacrificial layer (N1) is a high-quality Group 3 group that is an insulating material with high electrical resistance (Highly Electrical Resistive Insulator). A single layer or multiple layers made of nitride may be formed (grown) on the first sacrificial layer (N1).

Here, the first sacrificial layer (N1) is a layer necessary for growing a high-quality group III nitride semiconductor layer, and includes a melt-back etching prevention layer and a crack prevention layer.

The melt-back etching prevention layer has a thickness of less than 500 nm and is formed on the growth substrate (G) and contains aluminum nitride (AlN). This melt-back etching prevention layer is a (111) crystal plane of the Group 3 nitride semiconductor layer (including the Group 3 nitride semiconductor buffer layer and the channel layer, that is, the first buffer layer 140 and the channel layer 150) to be grown on the top. It serves as a buffer so that it can be grown directly on the silicon (Si) growth substrate (G), minimizes crystal defects in the group 3 nitride semiconductor layer, and serves as a silicon growth substrate when growing on a gallium nitride (GaN) material. It performs the function of preventing chemical interface reaction between the surface and Ga-Si.

The crack prevention layer has a thickness of less than 1㎛, is formed on the melt-back etching prevention layer, and contains aluminum gallium nitride (AlGaN). This crack prevention layer is a layer introduced to artificially introduce condensation stress inside the high-quality Group III nitride semiconductor layer and prevent cracks when cooling to room temperature after growth, and may be omitted in some cases.

In addition, the Group 3 nitride semiconductor layer (including the Group 3 nitride semiconductor buffer layer and the channel layer, that is, the first buffer layer 140 and the channel layer 150) is composed of a single or multi-layer Group 3 nitride semiconductor, Gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AlN) with high temperature (HT) and high resistance (HR) characteristics, aluminum gallium nitride/gallium nitride (AlGaN/GaN SLs) with superlattice structure, Aluminum nitride/gallium nitride (AlN/GaN SLs) with lattice structure, aluminum gallium nitride/aluminum nitride (AlGaN/AlN SLs) with superlattice structure, indium gallium nitride (InGaN), indium aluminum nitride (InAlN), gallium nitride/nitride It may be composed of indium aluminum (GaN/InAlN), aluminum scandium nitride (AlScN), gallium nitride/aluminum scandium nitride (GaN/AlScN), etc. For this Group 3 nitride semiconductor layer, reducing the density of critical crystal defects, that is, penetration dislocations (existing in a direction perpendicular to the initial growth substrate (G)), is a critical quality factor (≤ Low 10 ⁸ /cm2).

Meanwhile, the surface of the first buffer layer 140 or channel layer 150 formed on the growth substrate (G), and the first buffer layer 140 or channel layer 150 later transferred to the upper part of the temporary substrate (T). Since the surfaces of Minimization of particles such as organic and metallic substances must be achieved. Growth processes that can achieve this include both MOCVD (Metal Organic Chemical Vapor Deposition) and MBE (Molecular Beam Epitaxy) equipment. , it is desirable to perform it through a process with a relatively low growth temperature.

The third step (S103) is a step of forming an epitaxial protective layer (P) on the channel layer 150 and then forming a first adhesive layer (A1) on the epitaxial protective layer (P).

Here, the epitaxial protection layer (P) is a layer to prevent the channel layer 150 from being damaged during the subsequent process, and may be made of a material that takes selective wet etching into consideration, and this epitaxial protective layer (P) is a layer to prevent damage to the channel layer 150 during the subsequent process. For example, the taxi protection layer (P) may preferentially include an oxide including silicon oxide (SiO ₂ ), a nitride including silicon nitride (SiN _x ), and may include metals and alloys.

The fourth step (S104) is a step of forming the second sacrificial layer (N2) on the temporary substrate (T) and then forming the second adhesive layer (A2) on the second sacrificial layer (N2).

Here, the temporary substrate (T) is a substrate that is easily separated by the chemical lift off (CLO) technique in the subsequent process, and is placed on the temporary substrate (T) prior to forming the second adhesive layer (A2). A second sacrificial layer (N2) may be formed, and the second sacrificial layer (N2) includes an adhesion reinforcement layer and an etching stop layer in more detail.

The adhesion reinforcement layer is a layer that strengthens adhesion to the temporary substrate (T) and may include materials such as silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), metal, or alloy.

The etch stop layer functions to protect the adhesive layer and epitaxial protection layer from chemical etching effects during wet etching, and is used to protect the silicon (Si) temporary substrate (T) in the subsequent chemical lift off (CLO) process. After mechanical grinding and polishing, the remaining thin silicon (Si) is wet-etched with TMAH (Tetramethylammonium hydroxide) or HNA (Hydrofluoric + Nitric + Acetic Acids) solution to completely remove the remaining thin silicon (Si). At this time, the etch stop layer is silicon ( After Si) is completely removed, the adhesive layer, epitaxial protection layer, etc. perform the function of protecting against chemical etching effects, and this etch-stop layer may be omitted in some cases.

In addition, the first adhesive layer (A1) and the second adhesive layer (A2) are dielectric materials capable of direct bonding at temperatures below 100°C, including silicon oxide (SiO ₂ ), SOG (Spin On Glass), FOX (Flowable Oxides), _It may _contain materials such as _silicon nitride (SiN It may contain substances such as resin, BCB (Benzocyclobutene), and PI (polyimide).

The fifth step (S105) is a step of forming an adhesive layer (A) by temporarily bonding the first adhesive layer (A1) and the second adhesive layer (A2) to each other in order to separate the initial growth substrate (G). That is, the fifth step (S105) is a step of turning over the temporary substrate (T) on which the second adhesive layer (A2) is formed and bonding it to the growth substrate (G) on which the first adhesive layer (A1) is formed by applying pressure at a temperature of less than 300°C. .

Typically, thermo-mechanical induced tensile stress (Tensile) is generated by the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between the silicon (Si) growth substrate (G) having the initial (111) crystal plane and the group III nitride semiconductor. Due to stress, there is a bow in the concave shape of the epitaxial wafer, but in the present invention, this problem is resolved by strongly bonding a silicon (Si) temporary substrate to the upper surface of the grown Group III nitride semiconductor epitaxial wafer through an adhesive layer. can do. At this time, since the coefficient of thermal expansion (CTE) value between the initial growth substrate (G) and the temporary substrate (T) is almost the same, it is desirable to perform an adhesion process to ensure strong bonding strength regardless of temperature.

The sixth step is a step of separating the growth substrate (G) from the first sacrificial layer (N1) using a chemical lift off (CLO) technique.

Here, the chemical lift-off technique refers to the use of TMAH (Tetramethylammonium hydroxide) or HNA to completely remove the thin silicon (Si) remaining after mechanical grinding and polishing of the back of the silicon (Si) growth substrate (G) with a (111) crystal plane. This is a technique to separate and remove the silicon (Si) material of the initial growth substrate (G) by wet etching with a (Hydrofluoric + Nitric + Acetic Acids) solution. When the first growth substrate (G) is separated, the inside of the channel layer 150 transferred to the temporary substrate (T) is completely free of stress and remains flat along with the temporary substrate (T). Meanwhile, before mechanically polishing the growth substrate (G) and removing the residual silicon (Si) material, a protective film such as silicon oxide (SiO ₂ ) or silicon nitride (SiN _x ) is deposited on the back of the temporary substrate (T). Protection from etching solutions is desirable.

The seventh step (S107) is a step of exposing the channel layer 150 by etching and removing the first sacrificial layer (N1) and the first buffer layer 140. The lower surface of the channel layer 150 from which the first sacrificial layer (N1) and the first buffer layer 140 have been removed is a nitrogen-polar surface, and is the lower surface of the channel layer 150 exposed to the air. It is very important to bond the surface to the final support substrate 110 to ensure that the surface is in a particle zero state with completely removed residues.

Meanwhile, in some cases, it is desirable to introduce a regular or irregular patterning process to the channel layer 150 in order to improve the bonding strength with the final support substrate 110 in the subsequent process. ) It is also desirable to introduce a CMP process to improve the contact area.

The eighth step (S108) is a step of forming the first bonding layer (B1) on the channel layer 150, and in some cases, the same reinforcement layer as in the ninth step (S109) described later on the channel layer 150 ( After forming 120), the first bonding layer (B1) can be formed on the reinforcement layer 120.

The ninth step (S109) is a step of forming the second bonding layer (B2) on the support substrate 110. In some cases, after forming the reinforcement layer 120 on the support substrate 110, the reinforcement layer 120 ) A second bonding layer (B2) can be formed on top.

Here, the reinforcement layer 120 includes a bond reinforcement layer 121 and a condensation stress layer 122 in more detail.

The bonding reinforcement layer 121 is a layer introduced to strengthen the bonding force when the channel layer 150 is bonded to the final support substrate 110 through the bonding layer 130, and constitutes the bonding strengthening layer 121. It is desirable to preferentially select materials such as silicon oxide (SiO ₂ ) and silicon nitride (SiN _x ).

The condensation stress layer 122 is a layer that causes condensation stress, and is made of a dielectric material with a thermal expansion coefficient greater than that of the final support substrate 110, for example, aluminum nitride (AlN, 4.6 ppm), aluminum nitride oxide (AlNO , 4.6-6.8ppm), aluminum oxide (Al ₂ O ₃ , 6.8ppm), silicon carbide (SiC, 4.8ppm), silicon carbon nitride (SiCN, 3.8-4.8ppm), gallium nitride (GaN, 5.6ppm), nitride It is composed of materials that relieve tensile stress, that is, cause condensation stress, such as gallium oxide (GaNO, 5.6-6.8ppm), which plays a role in improving product quality through stress control.

Meanwhile, as shown in Figure 14, in the present invention, the bonding reinforcement layer 121 or the condensation stress layer 122 may be omitted in some cases, and in some cases, the entire reinforcement layer 120 may be omitted to form a support substrate ( 110) and the bonding layer 130 may be in direct contact (or, in the eighth step (S108), the channel layer 150 and the bonding layer 130 may be in direct contact). In this case, the bonding layer 130 may be formed of a material with a higher thermal expansion coefficient than the support substrate 110, such as silicon (Si), to function as a bonding layer and cause condensation stress.

In addition, the first bonding layer (B1) and the second bonding layer (B2) are each made of a dielectric material that does not change in physical properties and has excellent thermal conductivity in a MOCVD chamber (temperature of 1000°C or higher and reducing atmosphere) in which group 3 nitride semiconductors are grown. For example, silicon oxide (SiO ₂ , 0.8ppm) _, silicon nitride (SiN It may contain aluminum (Al ₂ O ₃ , 6.8ppm) and, furthermore, FOX (Flowable Oxides) such as SOG (Spin On Glass, Liquid SiO ₂ ) and HSQ (Hydrogen Silsesquioxane) to improve surface roughness.

The tenth step (S110) is a step of forming the bonding layer 130 by bonding the first bonding layer (B1) and the second bonding layer (B2) to each other in order to separate the temporary substrate (T). That is, in the tenth step (S110), the channel layer 150 on which the first bonding layer B1 is formed (deposited) and the temporary substrate T are turned over and placed on the support substrate 110 on which the second bonding layer B2 is formed. This is the step of bonding by pressing at a temperature below 300℃.

Conventionally, epitaxial wafer bending occurs due to thermo-mechanical induced stress caused by differences in lattice constant (LC) and coefficient of thermal expansion (CTE) between the initial growth substrate (G) and group 3 nitride semiconductor. However, in the case of an epitaxial wafer bonded to the temporary substrate (T) of the present invention, the stress is almost relieved and the wafer bow can be minimized to almost zero. At this time, setting the bonding process temperature near room temperature and performing the process can minimize stress and further minimize wafer warpage.

The 11th step (S111) is a step of separating the temporary substrate (T) from the second sacrificial layer (N2) using a chemical lift off (CLO) technique. In more detail, the back of the temporary substrate (T) is mechanically polished (grinding & polishing) to remove a significant thickness, and then TMAH (Tetramethylammonium hydroxide) or HNA (Hydrofluoric hydroxide) is used to completely remove the remaining thin silicon (Si) in a continuous process. + Nitric + Acetic Acids) to remove the silicon (Si) material from the temporary substrate (T) by wet etching.

The twelfth step (S112) is a step of etching and removing the second sacrificial layer (N2), the adhesive layer (A), and the epitaxial protective layer (P). Here, the second sacrificial layer (N2), the adhesive layer (A), and the epitaxial protective layer (P) may be formed through dry etching and wet etching. Afterwards, the residue on the surface of the contaminated channel layer 150 can be removed, and if necessary, it is desirable to perform an annealing process at a high temperature of 400°C or higher to strengthen the bonding strength of the permanent bonding layer 130. .

The thirteenth step (S113) is a step of regrowing a high-quality regrowth layer 160 on the channel layer 150. At this time, the re-grown layer 160 may be an aluminum gallium nitride (AlGaN) barrier layer, but is not limited to this and each layer suitable for a typical HEMT structure may be re-grown, for example, gallium nitride (GaN) or nitride. A channel layer of indium aluminum nitride (InAlN), a barrier layer of aluminum gallium nitride (AlGaN), aluminum scandium nitride (AlScN) or indium aluminum nitride (InAlN), p-type gallium nitride (pGaN), p-type aluminum gallium nitride (pAlGaN), or It may have a structure including an injection layer of p-type aluminum gallium indium nitride (pAlGaInN), a passivation layer of silicon nitride (SiN _x ), or aluminum nitride (AlN).

The Group 3 nitride semiconductor template manufactured by the method (S100) for manufacturing a Group 3 nitride semiconductor template using the chemical lift-off technique according to the first embodiment of the present invention described above includes a support substrate 110 and a reinforcement layer 120. ), the bonding layer 130, the reinforcement layer 120, the channel layer 150, and the regrowth layer 160 may be stacked in that order.

From now on, with reference to the attached drawings, a method (S200) for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to a second embodiment of the present invention will be described in detail.

Figure 3 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to a second embodiment of the present invention, and Figure 4 is a group using a chemical lift-off technique according to a second embodiment of the present invention. This shows the process of manufacturing a group III nitride semiconductor template.

As shown in Figures 3 and 4, the method (S200) for manufacturing a group 3 nitride semiconductor template using a chemical lift-off technique according to the second embodiment of the present invention includes a first step (S201) and a second step. Step (S202), third step (S203), fourth step (S204), fifth step (S205), sixth step (S206), seventh step (S207), and eighth step ( It includes the ninth step (S209), the tenth step (S210), the eleventh step (S211), the twelfth step (S212), and the thirteenth step (S213).

The first step (S201) is a step of preparing the growth substrate (G), the temporary substrate (T), and the support substrate 210.

The support substrate 210 is formed into a first buffer layer 240 and a channel layer 250 after going through each step of the method (S200) of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the second embodiment of the present invention. ) and a substrate that supports the regrowth layer 260.

This support substrate 210 is preferably provided as a silicon (Si) support substrate 210 with high heat dissipation ability, and the silicon (Si) support substrate 210 may be single crystalline, polycrystalline, or amorphous, ( It may be formed of silicon (Si) with a 111) crystal plane, a (110) crystal plane, or a (100) crystal plane.

Furthermore, in addition to the above-described silicon (Si), it may include at least one material selected from materials including silicon carbide (SiC), aluminum nitride (AlN), and sapphire. In particular, silicon carbide (SiC) and aluminum nitride (AlN) may be single crystalline or polycrystalline.

Hereinafter, the first step (S201) to the sixth step (S206) are the same as those of the method for manufacturing the group III nitride semiconductor template (S100) using the chemical lift-off technique according to the first embodiment of the present invention described above, so there is no overlap. The explanation is omitted.

The seventh step (S207) is a step of exposing the first buffer layer 240 by etching and removing the first sacrificial layer (N1). The lower surface of the first buffer layer 240 from which the first sacrificial layer (N1) has been removed is a nitrogen-polar surface, and the lower surface of the first buffer layer 240 exposed to the air removes the residue. It is very important to have a surface in a completely particle-free state for bonding to the final support substrate 210.

Meanwhile, in some cases, it is desirable to introduce a regular or irregular patterning process to the first buffer layer 240 to improve the adhesion with the final support substrate 210 in the subsequent process, and in some cases, the final support substrate (210) in the subsequent process. 210) It is also desirable to introduce a CMP process to improve the contact area.

The eighth step (S208) is a step of forming a first bonding layer (B1) on the first buffer layer 240, and in some cases, the same strengthening as in the ninth step (S209) described later on the first buffer layer 240. After forming the layer 220, the first bonding layer (B1) can be formed on the reinforcement layer 220.

The ninth step (S209) is a step of forming the second bonding layer (B2) on the support substrate 210. In some cases, after forming the reinforcement layer 220 on the support substrate 210, the reinforcement layer 220 ) A second bonding layer (B2) can be formed on top. Here, the reinforcement layer 220 includes a bond reinforcement layer 221 and a condensation stress layer 222 in more detail.

Meanwhile, as shown in Figure 14, in the present invention, the bonding reinforcement layer 221 or the condensation stress layer 222 may be omitted in some cases, and in some cases, the entire reinforcement layer 220 may be omitted to form a support substrate ( 210) and the bonding layer 230 may be in direct contact (or, in the eighth step (S208), the first buffer layer 240 and the bonding layer 230 may be in direct contact). In this case, the bonding layer 230 may be formed of a material with a thermal expansion coefficient greater than that of the silicon (Si) support substrate 210, which may have a bonding function and cause condensation stress.

The tenth step (S210) is a step of forming the bonding layer 230 by bonding the first bonding layer (B1) and the second bonding layer (B2) to each other in order to separate the temporary substrate (T). That is, in the tenth step (S210), the first buffer layer 240 on which the first bonding layer B1 is formed (deposited) and the temporary substrate T are turned over and the support substrate 210 on which the second bonding layer B2 is formed. This is the step of bonding by pressurizing at a temperature below 300℃.

Conventionally, epitaxial wafer bending occurs due to thermo-mechanical induced stress caused by differences in lattice constant (LC) and coefficient of thermal expansion (CTE) between the initial growth substrate (G) and group 3 nitride semiconductor. However, in the case of an epitaxial wafer bonded to the temporary substrate (T) of the present invention, the stress is almost relieved and the wafer bow can be minimized to almost zero. At this time, setting the bonding process temperature near room temperature and performing the process can minimize stress and further minimize wafer warpage.

The 11th step (S211) to the 13th step (S213) are the same as those of the method (S100) for manufacturing a group III nitride semiconductor template using the chemical lift-off technique according to the first embodiment of the present invention described above, so duplicate description is omitted.

The Group 3 nitride semiconductor template manufactured by the manufacturing method (S200) of the Group 3 nitride semiconductor template using the chemical lift-off technique according to the second embodiment of the present invention described above includes a support substrate 210 and a reinforcement layer 220. ), the bonding layer 230, the reinforcement layer 220, the first buffer layer 240, the channel layer 250, and the regrowth layer 260 may be stacked in that order.

From now on, with reference to the attached drawings, a method (S300) for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to a third embodiment of the present invention will be described in detail.

Figure 5 is a flowchart of a method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to a third embodiment of the present invention, and Figure 6 is a group using a chemical lift-off technique according to a third embodiment of the present invention. It shows a process of manufacturing a Group III nitride semiconductor template, and Figure 7 shows another process of manufacturing a Group III nitride semiconductor template using a chemical lift-off technique according to the third embodiment of the present invention.

As shown in FIGS. 5 to 7, the method (S300) for manufacturing a group 3 nitride semiconductor template using the chemical lift-off technique according to the third embodiment of the present invention includes a first step (S301) and a second step. Step (S302), third step (S303), fourth step (S304), fifth step (S305), sixth step (S306), seventh step (S307), and eighth step ( It includes the 9th step (S309), the 10th step (S310), the 11th step (S311), the 12th step (S312), and the 13th step (S313).

The support substrate 310 is formed into a second buffer layer 350 and a channel layer 360 after going through each step of the method (S300) of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the third embodiment of the present invention. ) and a substrate that supports the regrowth layer 370.

This support substrate 310 is preferably provided as a silicon (Si) support substrate 310 with high heat dissipation ability, and the silicon (Si) support substrate 310 may be single crystalline, polycrystalline, or amorphous, ( It may be formed of silicon (Si) with a 111) crystal plane, a (110) crystal plane, or a (100) crystal plane.

Furthermore, in addition to the above-described silicon (Si), it may include at least one material selected from materials including silicon carbide (SiC), aluminum nitride (AlN), and sapphire. In particular, silicon carbide (SiC) and aluminum nitride (AlN) may be single crystalline or polycrystalline.

Hereinafter, the first step (S301) to the sixth step (S306) are the same as those of the method of manufacturing the group III nitride semiconductor template (S100) using the chemical lift-off technique according to the first embodiment of the present invention described above, so there is no overlap. The explanation is omitted.

The seventh step (S307) is a step of exposing the channel layer 360 by etching and removing the first sacrificial layer (N1) and the first buffer layer 340. The lower surface of the channel layer 360 from which the first sacrificial layer (N1) and the first buffer layer 340 are removed is a nitrogen-polar surface, and is the lower surface of the channel layer 360 exposed to the air. It is very important to bond the surface to the final support substrate 210 to ensure that the surface is in a particle zero state with completely removed residues.

Meanwhile, in some cases, it is desirable to introduce a regular or irregular patterning process to the channel layer 360 in order to improve the bonding strength with the final support substrate 210 in the subsequent process. ) It is also desirable to introduce a CMP process to improve the contact area.

The eighth step (S308) is to form a new second buffer layer 350 on the surface of the channel layer 360 having nitrogen polarity, and to form a first bonding layer (B1) on the second buffer layer 350. It's a step. Here, the newly formed second buffer layer 350 is made of aluminum-containing nitride or oxide (AlN, AlNO, Al ₂ ), which has high resistance to leakage current without separate doping of iron (Fe) or carbon (C). It may be composed of a material such as O ₃ ), and in some cases, the same reinforcement layer 320 as in the ninth step (S309) described later is formed on the second buffer layer 350, and then formed on the reinforcement layer 320. A first bonding layer (B1) can be formed.

Meanwhile, when forming (depositing) the second buffer layer 350 based on aluminum nitride (AlN) material directly on the channel layer 360 based on gallium nitride (GaN) material, the gap between the channel layer 360 and the second buffer layer 350 Cracks may occur due to differences in lattice constant (LC) and coefficient of thermal expansion (CTE). Therefore, as shown in FIG. 7, the eighth step (S308) is to form a crack suppression layer (C) that provides condensation stress to suppress crack occurrence on the channel layer 360, and then form a crack suppression layer (C) The second buffer layer 350 may be formed (deposited) on the.

The ninth step (S309) is a step of forming the second bonding layer (B2) on the support substrate 310. In some cases, after forming the reinforcement layer 320 on the support substrate 310, the reinforcement layer 320 ) A second bonding layer (B2) can be formed on top. Here, the reinforcement layer 320 includes a bond reinforcement layer 321 and a condensation stress layer 322 in more detail.

Meanwhile, as shown in Figure 14, in the present invention, the bonding reinforcement layer 321 or the condensation stress layer 322 may be omitted in some cases, and in some cases, the entire reinforcement layer 320 may be omitted to form a support substrate ( 310) and the bonding layer 330 may be in direct contact (or, in the eighth step (S308), the second buffer layer 350 and the bonding layer 330 may be in direct contact). In this case, the bonding layer 330 may be formed of a material with a higher thermal expansion coefficient than the support substrate 310, such as silicon (Si), and may have a bonding function as well as a structure that causes condensation stress.

The tenth step (S310) is a step of forming the bonding layer 330 by bonding the first bonding layer (B1) and the second bonding layer (B2) to each other in order to separate the temporary substrate (T). That is, in the tenth step (S310), the second buffer layer 350 on which the first bonding layer (B1) is formed (deposited) and the temporary substrate (T) are turned over and the support substrate 310 on which the second bonding layer (B2) is formed. This is the step of bonding by pressing at a temperature of less than 300℃.

Conventionally, epitaxial wafer bending occurs due to thermo-mechanical induced stress caused by differences in lattice constant (LC) and coefficient of thermal expansion (CTE) between the initial growth substrate (G) and group 3 nitride semiconductor. However, in the case of an epitaxial wafer bonded to the temporary substrate (T) of the present invention, the stress is almost relieved and the wafer bow can be minimized to almost zero. At this time, setting the bonding process temperature near room temperature and performing the process can minimize stress and further minimize wafer warpage.

The 11th step (S311) to the 13th step (S313) are the same as those of the method (S100) for manufacturing a group III nitride semiconductor template using the chemical lift-off technique according to the first embodiment of the present invention described above, so duplicate description is omitted.

The Group 3 nitride semiconductor template manufactured by the method (S300) for manufacturing a Group 3 nitride semiconductor template using the chemical lift-off technique according to the third embodiment of the present invention described above includes a support substrate 310 and a reinforcement layer 320. ), the bonding layer 330, the reinforcement layer 320, the second buffer layer 350, the channel layer 360, and the regrowth layer 370 may be stacked in that order.

From now on, with reference to the attached drawings, a method (S400) for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to a fourth embodiment of the present invention will be described in detail.

Figure 8 is a flowchart of a method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to a fourth embodiment of the present invention, and Figure 9 is a flow chart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to a fourth embodiment of the present invention. This shows the process of manufacturing a group III nitride semiconductor template.

As shown in Figures 8 and 9, the method (S400) for manufacturing a group 3 nitride semiconductor template using a chemical lift-off technique according to the fourth embodiment of the present invention includes a first step (S401) and a second step. Step (S402), third step (S403), fourth step (S404), fifth step (S405), sixth step (S406), seventh step (S407), and eighth step ( It includes the 9th step (S409), the 10th step (S410), the 11th step (S411), the 12th step (S412), and the 13th step (S413).

The first step (S401) is a step of preparing the growth substrate (G), the temporary substrate (T), and the support substrate 410.

The support substrate 410 is formed into a first buffer layer 440, a second buffer layer ( 450), a substrate that supports the channel layer 460 and the regrowth layer 470.

This support substrate 410 is preferably provided as a silicon (Si) support substrate 410 with high heat dissipation ability, and the silicon (Si) support substrate 410 may be single crystalline, polycrystalline, or amorphous, ( It may be formed of silicon (Si) with a 111) crystal plane, a (110) crystal plane, or a (100) crystal plane.

Furthermore, in addition to the above-described silicon (Si), it may include at least one material selected from materials including silicon carbide (SiC), aluminum nitride (AlN), and sapphire. In particular, silicon carbide (SiC) and aluminum nitride (AlN) may be single crystalline or polycrystalline.

Hereinafter, the first step (S401) to the sixth step (S406) are the same as those of the method of manufacturing the group III nitride semiconductor template (S100) using the chemical lift-off technique according to the first embodiment of the present invention described above, so there is no overlap. The explanation is omitted.

The seventh step (S407) is a step of exposing the first buffer layer 440 by etching and removing the first sacrificial layer (N1). The lower surface of the first buffer layer 440 from which the first sacrificial layer (N1) has been removed is a nitrogen-polar surface, and the lower surface of the first buffer layer 440 exposed to the air removes the residue. It is important to have a surface with zero particles completely removed.

Meanwhile, in some cases, it is desirable to introduce a regular or irregular patterning process to the first buffer layer 440 to improve adhesion in the subsequent process, and in some cases, it is also desirable to introduce a CMP process to improve the contact area in the subsequent process. desirable.

In the eighth step (S408), a new second buffer layer 450 is deposited on the surface of the first buffer layer 440 having nitrogen polarity, and a first bonding layer (B1) is formed on the second buffer layer 450. This is the step to do it. Here, the newly formed second buffer layer 450 is made of aluminum-containing nitride or oxide (AlN, AlNO, Al ₂ ), which has high resistance to leakage current without separate doping of iron (Fe) or carbon (C). It may be composed of a material such as O ₃ ), and in some cases, the same reinforcement layer 420 as in the ninth step (S409) described later is formed on the second buffer layer 450, and then formed on the reinforcement layer 420. A first bonding layer (B1) can be formed.

The ninth step (S409) is a step of forming the second bonding layer (B2) on the support substrate 410. In some cases, after forming the reinforcement layer 420 on the support substrate 410, the reinforcement layer 420 ) A second bonding layer (B2) can be formed on top. Here, the reinforcement layer 420 includes a bond reinforcement layer 421 and a condensation stress layer 422 in more detail.

Meanwhile, as shown in Figure 14, in the present invention, the bonding reinforcement layer 421 or the condensation stress layer 422 may be omitted in some cases, and in some cases, the entire reinforcement layer 420 may be omitted to form a support substrate ( 410) and the bonding layer 430 may be in direct contact (or, in the eighth step (S408), the second buffer layer 450 and the bonding layer 430 may be in direct contact). In this case, the bonding layer 430 may be formed of a material with a greater thermal expansion coefficient than the support substrate 410, such as silicon (Si), to function as a bonding layer and cause condensation stress.

The tenth step (S410) is a step of forming the bonding layer 430 by bonding the first bonding layer (B1) and the second bonding layer (B2) to each other in order to separate the temporary substrate (T). That is, the tenth step (S410) is to flip the second buffer layer 450 on which the first bonding layer (B1) is formed (deposited) and the temporary substrate (T) over the support substrate 410 on which the second bonding layer (B2) is formed. This is the step of bonding by pressing at a temperature of less than 300℃.

Conventionally, epitaxial wafer bending occurs due to thermo-mechanical induced stress caused by differences in lattice constant (LC) and coefficient of thermal expansion (CTE) between the initial growth substrate (G) and group 3 nitride semiconductor. However, in the case of an epitaxial wafer bonded to the temporary substrate (T) of the present invention, the stress is almost relieved and the wafer bow can be minimized to almost zero. At this time, setting the bonding process temperature near room temperature and performing the process can minimize stress and further minimize wafer warpage.

The 11th steps (S411) to the 13th steps (S413) are the same as those of the method (S100) for manufacturing a group III nitride semiconductor template using the chemical lift-off technique according to the first embodiment of the present invention described above, so duplicate description is omitted.

The group 3 nitride semiconductor template manufactured by the manufacturing method (S400) of the group 3 nitride semiconductor template using the chemical lift-off technique according to the fourth embodiment of the present invention described above includes a support substrate 410 and a reinforcement layer 420. ), the bonding layer 430, the reinforcement layer 420, the second buffer layer 450, the first buffer layer 440, the channel layer 460, and the regrowth layer 470 may be stacked in that order.

From now on, with reference to the attached drawings, a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the fifth embodiment of the present invention will be described in detail.

Figure 10 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the fifth embodiment of the present invention, and Figure 11 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the fifth embodiment of the present invention. This shows the process of manufacturing a group III nitride semiconductor template.

As shown in Figures 10 and 11, the method (S500) for manufacturing a group 3 nitride semiconductor template using the chemical lift-off technique according to the fifth embodiment of the present invention includes a first step (S501) and a second step. Step (S502), third step (S503), fourth step (S504), fifth step (S505), sixth step (S506), seventh step (S507), and eighth step ( It includes the ninth step (S509), the tenth step (S510), the eleventh step (S511), the twelfth step (S512), and the thirteenth step (S513).

The first step (S501) is a step of preparing a growth substrate (G), a temporary substrate (T), and a support substrate (510).

The support substrate 510 is formed into a first buffer layer 540 and a first buffer layer ( It is a substrate that supports the channel layer 550 and the re-growth layer 560 re-grown on 540).

Furthermore, in addition to the above-described silicon (Si), it may include at least one material selected from materials including silicon carbide (SiC), aluminum nitride (AlN), and sapphire. In particular, silicon carbide (SiC) and aluminum nitride (AlN) may be single crystalline or polycrystalline.

The second step (S502) is a step of forming a first sacrificial layer (N1) on the growth substrate (G) and then growing a high-quality group III nitride semiconductor layer in a single layer or multiple layers on the first sacrificial layer (N1). , Specifically, this is a step of growing only the high-quality first buffer layer 540 as a single layer or multilayer on the first sacrificial layer (N1).

The third step (S503) is a step of forming the epitaxial protective layer (P) on the first buffer layer 540 and then forming the first adhesive layer (A1) on the epitaxial protective layer (P). The following contents of the third step (S503) and the contents of the fourth step (S504) to the sixth step (S506) are related to the Group 3 nitride semiconductor using the chemical lift-off technique according to the first embodiment of the present invention described above. Since it is the same as that of the template manufacturing method (S100), redundant description will be omitted.

The seventh step (S507) is a step of exposing the first buffer layer 540 by etching and removing the first sacrificial layer (N1). The lower surface of the first buffer layer 540 from which the first sacrificial layer (N1) has been removed is a nitrogen-polar surface, and the lower surface of the first buffer layer 540 exposed to the air removes the residue. It is very important to have a surface in a completely particle-free state for bonding to the final support substrate 510.

Meanwhile, in some cases, it is desirable to introduce a regular or irregular patterning process to the first buffer layer 540 in order to improve the adhesion with the final support substrate 510 in the subsequent process, and in some cases, the final support substrate (510) in the subsequent process. It is also desirable to introduce a CMP process to improve the contact area with 510).

The eighth step (S508) is a step of forming a first bonding layer (B1) on the first buffer layer 540, and in some cases, the same strengthening as in the ninth step (S509) described later on the first buffer layer 540. After forming the layer 520, the first bonding layer (B1) can be formed on the reinforcement layer 520.

The ninth step (S509) is a step of forming the second bonding layer (B2) on the support substrate 510. In some cases, after forming the reinforcement layer 520 on the support substrate 510, the reinforcement layer 520 ) A second bonding layer (B2) can be formed on top. Here, the reinforcement layer 520 includes a bond reinforcement layer 521 and a condensation stress layer 522 in more detail.

Meanwhile, as shown in Figure 14, in the present invention, the bonding reinforcement layer 521 or the condensation stress layer 522 may be omitted in some cases, and in some cases, the entire reinforcement layer 520 may be omitted to form a support substrate ( 510) and the bonding layer 530 may be in direct contact (or, in the eighth step (S508), the first buffer layer 540 and the bonding layer 530 may be in direct contact). In this case, the bonding layer 530 may be formed of a material with a higher thermal expansion coefficient than the support substrate 510, such as silicon (Si), to function as a bonding layer and cause condensation stress.

The tenth step (S510) is a step of forming a bonding layer 530 by bonding the first bonding layer (B1) and the second bonding layer (B2) to each other in order to separate the temporary substrate (T). That is, in the tenth step (S510), the first buffer layer 540 on which the first bonding layer B1 is formed (deposited) and the temporary substrate T are turned over and the support substrate 510 on which the second bonding layer B2 is formed. This is the step of bonding by pressurizing at a temperature below 300℃.

Conventionally, epitaxial wafer bending occurs due to thermo-mechanical induced stress caused by differences in lattice constant (LC) and coefficient of thermal expansion (CTE) between the initial growth substrate (G) and group 3 nitride semiconductor. However, in the case of an epitaxial wafer bonded to the temporary substrate (T) of the present invention, the stress is almost relieved and the wafer bow can be minimized to almost zero. At this time, setting the bonding process temperature near room temperature and performing the process can minimize stress and further minimize wafer warpage.

The 11th step (S511) to the 12th step (S512) are the same as those of the method (S100) for manufacturing a group III nitride semiconductor template using the chemical lift-off technique according to the first embodiment of the present invention described above, so duplicate description is omitted.

The thirteenth step (S513) is a step of re-growing a high-quality channel layer 550 on the first buffer layer 540 and re-growing a high-quality re-grown layer 570 on the re-grown channel layer 550. At this time, the re-grown layer 570 may be an aluminum gallium nitride (AlGaN) barrier layer, but is not limited to this and each layer suitable for a typical HEMT structure may be re-grown, for example, gallium nitride (GaN) or nitride. A channel layer of indium aluminum nitride (InAlN), a barrier layer of aluminum gallium nitride (AlGaN), aluminum scandium nitride (AlScN) or indium aluminum nitride (InAlN), p-type gallium nitride (pGaN), p-type aluminum gallium nitride (pAlGaN), or It may have a structure including an injection layer of p-type aluminum gallium indium nitride (pAlGaInN), a passivation layer of silicon nitride (SiN _x ), or aluminum nitride (AlN).

The Group 3 nitride semiconductor template manufactured by the method (S500) for manufacturing a Group 3 nitride semiconductor template using the chemical lift-off technique according to the fifth embodiment of the present invention described above includes a support substrate 510 and a reinforcement layer 520. ), the bonding layer 530, the reinforcement layer 520, the first buffer layer 540, the channel layer 550, and the regrowth layer 560 may be stacked in that order.

From now on, with reference to the attached drawings, a method (S600) for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the sixth embodiment of the present invention will be described in detail.

Figure 12 is a flowchart of a method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the sixth embodiment of the present invention, and Figure 13 is a flowchart of a method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the sixth embodiment of the present invention. This shows the process of manufacturing a group III nitride semiconductor template.

As shown in Figures 12 and 13, the method (S600) for manufacturing a group 3 nitride semiconductor template using the chemical lift-off technique according to the sixth embodiment of the present invention includes a first step (S601) and a second step. Step (S602), third step (S603), fourth step (S604), fifth step (S605), sixth step (S606), seventh step (S607), and eighth step ( It includes the 9th step (S609), the 10th step (S610), the 11th step (S611), the 12th step (S612), and the 13th step (S613).

The first step (S601) is a step of preparing a growth substrate (G), a temporary substrate (T), and a support substrate (610). The following content is the same as that of the method (S500) for manufacturing a group 3 nitride semiconductor template using the chemical lift-off technique according to the fifth embodiment of the present invention described above, and therefore redundant description is omitted.

The second step (S602) is a step of forming a first sacrificial layer (N1) on the growth substrate (G) and then growing a high-quality Group III nitride semiconductor layer in a single layer or multiple layers on the first sacrificial layer (N1). , Specifically, this is the step of forming (depositing) only the high-quality second buffer layer 650 as a single layer or multilayer on the first sacrificial layer (N1). At this time, the formed (film-deposited) second buffer layer 650 is composed of a single-layer or multi-layer Group 3 nitride semiconductor, and the second buffer layer 650 of this embodiment is made of a separate material such as iron (Fe) or carbon (C). It can be made of a nitride or oxide (AlN, AlNO, Al ₂ O ₃ ) material containing aluminum, which has high resistance to leakage current even without doping.

Since the contents of the third step (S603) to the twelfth step (S612) are the same as those of the method (S500) for manufacturing a group III nitride semiconductor template using the chemical lift-off technique according to the fifth embodiment of the present invention described above, Redundant explanations are omitted.

The thirteenth step (S613) is a step of regrowing a high-quality group III nitride semiconductor layer on the second buffer layer 650.

Specifically, in the 13th step (S613), 1) the channel layer 660 is immediately re-grown on the second buffer layer 650, or 2) the second buffer layer 660 composed of aluminum-containing nitride or oxide (AlN, AlNO, Al ₂ O ₃ ) is formed. After re-growing the new first buffer layer 640 on the buffer layer 650, the channel layer 660 can be re-grown, and then a high-quality re-grown layer 670 can be re-grown on the channel layer 660. At this time, the first buffer layer 640 is composed of a single-layer or multi-layer Group III nitride semiconductor, and the first buffer layer 640 of this embodiment is composed of gallium nitride (GaN) material with high resistance to leakage current. It can be doped with iron (Fe), carbon (C), etc. to increase resistance as needed.

The group 3 nitride semiconductor template manufactured by the method (S600) for manufacturing a group 3 nitride semiconductor template using the chemical lift-off technique according to the sixth embodiment of the present invention described above includes a support substrate 610 and a reinforcement layer 620. ), the bonding layer 630, the reinforcement layer 620, the second buffer layer 650, the channel layer 660, and the regrowth layer 670 may be stacked in that order, or the support substrate 610, A structure in which the reinforcement layer 620, the bonding layer 630, the reinforcement layer 620, the second buffer layer 650, the first buffer layer 640, the channel layer 660, and the regrowth layer 670 are stacked in order. You can have it.

In the above, just because all the components constituting the embodiment of the present invention have been described as being combined or operated in combination, the present invention is not necessarily limited to this embodiment. That is, as long as it is within the scope of the purpose of the present invention, all of the components may be operated by selectively combining one or more of them.

In addition, terms such as “include,” “comprise,” or “have” described above mean that the corresponding component may be present, unless specifically stated to the contrary, and thus do not exclude other components. Rather, it should be interpreted as being able to include other components. All terms, including technical or scientific terms, unless otherwise defined, have the same meaning as generally understood by a person of ordinary skill in the technical field to which the present invention pertains. Commonly used terms, such as terms defined in a dictionary, should be interpreted as consistent with the contextual meaning of the related technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in the present invention.

The above description is merely an illustrative explanation of the technical idea of the present invention, and those skilled in the art will be able to make various modifications and variations without departing from the essential characteristics of the present invention.

Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are for illustrative purposes, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of the present invention.

S100: Method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the first embodiment of the present invention
S101: Step 1
S102: Second stage
S103: Step 3
S104: Step 4
S105: Step 5
S106: Step 6
S107: Step 7
S108: Step 8
S109: Step 9
S110: Step 10
S111: Step 11
S112: Step 12
S113: Step 13
110: support substrate
120: Reinforced layer
121: Bonding reinforcement layer
122: Condensation stress layer
130: bonding layer
140: first buffer layer
150: channel layer
160: Regrowth layer
G: growth substrate
T: Temporary board
N1: first sacrificial layer
N2: Second sacrificial layer
P: Epitaxial protective layer
A1: first adhesive layer
A2: Second adhesive layer
A: Adhesive layer
B1: first bonding layer
B2: second bonding layer
S200: Method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the second embodiment of the present invention
S201: Step 1
S202: Second stage
S203: Step 3
S204: Step 4
S205: Step 5
S206: Step 6
S207: Step 7
S208: Step 8
S209: Step 9
S210: Step 10
S211: Step 11
S212: Step 12
S213: Step 13
210: support substrate
220: Reinforced layer
221: Bonding reinforcement layer
222: Condensation stress layer
230: bonding layer
240: first buffer layer
250: channel layer
260: Regrowth layer
S300: Method for manufacturing a Group 3 nitride semiconductor template using a chemical lift-off technique according to the third embodiment of the present invention
S301: Step 1
S302: Second stage
S303: Third stage
S304: Step 4
S305: Step 5
S306: Step 6
S307: Step 7
S308: Step 8
S309: Step 9
S310: Step 10
S311: Step 11
S312: Step 12
S313: Step 13
310: support substrate
320: Reinforced layer
321: Bonding reinforcement layer
322: Condensation stress layer
330: bonding layer
340: first buffer layer
350: second buffer layer
360: Channel layer
370: Regrowth layer
C: Crack suppression layer
S400: Method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the fourth embodiment of the present invention
S401: Step 1
S402: Second stage
S403: Step 3
S404: Step 4
S405: Step 5
S406: Step 6
S407: Step 7
S408: Step 8
S409: Step 9
S410: Step 10
S411: Step 11
S412: Step 12
S413: Step 13
410: Support substrate
420: Reinforced layer
421: Bonding reinforcement layer
422: Condensation stress layer
430: bonding layer
440: first buffer layer
450: second buffer layer
460: Channel layer
470: Regrowth layer
S500: Method for manufacturing a group 3 nitride semiconductor template using a chemical lift-off technique according to the fifth embodiment of the present invention
S501: Step 1
S502: Second stage
S503: Stage 3
S504: Step 4
S505: Step 5
S506: Step 6
S507: Step 7
S508: Step 8
S509: Step 9
S510: Step 10
S511: Step 11
S512: Step 12
S513: Step 13
510: Support substrate
520: Reinforced layer
521: Bonding reinforcement layer
522: Condensation stress layer
530: bonding layer
540: first buffer layer
550: Channel layer
560: Regrowth layer
S600: Method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique according to the sixth embodiment of the present invention
S601: Step 1
S602: Second stage
S603: Step 3
S604: Step 4
S605: Step 5
S606: Step 6
S607: Step 7
S608: Step 8
S609: Step 9
S610: Step 10
S611: Step 11
S612: Step 12
S613: Step 13
610: Support substrate
620: Reinforced layer
621: Bonding reinforcement layer
622: Condensation stress layer
630: Bonding layer
640: first buffer layer
650: second buffer layer
660: Channel layer
670: Regrowth layer

Claims (20)

A first step of preparing a growth substrate, temporary substrate, and support substrate;
a second step of forming a first sacrificial layer on the growth substrate, growing a first buffer layer on the first sacrificial layer, and then growing a channel layer on the first buffer layer;
A third step of forming an epitaxial protective layer on the channel layer and then forming a first adhesive layer on the epitaxial protective layer;
A fourth step of forming a second sacrificial layer on the temporary substrate and then forming a second adhesive layer on the second sacrificial layer;
A fifth step of forming an adhesive layer by adhering the first adhesive layer and the second adhesive layer to each other;
A sixth step of separating the growth substrate from the first sacrificial layer using a chemical lift off (CLO) technique;
A seventh step of etching and removing the first sacrificial layer, or etching and removing the first sacrificial layer and the first buffer layer;
An eighth step of forming a first bonding layer on the first buffer layer or forming the first bonding layer on the channel layer;
A ninth step of forming a second bonding layer on the support substrate;
A tenth step of forming a bonding layer by bonding the first bonding layer and the second bonding layer to each other;
An 11th step of separating the temporary substrate from the second sacrificial layer using a chemical lift off (CLO) technique; and
A twelfth step of etching and removing the second sacrificial layer, the adhesive layer, and the epitaxial protective layer,
On at least one of the upper and lower surfaces of the bonding layer,
The reinforcement layer is formed to contact,
The reinforcement layer is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, comprising a bonding reinforcement layer that strengthens the bonding force of the bonding layer and a condensation stress layer that causes condensation stress. In claim 1,
The ninth step is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, in which the reinforcement layer is formed on the support substrate and then the second bonding layer is formed on the reinforcement layer. In claim 1,
The seventh step is,
Etching and removing the first sacrificial layer and the first buffer layer,
The eighth step is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, forming the first bonding layer on the channel layer. In claim 3,
The eighth step is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, in which the reinforcement layer is formed on the channel layer and then the first bonding layer is formed on the reinforcement layer. In claim 1,
The seventh step is,
Etching and removing the first sacrificial layer,
The eighth step is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, wherein the first bonding layer is formed on the first buffer layer. In claim 5,
The eighth step is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, comprising forming the reinforcement layer on the first buffer layer and then forming the first bonding layer on the reinforcement layer. In claim 3,
The eighth step is,
A method of manufacturing a group III nitride semiconductor template by depositing a second buffer layer on the channel layer, forming the first bonding layer on the second buffer layer, and using a chemical lift-off technique. In claim 5,
The eighth step is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, comprising depositing a second buffer layer on the first buffer layer and then forming the first bonding layer on the deposited second buffer layer. In claim 7,
The eighth step is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, comprising forming the reinforcement layer on the formed second buffer layer and then forming the first bonding layer on the reinforcement layer. In claim 8,
The eighth step is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, comprising forming the reinforcement layer on the formed second buffer layer and then forming the first bonding layer on the reinforcement layer. In claim 1,
The growth substrate is,
It is a silicon (Si) growth substrate,
The support substrate is,
Method for manufacturing a group 3 nitride semiconductor template using a chemical lift-off technique, which is a silicon (Si) support substrate. In claim 1,
The first buffer layer is,
Method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique, including a gallium nitride (GaN) material system. In claim 7,
The second buffer layer is,
A method of manufacturing a Group III nitride semiconductor template containing a nitride or oxide containing aluminum using a chemical lift-off technique. In claim 8,
The second buffer layer is,
A method of manufacturing a Group III nitride semiconductor template containing a nitride or oxide containing aluminum using a chemical lift-off technique. A first step of preparing a growth substrate, temporary substrate, and support substrate;
a second step of forming a first sacrificial layer on the growth substrate and growing a buffer layer on the first sacrificial layer;
A third step of forming an epitaxial protective layer on the buffer layer and then forming a first adhesive layer on the epitaxial protective layer;
A fourth step of forming a second sacrificial layer on the temporary substrate and then forming a second adhesive layer on the second sacrificial layer;
A fifth step of forming an adhesive layer by adhering the first adhesive layer and the second adhesive layer to each other;
A sixth step of separating the growth substrate from the first sacrificial layer using a chemical lift off (CLO) technique;
A seventh step of etching and removing the first sacrificial layer;
An eighth step of forming a first bonding layer on the buffer layer;
A ninth step of forming a second bonding layer on the support substrate;
A tenth step of forming a bonding layer by bonding the first bonding layer and the second bonding layer to each other;
An 11th step of separating the temporary substrate from the second sacrificial layer using a chemical lift off (CLO) technique; and
A twelfth step of etching and removing the second sacrificial layer, the adhesive layer, and the epitaxial protective layer,
On at least one of the upper and lower surfaces of the bonding layer,
The reinforcement layer is formed to contact,
The reinforcement layer is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, comprising a bonding reinforcement layer that strengthens the bonding force of the bonding layer and a condensation stress layer that causes condensation stress. In claim 15,
The ninth step is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, in which the reinforcement layer is formed on the support substrate and then the second bonding layer is formed on the reinforcement layer. In claim 15,
The eighth step is,
A method of manufacturing a group III nitride semiconductor template using a chemical lift-off technique, comprising forming the reinforcement layer on the buffer layer and then forming the first bonding layer on the reinforcement layer. In claim 15,
The buffer layer is,
Method for manufacturing a group III nitride semiconductor template using a chemical lift-off technique, including a gallium nitride (GaN) material system. In claim 15,
The buffer layer is,
A method of manufacturing a Group III nitride semiconductor template containing a nitride or oxide containing aluminum using a chemical lift-off technique. A Group 3 nitride semiconductor template manufactured by the method for manufacturing a Group 3 nitride semiconductor template using a chemical lift-off technique according to any one of claims 1 to 19.