KR102604412B1 - Real Time Compensation Circuit And Electroluminescent Display Device Including The Same - Google Patents

Abstract

The present invention relates to a real-time compensation circuit and an electroluminescence display device including the same. This real-time compensation circuit is a plurality of pixel blocks set in pixel block units including M x N (M, N are each positive integers of 2 or more) pixels. a first memory storing star compensation values; a second memory that receives compensation values for each of the plurality of pixel blocks from the first memory; a compensation unit that modulates the pixel data of an input image by adding a compensation value for each pixel block to the pixel data; and a data driver that converts the compensated pixel data received from the compensation unit into a data voltage. The compensation value for each pixel block is collectively applied to each pixel in the pixel block in at least one color.

Description

Real Time Compensation Circuit And Electroluminescent Display Device Including The Same}

The present invention relates to a real-time compensation circuit and an electroluminescent display device including the same.

Electroluminescent display devices are roughly divided into inorganic light emitting display devices and organic light emitting display devices depending on the material of the light emitting layer. The active matrix type organic light emitting display device includes an organic light emitting diode (hereinafter referred to as “OLED”) that emits light on its own, has a fast response speed, and has high luminous efficiency, brightness, and viewing angle. There is an advantage.

An OLED organic light emitting display device includes an anode electrode and a cathode electrode, and an organic compound layer formed between them. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL). When the power supply voltage is applied to the anode electrode and cathode electrode, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) are moved to the emitting layer (EML) to form excitons, and as a result, the emitting layer (EML) Visible light is generated.

Each pixel of an organic light emitting display device includes a driving element that controls the current flowing through the OLED. The driving element may be implemented as a transistor. Electrical characteristics of the driving element, such as threshold voltage and mobility, must be the same for all pixels, but the electrical characteristics of the driving element are not uniform due to process conditions, driving environment, etc. The driving element experiences more stress as the driving time increases. Additionally, the stress of the driving element varies depending on the data of the input image. The electrical characteristics of the driving element are affected by stress. Accordingly, the electrical characteristics of the driving elements change as driving time elapses.

In order to improve the image quality and lifespan of organic light emitting display devices, compensation circuits to compensate for differences in driving characteristics of pixels are being applied to organic light emitting display devices.

In the trend of high-resolution and high-speed driving of organic light emitting display devices, existing compensation methods cannot sufficiently compensate for differences in pixel driving characteristics. For example, as the resolution increases and the driving frequency increases, the 1 horizontal period for writing data to the pixels of 1 line in the display panel decreases, so the threshold voltage sampling period of the driving element allocated within 1 horizontal period may be reduced. There is no outside. If the time required to sample the threshold voltage of the driving element is insufficient, the threshold voltage sampling value of the driving voltage becomes inaccurate, resulting in differences in driving characteristics between pixels on the screen. Differences in driving characteristics between pixels result in luminance differences even if data of the same gray level is written to all pixels, making them appear as spots on the screen.

The present invention provides a real-time compensation circuit that can sufficiently compensate for differences in driving characteristics between pixels in high-resolution, high-speed driving and reduce the memory capacity of the compensation circuit, and an electroluminescent display device including the same.

The real-time compensation circuit of the present invention includes a first memory storing a plurality of compensation values for each pixel block set in units of pixel blocks including M x N (M and N are each positive integers of 2 or more) pixels; a second memory that receives compensation values for each of the plurality of pixel blocks from the first memory; a compensation unit that modulates the pixel data of an input image by adding a compensation value for each pixel block to the pixel data; and a data driver that converts the compensated pixel data received from the compensation unit into a data voltage. The compensation value for each pixel block is collectively applied to each pixel in the pixel block in at least one color. The pixel data and the compensation value for each pixel block are added between data of the same color.

The compensation value for each pixel block compensates for unevenness obtained through image capture of the display panel.

The pixel block includes at least one first pentile pixel including a first color subpixel and a second color subpixel; and at least one second pentile pixel including a subpixel of a third color and a subpixel of the second color.

The pixel block includes at least one first real color pixel including a first color subpixel, a second color subpixel, and a third color subpixel; and at least one second real color pixel including the first color subpixel, the second color subpixel, and the fourth color subpixel.

The compensation unit is applied to both the display panel including the pentile pixels and the display panel including the real color pixels according to the register setting value.

The real-time compensation circuit further includes a real/pentile conversion unit. The real/pentile converter converts first real pixel data including data of the first color, data of the second color, and data of the third color into first pixel data including data of the first color and data of the second color. Converting to pentile pixel data, second real pixel data including the first color data, the second color data, and the third color data are converted into the third color data and the second color data. Convert to second pentile pixel data including.

The compensation unit adds the compensation value for each pixel block to the pixel data of the input image received from the real/pentile conversion unit.

The compensation value for each pixel block includes a first compensation value applied collectively to subpixels of the first color, a second compensation value applied collectively to subpixels of the second color, and subpixels of the third color. Includes a third compensation value that is applied collectively.

The pixel block includes a left half sub-block including the first and second pentile pixels located in the left half of the pixel block, and the first and second pentile pixels located in the right half of the pixel block. Includes.

The compensation value for each pixel block includes a first compensation value applied collectively to subpixels of the first color, and a 2-1 compensation value applied collectively to subpixels of the second color present in the left half subblock. , a 2-2 compensation value collectively applied to subpixels of the second color present in the right half subblock, and a third compensation value collectively applied to subpixels of the third color.

The pixel block contains 8 x 4 pixels. Each of the left half pixel block and the right half pixel block includes 4 x 4 pixels.

In a pixel array of a display panel having a resolution of x Compensation value data size + checksum data size.

In the pixel array of the display panel having a resolution of ) x is the compensation value data size.

The first compensation value, the 2-1 compensation value, the 2-2 compensation value, and the third compensation value are each 8 bit data.

When the display panel operates in partial mode, the compensation value for each pixel block is applied to pixel data only for all pixels among all pixels of the display panel.

The compensation unit adds a weighted result to the compensation value to the pixel data of the input image.

The compensation unit includes one or more lookup tables in which weights are individually set according to the luminance value received from the host system and the pixel data of the input image.

The compensation unit adds a weighted result to the compensation value to the pixel data of the input image. When the display panel is driven in HBM (high brightness mode) mode, a relatively large weight among the weights is added to the compensation value.

The first memory includes flash memory, and the second memory includes static RAM (SRAM).

The real-time compensation circuit of the present invention includes a memory storing a plurality of compensation values for each pixel block set in units of pixel blocks including M x N (M and N are each positive integers of 2 or more) pixels; a compensation unit that modulates the pixel data of an input image by adding a compensation value for each pixel block to the pixel data; and a data driver that converts the compensated pixel data received from the compensation unit into a data voltage.

The electroluminescent display device of the present invention includes a display panel on which data lines, gate lines crossing the data lines, and pixels are arranged; a first memory storing a plurality of compensation values for each pixel block set in units of pixel blocks including M x N (where M and N are positive integers of 2 or more) pixels; and a drive integrated circuit that generates compensated pixel data by adding the compensation value for each pixel block read from the first memory to the pixel data of the input image, converts the compensated pixel data into a data voltage, and applies it to the data lines. is provided. The compensation value for each pixel block includes a compensation value collectively applied to each pixel in the pixel block in at least one color.

The present invention sufficiently compensates for and compensates for differences in driving characteristics between pixels in high-resolution, high-speed driving by compensating the pixel data of the input image with a compensation value for each pixel block that compensates for mura on the screen by reflecting the screen shooting results using a camera. The memory capacity of the circuit can be reduced.

Since the present invention compensates for pixel data using only gray level without calculating the threshold voltage (Vth) and mobility of the driving element, the logic circuit configuration for calculation can be reduced and the tact time (Tact time) can be reduced. ) can be reduced.

The present invention can realize the common use of drive ICs by compensating the pixel data of the input image with a compensation value for each pixel block according to the pentile pixel arrangement and the real pixel arrangement, respectively, according to the register settings. Drive modes can be supported.

1 is a diagram schematically showing a method of determining a compensation value using a camera mura measurement method in an electroluminescent display device according to an embodiment of the present invention.
Figure 2 is a flowchart showing a compensation method for an electroluminescent display device according to an embodiment of the present invention.
Figure 3 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.
Figure 4 is a diagram showing an example of pentile pixel arrangement.
Figure 5 is a diagram showing an example of real pixel arrangement.
Figure 6 is a circuit diagram showing an example of a pixel circuit.
FIG. 7 is a waveform diagram showing a method of driving the pixel circuit shown in FIG. 6.
Figure 8 is a diagram showing an example in which various image processing circuits and a compensation unit are connected.
Figure 9 is a diagram showing the compensation unit in detail.
Figure 10 is a diagram showing an example of an 8x4 pixel block applicable to pentile pixel arrangement.
FIG. 11 is a diagram showing an example of grouping pixels by dividing them into 8x4 pixel blocks shown in FIG. 10 in the pentile pixel arrangement of WQXGA (1600x2560).
FIG. 12 is a diagram showing subpixels for each color when the pentile pixel arrangement of WQXGA (1600x2560) as shown in FIG. 11 is divided into 8x4 pixel blocks.
Figure 13 is a diagram showing an example in which compensation values are stored in the first memory in the order of scan directions defined by PID = 00 and SID = 00 when the screen of WQXGA is divided into 8x4 pixel blocks in the same manner as Figures 10 to 12. .
FIG. 14 is a diagram showing compensation values and checksum data stored in the first memory in the same order as FIG. 13.
Figure 15 is a diagram showing the 4 Byte compensation value defined in one 8x4 pixel block.
Figure 16 is a diagram showing an example of an 8x4 pixel block applicable to real pixel arrangement.
FIG. 17 is a diagram showing an example of grouping pixels by dividing them into 8x4 pixel blocks shown in FIG. 16 in a real pixel arrangement of resolution (1072x2560).
FIG. 18 is a diagram showing subpixels for each color when the real pixel arrangement of the same resolution (1072x2560) as in FIG. 17 is divided into 8x4 pixel blocks.
Figure 19 shows an example in which compensation values are stored in the first memory in the order of the scan direction defined by PID = 00 and SID = 00 when the screen with a resolution (1072x2560) is divided into 8x4 pixel blocks in the same manner as in Figures 16 to 18. This is a drawing given.
FIG. 20 is a diagram showing compensation values and checksum data stored in the first memory in the same order as FIG. 19.
Figure 21 is a diagram showing the 3 Byte compensation value defined in one 8x4 pixel block.
FIG. 22 is a diagram showing an example of applying the compensation value of the 8x4 pixel block shown in FIG. 10 to pixel data.
FIG. 23 is a diagram showing an example of applying the compensation value of the 8x4 pixel block shown in FIG. 16 to pixel data.
Figure 24 is a flowchart showing the overflow and underflow operation processing of the operation unit.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms, but the present embodiments only serve to ensure that the disclosure of the present invention is complete and are within the scope of common knowledge in the technical field to which the present invention pertains. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification. Additionally, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description.

In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other parts placed between the two parts, unless 'directly' is used.

In the description of the implementation, first, second, etc. are used to describe various elements, but these elements are not limited by these terms. These terms are merely used to distinguish one component from another. Accordingly, the first component mentioned below may also be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

Each of the features of the various embodiments of the present invention can be combined or combined with each other partially or entirely, and various technical interconnections and operations are possible, and each embodiment may be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings. In the following embodiments, the description will focus on an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical idea of the present invention is not limited to organic light emitting display devices, but can be applied to inorganic light emitting display devices including inorganic light emitting materials.

The real-time compensation circuit of the present invention is a first memory storing compensation values for a plurality of pixel blocks set in units of pixel blocks including M A second memory that receives a separate compensation value, a compensation unit that modulates the pixel data by adding the compensation value for each pixel block to the pixel data of the input image, and a data driver that converts the compensated pixel data received from the compensation unit into a data voltage. Equipped with

The compensation value for each pixel block includes a compensation value collectively applied to each pixel in the pixel block in at least one color. The pixel data and the compensation value for each pixel block are added between data of the same color.

The compensation value for each pixel block is set to a value that compensates for spots obtained through image capture of the display panel.

A compensation circuit for compensating for differences in driving characteristics of pixels in an organic light emitting display device may be divided into an internal compensation circuit and an external compensation circuit. The internal compensation circuit uses an internal compensation circuit placed in each pixel to sample the threshold voltage of the driving element and adds the threshold voltage to the data voltage of the pixel data to drive the pixels, thereby reducing the threshold voltage difference between the driving elements within the pixel circuit. Automatically compensates. The external compensation circuit senses the electrical characteristics of the driving elements and modulates the pixel data of the input image based on the sensing results to compensate for changes in the driving characteristics of each pixel.

It should be noted that the compensation circuit of the present invention will be described in the following embodiments with a focus on the internal compensation circuit, but is not limited thereto.

In the electroluminescence display device of the present invention, the pixels and the gate driver include a plurality of transistors. A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage to allow holes to flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. In the following description of the embodiment, the source and drain of the transistor will be referred to as first and second electrodes. In the following description, the invention is not limited by the source and drain of the transistor.

Referring to FIGS. 1 and 2 , in the inspection process, image data for testing is input to the electroluminescent display device and the image for testing is displayed on the screen. The electroluminescent display device displays image data for testing while compensating in real time the driving characteristic deviation of each pixel through a compensation circuit (S1). In such an electroluminescent display device, compensation may be unstable due to insufficient sampling time of the driving element in each pixel. As a result, even if data of the same gray level is written to the pixels, spots may be visible on the screen due to the difference in luminance between pixels.

The computer 200 displays a test image on the display panel 100 of the electroluminescent display device at the inspection factory according to a preset program, and captures the screen of the display panel 100 with the camera 210 to create a test image. Measure luminance (S2). Incomplete compensation may be reflected in the image displayed on the electroluminescence display, causing spots to appear, and these spots are photographed by the camera 210. The test image captured by the camera 210 is transmitted to the computer 200.

The computer 200 stores a reference compensation value set in pixel block units of a preset size. A pixel block contains M x N pixels. The computer 200 adjusts the reference compensation value until the luminance difference between pixels in the image received from the camera 210 becomes less than the preset luminance uniformity, and adds the compensation value to each pixel data of the test image to provide compensation data. It is generated and transmitted to the display panel driving circuit. The display panel driving circuit writes pixel data of the input image to pixels of the display panel 100 and displays the pixel data of the input image in the pixels. If spots are visible in the image captured by the camera 210, it means that the difference in luminance between pixels is greater than the preset luminance uniformity.

The display panel driving circuit writes the pixel data of the test image received from the computer 200 to the pixels of the display panel 100 and displays the pixel data of the test image to which the compensation value is applied on the screen, and the camera 210 ) captures an updated test image (S2 to S4). The computer 200 stores the compensation value applied when the luminance difference between pixels of the image received from the camera 210 falls below the preset luminance uniformity as the optimal compensation value in the memory (S5 and S6). The optimal compensation value is stored in the first memory 30 connected to the compensation circuit of the electroluminescent display device. The first memory 30 may be a memory that retains stored information even when the power is turned off and is free to read/write, for example, a flash memory, but is not limited thereto. Compensation values for each pixel block are generated for each color and gray level for each pixel block by repeating steps S1 to S6.

The compensation value for each pixel block is divided into real pixel pixel arrangement and pentile pixel arrangement. Real pixel arrangement consists of one pixel consisting of red, green, and blue subpixels. As a result of performing steps S1 to S6 while driving a display panel having a real pixel arrangement, compensation values for each pixel block of the real pixel arrangement can be obtained. A display panel with a pentile pixel arrangement uses a preset pentile pixel rendering algorithm to drive two subpixels of different colors as one pixel. As a result of performing steps S1 to S6 while driving this display panel, compensation values for each pixel block of the pentile pixel arrangement can be obtained. The Pentile pixel rendering algorithm compensates for the lack of color expression in each pixel with the color of light emitted from adjacent pixels.

After shipping, the electroluminescent display device in which the optimal compensation value is stored through processes S1 to S6 loads the compensation value stored in the first memory 30 into the second memory in the compensation circuit every time the power is turned on. The second memory 31 may be implemented as random-access memory (RAM) such as static RAM (SRAM).

The electroluminescent display device of the present invention compensates for the pixel data in real time by collectively applying the compensation value read from the second memory to the pixel data in at least one color within the pixel block when the input image is pixel data ( S7). Therefore, the present invention extracts the camera shooting-based mura compensation value in pixel block units and applies the compensation value to at least one color within the pixel block at the same time, so that the internal /Even if the compensation of the external compensation circuit is not sufficient, uniform image quality can be achieved throughout the screen by additionally reflecting camera shooting-based mura compensation, and the memory capacity to which the compensation value is applied can be significantly reduced.

Figure 3 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.

3 to 5, the electroluminescent display device of the present invention includes a display panel 100 and a drive IC (Integrated Circuit) 20 for writing pixel data of an input image into pixels of the display panel 100. , a first memory 30 connected to the drive IC 20, a gate driver 40, a host system 50, etc.

The display panel 100 includes data lines, gate lines GL1 and GL2 that intersect the data lines DL1 to DL6, and a pixel array in which pixels P are arranged in a matrix form. The data lines DL1 to DL6 supply data voltage from the drive IC 20 to the pixels P. The gate lines GL1 to GL3 supply the gate signal from the gate driver 40 to the pixels P. As shown in FIG. 6, the gate signal can be divided into a scan signal (SCAN), an emission control signal (hereinafter referred to as “EM signal”) (EM), an initialization signal (INI), etc. In this case, the gate lines (GL1, GL2) each have a SCAN line 71 for supplying the scan signal (SCAN) to the pixels (P) of line 1 and the EM signal (EM) to supply the pixels (P) of line 1. ), an EM line 72 for supplying the initialization signal (INI) to the pixels (P) of line 1, and an INI line 73.

Each pixel includes subpixels of different colors for color implementation. Subpixels include red (hereinafter referred to as “R subpixel”), green (hereinafter referred to as “G subpixel”), and blue (hereinafter referred to as “B subpixel”). Although not shown, white subpixels (White, hereinafter referred to as “W subpixels”) may be further included. Each of the subpixels may include, but is not limited to, the pixel circuit shown in FIG. 6. It should be noted that the pixel circuit may be implemented with pixel circuits of various known structures.

Figure 4 is a diagram showing an example of pentile pixel arrangement. In the example of Figure 4, one pixel includes R subpixels and G subpixels or B and G subpixels. In the pentaming pixel arrangement, each pixel is composed of two sub-pixels in the example of FIG. 4, but the present invention is not limited thereto. The Pentile pixel rendering algorithm renders each pixel data of the input image including RGB data according to the color arrangement of the pixel (P), and compensates for color expression by adding insufficient color data to the color data of neighboring pixels. Any known Pentile pixel rendering algorithm can be used.

Figure 5 is a diagram showing an example of real pixel arrangement. In the example of Figure 5, one pixel includes an R subpixel, a G subpixel, and a B subpixel. Accordingly, in the real pixel arrangement, each pixel is composed of three sub-pixels in the example of FIG. 5, but the present invention is not limited thereto.

As shown in FIG. 6, the display panel 100 has an ELVDD line 74 for supplying the pixel driving voltage ELVDD to the pixels P, and a Vref line for supplying the reference voltage Vref to the pixels ( 75), and an ELVSS electrode 76 for supplying a low-potential power supply voltage (ELVSS) to the pixels. These power lines are connected to a power circuit not shown. The power circuit uses a DC-DC converter to generate the DC power needed to drive the display panel. The DC-DC converter includes a charge pump, regulator, buck converter, boost converter, etc. The power circuit can be implemented with a power IC (Power Integrated Circuit, PIC).

The power circuit outputs the power necessary to drive the pixels (P) of the display panel, such as ELVDD, VGH, VGL, Vref, and analog gamma voltage. VGH is the Gate High Voltage, and VGL is the Gate Low Voltage.

A gate driver 40 may be formed and mounted on the substrate of the display panel 100 along with a pixel array. Each of the pixels P and the gate driver 40 is implemented with a plurality of transistors. The transistors are one of a thin film transistor (hereinafter referred to as “TFT”) containing an oxide semiconductor, a TFT containing amorphous silicon (a-Si), or a TFT transistor containing low temperature poly silicon (LTPS). It can be implemented as above. TFT can be implemented with a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. The TFT may be implemented with either an n-type transistor (NMOS) or a p-type transistor (PMOS) or a combination thereof.

The gate signal output from the gate driver 40 is between the gate on voltage at which the TFT can be turned on and the gate off voltage at which the TFT can be turned off. swing from In NMOS, the gate-on voltage is VGH and the gate-off voltage is VGL. In PMOS, the gate-on voltage is VGL and the gate-off voltage is VGH.

The gate driver 40 includes a shift register. The shift register includes a number of stages connected dependently and sequentially supplies gate signals (GATE1, GATE2) to the gate lines (GL1, GL2) by shifting the output voltage according to the gate shift clock timing. do.

The driver IC 20 includes a timing control unit 21, a data driver 22, a second memory 31, a compensation unit 32, a register 33, etc.

The timing control unit 21 uses timing signals received from the host system 50, such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a dot clock signal (DCLK), and a data enable signal (DE). Thus, timing control signals for controlling the operation timing of the gate driver 40 and the data driver 22 are generated. The host system 50 may be any one of a television system, set-top box, navigation system, personal computer (PC), home theater system, mobile system, wearable system, and virtual reality system.

The data driver 22 is a digital to analog converter (hereinafter referred to as a digital to analog converter) that converts the pixel data (digital signal) of the input image received from the compensator 32 into an analog signal and outputs data signals (DATA1 to DATA6). (referred to as “DAC”). The data driver 22 supplies data signals DATA1 to DATA6 to the pixels P through data lines DL1 to DL6.

The second memory 31 stores the compensation value received from the first memory 30 when power is input and supplies the compensation value to the compensation unit 32. The compensation unit 32 receives pixel data of the input image from the host system 50. The compensation unit 32 adds the compensation value for each pixel block input from the second memory 31 to the pixel data of the input image and transmits it to the data driver 22. Accordingly, pixel data input to the data driver 22 includes compensation values obtained through camera shooting.

The register 33 stores tables defining the function settings of the compensation unit 32. The function of the compensation unit 32 can be changed depending on the register setting value.

Figure 6 is a circuit diagram showing an example of a pixel circuit. FIG. 7 is a waveform diagram showing a method of driving the pixel circuit shown in FIG. 6. The pixel circuit of the present invention is not limited to Figure 6.

Referring to FIGS. 6 and 7 , the pixel circuit includes a plurality of TFTs (M1 to M6), a capacitor (Cstg), and an OLED.

A scan signal (SCAN), an initialization signal (INI), and an EM signal (EM) are supplied to the pixels (P) during one horizontal period (1H). 1 horizontal period (1H) is the t2 and t3 period for initializing the pixel circuit, and the voltage of the data signal ( Includes a t4 period compensating for Vdata).

OLED includes an anode and cathode. The anode of the OLED is connected to the fifth and sixth TFTs (M5, M6). A low-potential power supply voltage (ELVSS) is applied to the cathode of the OLED.

The first TFT (M1) is turned on according to the scan signal (SCAN) and applies the data signal from the data line 77 to the first node (n1). The first TFT (M1) includes a gate connected to the scan line 71, a first electrode connected to the data line 77, and a second electrode connected to the first node (n1).

The second TFT (M2) is turned on according to the EM signal (EM) to initialize the first node (n1) to a predetermined reference voltage (Vref). The second TFT (M2) includes a gate connected to the EM line 72, a first electrode connected to the first node (n1), and a second electrode connected to the Vref line 75 to receive a reference voltage (Vref). do. The fifth TFT (M5) is turned on according to the EM signal (EM) to initialize the third node (n3) to the reference voltage (Vref). The fifth TFT (M5) includes a gate connected to the EM line 72, a first electrode connected to the third node (n3), and a second electrode connected to the anode of the OLED.

The third TFT (M3) is a driving element that drives the OLED by controlling the current flowing through the OLED according to the gate voltage. The third TFT (M3) includes a gate connected to the second node (n1), a first electrode connected to the ELVDD line 74 to receive ELVDD, and a second electrode connected to the third node (n3). The capacitor Cst is connected between the first and second nodes n1 and n2 and maintains the data voltage plus the threshold voltage of the third TFT M3 for one frame period.

The fourth TFT (M4) is turned on during a period (t3, t4) during which the threshold voltage of the third TFT (M3) is sampled and connects the gate of the third TFT (M3) to the second electrode. The third TFT (M3) operates as a diode by the fourth TFT (M4) during the period t3 and t4. The fourth TFT (M4) has a gate connected to the SCAN line 71 to receive a scan signal (SCAN), a first electrode connected to the gate of the third TFT (M3), and a second electrode of the third TFT (T3). It includes a second electrode connected to.

The sixth TFT (M6) is turned on according to the initialization signal (INI) to initialize the anode of the OLED to the reference voltage (Vref). The sixth TFT (M6) includes a gate connected to the INI line 73, a first electrode connected to the Vref line 75, and a second electrode connected to the anode of the OLED.

The operation of this pixel circuit is explained step by step as follows.

Each of the pixels maintains the previous frame data in the t1 period. During the t1 period, the reference voltage Vref is applied to the first node n1.

The gate-on voltage of the initialization signal (INI) is applied to the pixel circuit at the start of the t2 period, and immediately thereafter, the gate-on voltage of the scan signal (SCAN) is applied to the pixel circuit in the t3 period. In the t2 and t3 periods, after the sixth TFT (M6) is turned on according to the gate-on voltage of the initialization signal (INI), the first and fourth TFTs (M1, M4) are turned on according to the gate-on voltage of the scan signal (INI). It turns on depending on the voltage. Since the EM signal EM maintains the gate-on voltage during the t2 and t3 periods, the second and fifth TFTs M2 and M5 remain on. As a result, in the t2 period, the first node (n1), the second node (n2), the third node (n3), and the anode of the OLED are initialized to the reference voltage (Vref).

The EM signal (EM) is inverted to the gate-off voltage during the t4 period. Accordingly, the second and fifth TFTs M2 and M5 are turned off during the t4 period. During the t4 period, the data voltage DATA is charged to the first node n1 through the first TFT M1. During the t4 period, when the voltage between the gate of the third TFT (M3) and the second electrode reaches ELVDD+Vth, the third TFT (M3) is turned off. As a result, the voltage of the second and third nodes is charged to ELVDD+Vth during the t4 period. At this time, the voltage of the capacitor (Cstg) is ELVDD+Vth+Vdata. Vth is the threshold voltage of the third TFT (M3), which is a driving element. The t4 period is a programming period in which the threshold voltage (Vth) of the third TFT (M3), which is a driving element, is sampled and the data voltage (Vdata) is compensated by the threshold voltage (Vth).

The EM signal (EM) is inverted to the gate-on voltage at the beginning of the t5 period. The t5 period is a light emission period in which the OLED emits light according to the data voltage and emits light as much as the gradation of the pixel data. During the t5 period, the scan signal (SCAN) and the initialization signal (INI) are inverted to the gate-off voltage. Accordingly, during the t5 period, the second and fifth TFTs (M2, M5) are turned on to form a current path of the OLED, while the other switch elements (M1, M4, M6) are turned off.

The current (I _oled ) flowing through the OLED during the t5 period is expressed in the equation below. As can be seen from this equation, the current flowing through the OLED is not affected by the Vth of the third TFT (M3) and therefore is not affected by changes in Vth over time or Vth differences between pixels. In the equation below, Vgs is the voltage between the gate and source of the third TFT (M3), and Vds is the voltage between the drain and source of the third TFT (M3).

Here, K is a proportionality constant determined by the charge mobility, parasitic capacitance, and channel capacity of the third TFT (M3).

An image processing circuit other than the compensator 32 may be connected to the compensator 32 to complexly process pixel data of the input image. In this case, the compensator 32 and other image processing circuits must be efficiently connected.

Figure 8 is a diagram showing an example in which various image processing circuits and a compensation unit are connected.

Referring to FIG. 8, the drive IC 20 further includes an image quality enhancement unit 81 and a real/pentile conversion unit 82 disposed in front of the compensation unit 32.

The image quality improvement unit 81 processes input image data using a preset algorithm to improve image quality, such as color temperature compensation, sharpness improvement, and HDR (High Dynamic Range).

The Real/Pentile converter 82 converts real pixel data (RGB data) into Pentile pixel data (RG or GB data) using the Pentile pixel rendering algorithm. Real pixel data RGB RGB (2 pixel, 6 sub-pixel) is converted into RG BG (2 pixel, 4 sub-pixel) by the real/pentile conversion unit 82.

When the compensation unit 32 is placed in front of the image quality improvement unit 81 or the real/pentile conversion unit 82, the compensation value for each pixel block is added by the compensation unit 32 and the modulated pixel data is converted to the image quality improvement unit 81. ) and/or the pixel data is modulated again by the real/pentile converter 82, so that the effect of applying the compensation value for each pixel block may vary. Therefore, it is efficient for the compensation unit 32 to apply a compensation value for each pixel block to pixel data modulated by another image processing circuit.

Figure 9 is a diagram showing the compensation unit 32 in detail.

Referring to FIG. 9, the compensation unit 32 collectively applies the compensation value for each pixel block obtained through camera photography to at least one color within the pixel block of the input image. The present invention can significantly reduce the capacity of the memories 30 and 31 by grouping pixels into pixel blocks of a preset size and collectively applying the same compensation value to pixel data of at least one color within the pixel block.

The function of the compensation unit 32 can be selected according to the register setting value defined in the table in the register 33. The compensation unit 32 includes a calculation unit 321 and one or more look-up tables (LUTs) 341 to 349.

The operation unit 321 modulates the pixel data by adding a compensation value for each pixel block to the pixel data (DATA) of the input image, thereby outputting data (DATA') to which a camera shooting-based mura compensation value has been applied. A preset weight may be added to each of the compensation values for each pixel block in the lookup tables 341 to 349. The weight may vary depending on the luminance value received from the host system and the pixel data of the input image. The lookup tables 341 and 342 may be selected and output weights according to the driving mode of the display device, the luminance value received from the host system, and the pixel data of the input image. The host system 50 can automatically switch the driving mode by analyzing various sensor signals or can switch the driving mode according to a user command input through a user interface.

The lookup tables 341 to 349 set weights differently depending on the luminance value (DBV) or input grayscale value (GRAY) input to the host system 50. The input grayscale value is the grayscale of pixel data received from input image data, that is, the original grayscale value. The weight output from the lookup table is an additional compensation value added to the compensation value for each pixel block loaded from the second memory 31 and is reflected in the pixel data of the input image. The brightness value (DBV) indicates the brightness corresponding to the maximum gray level value of pixel data, for example, gray level 255 in the case of 8-bit data. The luminance value (DBV) is a luminance value automatically set by the host system using a user command input from the user through a user interface or various sensors such as an illuminance sensor.

The calculation unit 32 inputs the luminance value (DBV) and the input gray level value (GRAY) into the lookup tables 341 to 349 in the manner shown in Table 1 below and calculates the weight output from the lookup tables 341 to 349. It can be added to the compensation value for each pixel block, and the result can be added to the pixel data. Each of the lookup tables 341 to 349 is selected according to the luminance value (DBV) and the input grayscale value (GRAY) in the same manner as Table 1. For example, LUT1 341 is selected when the luminance value (DBV) is GCBDBV_TH1[9:0] and the grayscale value (GRAY) is GCBGRAY_TH1[7:0]. LUT3 (343) is selected when the luminance value (DBV) is GCBDBV_255 and the grayscale value (GRAY) is GCBGRAY_TH1[7:0]. LUT9 (349) is selected when the luminance value (DBV) is GCBDBV_1023 and the grayscale value (GRAY) is GCBGRAY_255.

If mura is seen in a different way depending on the luminance value of the maximum gray level or the gray level value of the pixel data using the weight set in the lookup table (341 to 349), it is determined according to the luminance value (DBV) and gray level value (GRAY). Various mura can be compensated for in detail. If the weight is set to lookup table data as shown in Table 1 below, detailed compensation can be implemented by distinguishing the compensation value in 9 situations where the luminance value and grayscale value are different.

GCBGRAY_TH1[7:0] GCBGRAY_TH2[7:0] GCBGRAY_255 GCBDBV_TH1[9:0] LUT1 LUT2 LUT3 GCBDBV_TH2[9:0] LUT4 LUT5 LUT6 GCBDBV_1023 LUT7 LUT8 LUT9

The example below illustrates Table 1 in quantitative values. In the table below, when the luminance value (DBV) is 50 nit or less and the grayscale value (GRAY) is 15 or less, +2 set in LUT1 (341) is output. When the luminance value (DBV) is greater than 100 nit and less than 200 nit, and when the grayscale value (GRAY) is greater than 100 and less than 200, -1 set in LUT9 (349) is output. The method of setting the weight of the lookup table is not limited to this.

The register 33 includes one or more tables 331 to 333 that store setting values for controlling the operation unit 321. Register settings may be stored in the first memory 30 and loaded from the first memory 30 to the second memory 31.

The first table 331 may be set as shown in Table 2 below. The first table 331 defines whether and how to support the compensator 32 in various operation modes supported by the drive IC 20, along with the On/Off settings of the compensator 32. . In Table 2, “Normal” is a state in which pixel data does not pass through the compensator 32 but is bypassed to the data driver 22. “GCB” is a camera shooting-based mura compensation method of the present invention. Therefore, GCB is a state in which pixel data is input to the compensation unit 32 and the pixel data is modulated by the compensation value for each pixel block.

“PPA” stands for Pentile Pixel Arrangement. The compensator 32 supports real color placement (RGB) and pentile color placement (RG/GB) at all resolutions. The compensation unit 32 supports all panel scan directions. PID (Panel ID) and SID (Scan ID) define various scan directions, such as whether the scan direction proceeds from the upper left to the lower right, or from the upper right to the lower left. PID (Panel ID) and SID (Scan ID) allow the scanning direction to be changed according to real color arrangement (RGB) and pentile color arrangement (RG/GB) or according to the position of the drive IC 20.

In Table 2, the partial mode is a driving mode in which only some pixels in the pixel array of the display panel 100 are driven and other pixels are turned off. In always on mode, virtual reality mode (VR), etc., the screen can be driven in partial mode. The compensation unit 32 applies compensation values for each pixel block only to pixel data to be written to ON pixels in partial mode and bypasses other invalid data, thereby increasing data operation speed and consumption. Power and heat generation can be managed efficiently.

Idle mode is a low power model that reproduces pixel data with only 8 colors by allowing only the minimum gradation (G0) and maximum gradation (G255) to be expressed in each RGB color. In this idle mode, there is no difference in image quality whether the compensation value is applied by the compensator 32 or not, so the compensator 32 is not driven in the idle mode.

PLC (peak luminance control) is a control method of the drive IC 20 that lowers peak luminance in a bright image to reduce power consumption when the luminance of the input image is above a certain level. The compensation unit 32 may operate in a PLC.

BC (Brightness control) is a various brightness control method of the drive IC 20. HBM (High brightness mode) is a driving mode that increases the brightness of pixels in an outdoor environment. ISP (image signal processing) is another image processing circuit described in the example of FIG. 8. The compensation unit 32 can support BC, HBM, and ISP. In order to increase luminance in HBM, the compensation unit 32 can further increase the luminance of pixels by adding the maximum weight (GCB_LUT7) set in a look-up table (LUT) to the compensation value for each pixel block.

State Normal GCB Remark Resolution Support Support Real support, PPA support, support all resolutions Panel Scan Direction Support Support Operates on all PIDs and SIDs (changing PIDs and SIDs during operation is not supported) Partial Mode Support Support 1. No calculation required for non-display areas
2. Partial area can be set line by line.
3. GCB SRAM read function is supported by a partial area set. Idle Mode Support N/A G0, G255 don't need GCB.
Image data bypasses the GCB block plc Support Support B.C. Support Support HBM Support Support Operates as GCBDBV_1023 (GCB_LUT7~9) ISP Support Support

The second table 332 may be set as shown in Table 3 below. The second table 332 defines whether to apply weights, data error check options, etc.

In Table 3, "GCB_LUT_EN: defines whether to apply weight. "GCB_ERRFG" is the GCB error flag. Compensation value stored in the first memory 30 of the drive IC 20 when power is input to the drive IC 20. All are loaded into the second memory 31. At this time, while loading the compensation value, the drive IC 20 calculates a checksum to check for errors in the received data, and stores this value in the first memory ( 30) Check for abnormalities by comparing them with the checksum result stored in 30). If it is determined that there is an abnormality in the received data as a result of the checksum calculation, change :GCB_ERRFG" to 1 to indicate that there is an error in the data loading exaggeration. "GCB_ERR_CNT[1:0]" means that if an error occurs in the checksum comparison process, the drive IC 20 reads the data again from the first memory 30 and loads it. The number of repetitions allowed in this process is Define. If "GCB_ERR_CNT[1:0]" is set to 2, checksum errors are allowed twice and reloading of data from the first memory 30 is possible up to three times. If the error still occurs because the number of loading times defined in "GCB_ERR_CNT[1:0]" is exceeded, change GCB_ERRFG to 1 and operate as defined in :GCB_CON". "GCB_SUM[15:0]" is the drive IC (20) It is a value stored so that the checksum result calculated in can be checked externally. "FLASH_RD_ST", "FRASH_RD_STB", and "FLASH_FRM[2:0]" are read out options of the second memory data. Depending on the specifications of the first memory, Options may change.

Register Name Description Default GCB_EN 0: Bypass 1: Enable 0h GCBDBV_TH1~2[9:0] Luminance LUT Range settings.
Both TH1 and TH12 can be set from 0 to 1023.
0 ≤ TH1 ≤ TH2 ≤ 1023 GCBGRAY_TH1~2[7:0] Gray LUT Range settings.
Both TH1 and 2 can be set from 0 to 255.
0 ≤ TH1 ≤ TH2 ≤ 255 GCB_LUT1~9[3:0] weight.
Final Output = Compensation value for each pixel block + LUT output
For HBM, GCB_LUT7~9 operates
0: Bypass (Original image)
1: -7 2: -6 3:-5 4:-4 5:-3 6:-2 7:-1 8:+0 9:+1 10:+2 11:+3 12:+4 13: +5 14:+6 15:+7 8h GCB_LUT_EN 0: Disable (no weighting applied)
1: Enable (apply weighting)
(HBM applies weight to GCB_LUT7~9 output even if GCB_LUT_EN=0) 0h GCB_SUM[15:0] Checksum parameters. Read only GCB_ERRFG
If the number of failures set in GCB_ERR_CNT is exceeded, GCB_ERRFG is changed to 1.
Recovery to 0 only during sleep-in. Read only GCB_ERR_CNT[1:0] Number of failures allowed during checksum comparison
0: 0 1: 1 2: 2 3: 3 1h GCB_CON When GCB_ERRFG is 1 (in case of a read error in the first memory), set the GCB operation.
0: Ignore Error and operate GCB,
1: GCB function bypass 1h FLASH_RD_ST Read start point of first memory during sleep-out
0: Simultaneous with sleep-out
1: After (FLASH_RD_STB + FLASH_FRM) hours 0h FLASH_RD_STB[7:0] Flash read start delay during sleep-out.
0H~255H 0h FLASH_FRM[2:0] Frame delay to apply to FLASH_RD_ST.
0: 0 frame 1: 0.5 2: 1 3: 1.5 4: 2 5: 2.5 6: 3 7: 3.5 0h

The third table 333 may be set as shown in Table 4 below. The third table 333 defines read/write options of the first and second memories 30 and 31.

Register Name Description SRAM Read/Write
Define how users can read/write data to secondary memory Flash Read/Write Define data read/write method in each case: 2nd memory -> 1st memory, 1st memory -> 2nd memory Flash Low Power Mode After completing data read from the first memory, switch the first memory to low power mode (switch to normal mode when sleep-out) Flash Power Down Mode After completing data read from the first memory, switch the first memory to power down mode
(Switch to normal mode when sleep-out) SRAM Power Down Mode When disabling the GCB function is selected
Switch to power down mode of second memory

Figure 10 is a diagram showing an example of an 8x4 pixel block applicable to pentile pixel arrangement. FIG. 11 is a diagram showing an example of grouping pixels by dividing them into 8x4 pixel blocks shown in FIG. 10 in the pentile pixel arrangement of WQXGA (1600x2560). Figure 12 is a diagram showing the number of subpixels for each color when the pentile pixel arrangement of WQXGA (1600x2560) is divided into 8x4 pixel blocks.

Referring to FIG. 10, an 8x4 pixel block includes 8 pixels in the row direction and 4 pixels in the column direction. Each of the pixels P includes an R subpixel and a B subpixel as shown in FIG. 4, or includes two subpixels including a B subpixel and a G subpixel. Therefore, an 8x4 pixel block contains 16x4 subpixels.

Each piece of pixel data is input as real pixel data including RGB data, and the real/pentile conversion unit 82 converts the real pixel data into pixel data including RG or GB data. Real pixel data RGB RGB (2 pixel, 6 sub-pixel) is converted into RG BG (2 pixel, 4 sub-pixel) by the real/pentile conversion unit 82.

Each of the R data and B data to be written in an 8x4 pixel block is 8x4 when viewed as real pixel data. There are 8x4 G data to be written in 8x4 pixel blocks.

In the case of an 8x4 pixel block as shown in Figure 10, the compensation value for each pixel group is divided into one R compensation value to be applied collectively to 8x4 pieces of R data, one B compensation value to be applied collectively to 8x4 pieces of B data, and 8x4 pieces of G data. It contains a total of four compensation values, including two G compensation values (GL, GR) to be applied. Accordingly, the compensation value for each pixel group includes much smaller compensation values than the actual number of pixels, thereby significantly reducing the memory capacity required for the compensation unit 32. Each compensation value may be 8 bits, that is, R: 8bit, GL: 8bit, B: 8bit, GR: 8bit. If each compensation value is 8 bit data, -127 to +128 can be expressed, so -127 to +128 can be added to the pixel data of the input image.

In order to express the luminance of a 4x4 pixel block in detail, the present invention separates the G compensation values (GL, GR), which have a large contribution to luminance, into two. When dividing a pixel block into a left half subblock (BLOCK1) and a right half (BLOCK2), the G compensation values (GL, GR) are the first G compensation applied collectively to the G subpixels of the left half subblock (BLOCK1). It is divided into a value GL and a second G compensation value GR applied collectively to the G subpixels of the right half subblock BLOCK2. Meanwhile, in the 2.2 gamma curve, the luminance contribution for each RGB color is R:G:B = 0.25:0.65:0.10.

It is not limited to the G compensation value being separated into two within an 8x4 pixel block. For example, in the case of a model that does not need to separate the G compensation value within an 8x4 pixel block, the G compensation value can be set to one.

When the pixel grouping method shown in FIGS. 10 to 12 is applied, 1600x2560 is divided into 8x4 pixel blocks in the pentile pixel arrangement of WQXGA (1600x2560), so the memory size of the second memory 31, that is, SRAM, is compensated for each pixel. The value is only 1600/8 x 2560/4 x 32bits = 4,096,000 bits, which is much less than the case where it is applied. Here, 32bits is the data size of R: 8bit, GL: 8bit, B: 8bit, and GR: 8bit. In the case of the display panel 100 having a resolution of x(Y/N) x This is the compensation value data size for each pixel block. In the above example, the compensation value data size for each pixel block = 8 bits x 4 = 32 bits.

Figures 13 to 15 are diagrams showing compensation values stored in the first memory 30 when the WQXGA screen is divided into 8x4 pixel blocks in the same manner as Figures 10 to 12. Figure 13 is a diagram showing an example in which compensation values are stored in the first memory in the order of scan directions defined by PID = 00 and SID = 00 when the screen of WQXGA is divided into 8x4 pixel blocks in the same manner as Figures 10 to 12. . FIG. 14 is a diagram showing compensation values and checksum data stored in the first memory in the same order as FIG. 13. Figure 15 is a diagram showing the 4 Byte compensation value defined in one 8x4 pixel block.

Referring to FIGS. 13 to 15 , compensation values for each pixel block may be stored in the first memory 30 in an order following a scan direction determined by the PID and SID. For example, when PID=00, SID=00, the compensation value of the pixel block located at the upper right (200, 1) of the screen from the compensation value (R1_1, GL1_1, B1_1, GR1_1) of the pixel block located at (1,1) at the upper left of the screen. Compensation values for each pixel block are stored in the first memory 30 in the following order: (R200_1, GL200_1, B200_1, GR200_1). Next, compensation values for each pixel block are stored in the order from the left pixel block below to the right pixel block. In this order, from the compensation value of the pixel block located at the bottom left (1,640) of the screen (R1_640 GL1_640, B1_640, GR1_640) to the compensation value of the pixel block located at the bottom right (200, 640) (R200_640, GL200_640, B200_640, Compensation values for each pixel block are stored in the first memory 30 in the order GR200_640).

Compensation values allocated to one 8x4 pixel block are stored in the first memory as 4 Byte data. For example, the compensation values to be applied to the pixel data of the upper left 8x4 pixel block (1,1) are 1 Byte of R compensation value (R1_1), 1 Byte of GL compensation value (GL1_1), and 1 Byte as shown in FIG. It includes a B compensation value (B1_1) and a GR compensation value (GR1_1) of 1 Byte. The luminance of the stain captured by the camera includes a stain (+) with a luminance higher than the target luminance and a stain (-) with a luminance lower than the target luminance. Therefore, the compensation value may also include a + compensation value and a - compensation value. When the compensation value is 8 bits, the compensation value can express -127 to + 128 in actual gray levels using 2's complement.

When transmitting compensation value data for each pixel block from the computer 200 to the first memory 30, 2 bytes of checksum data (Checksum1, Checksum2) for data error checking are stored in the first memory 30. Data for each pixel block is applied in real time to the pixel data of the input image, and checksum data (Checksum1, Checksum2) is not reflected in the pixel data.

Therefore, when the screen of the WQXGA is divided into 8x4 pixel blocks as shown in FIGS. 10 to 12, the size of the first memory 30, that is, the flash memory, is much smaller (200x640x4) bytes than when the compensation value is applied to each pixel. + It is only a 2byte checksum. In the case of the display panel 100 having X x Y resolution, the data size stored in the first memory 30 = (X/M) x (Y/N)

The drive IC 20 of the present invention can be applied to both display panels with a pentile pixel arrangement and display panels with a real pixel arrangement. By selecting the register settings according to the pixel arrangement, one drive IC (20) can be applied to a pentile pixel arrangement or a real pixel arrangement.

Figure 16 is a diagram showing an example of an 8x4 pixel block applicable to real pixel arrangement. FIG. 17 is a diagram showing an example of grouping pixels by dividing them into 8x4 pixel blocks shown in FIG. 16 in a real pixel arrangement of resolution (1072x2560). FIG. 18 is a diagram showing subpixels for each color when the real pixel arrangement of the same resolution (1072x2560) as in FIG. 17 is divided into 8x4 pixel blocks.

Referring to FIG. 16, an 8x4 pixel block includes 8 pixels in the row direction and 4 pixels in the column direction. Each of the pixels P includes an R subpixel, a G subpixel, and a B subpixel, as shown in FIG. 5 . Therefore, an 8x4 pixel block contains 24x4 subpixels. Each of the R data, G data, and B data to be written in an 8x4 pixel block is 8x4.

In the case of an 8x4 pixel block as shown in Figure 16, the compensation value for each pixel group is divided into one R compensation value to be applied collectively to 8x4 pieces of R data, one G compensation value to be applied collectively to 8x4 pieces of G data, and 8x4 pieces of B data. It contains a total of three compensation values, including one B compensation value to be applied. Accordingly, the compensation value for each pixel group includes much smaller compensation values than the actual number of pixels, thereby significantly reducing the memory capacity required for the compensation unit 32. Each compensation value may be 8 bits, that is, R: 8 bits, G: 8 bits, and B: 8 bits. If each compensation value is 8 bit data, -127 to +128 can be expressed, so -127 to +128 can be added to the pixel data of the input image.

The G compensation value may be set one for each 8x4 pixel block or may be divided into two for each pixel block in the same manner as the embodiment shown in FIG. 10.

When applying the pixel grouping method shown in FIGS. 16 to 18, 1072x2560 is divided into 8x4 pixel blocks in the real pixel arrangement of resolution (1072x2560), so the memory size of the second memory 31, that is, SRAM, is a compensation value for each pixel. Compared to the case where this is applied, it is only 1072/8 x 2560/4 x 24bits = 2,058,240 bits. Here, 24bits is the data size of R: 8bit, G: 8bit, and B: 8bit. In the case of the display panel 100 having X x Y resolution, the data size stored in the second memory 31, that is, SRAM = (X/M) In the above example, the compensation value data size for each pixel block is 8 bits x 3 = 24 bits.

FIGS. 19 to 21 are diagrams showing compensation values stored in the first memory 30 when a screen with a resolution of 1072x2560 is divided into 8x4 pixel blocks in the same manner as in FIGS. 16 to 18. Figure 19 shows an example in which compensation values are stored in the first memory in the order of the scan direction defined by PID = 00 and SID = 00 when the screen with a resolution (1072x2560) is divided into 8x4 pixel blocks in the same manner as in Figures 16 to 18. This is a drawing given. FIG. 20 is a diagram showing compensation values and checksum data stored in the first memory in the same order as FIG. 19. Figure 21 is a diagram showing the 3 Byte compensation value defined in one 8x4 pixel block.

Referring to FIGS. 19 to 21 , compensation values for each pixel block may be stored in the first memory 30 in an order following a scan direction determined by the PID and SID. For example, when PID = 00, SID = 00, the compensation value (R134_1) of the pixel block located in the upper left corner of the screen (1, 1) from the compensation value (R1_1, G1_1, B1_1) of the pixel block located in the upper right corner (134, 1) Compensation values for each pixel block are stored in the first memory 30 in the following order: , G134, and B134_1). Next, compensation values for each pixel block are stored in the order from the left pixel block below to the right pixel block. Following this order, from the compensation values (R1_640 G1_640, B1_640) of the pixel block located at the bottom left (1,640) of the screen, to the compensation values (R134_640, G134_640, B134_640) of the pixel block located at the bottom right (134, 640). Compensation values for each pixel block are sequentially stored in the first memory 30.

Compensation values allocated to one 8x4 pixel block are stored in the first memory 30 as 3 Byte data. For example, the compensation values to be applied to the pixel data of the upper left 8x4 pixel block (1,1) are 1 Byte of R compensation value (R1_1), 1 Byte of G compensation value (G1_1), and 1 Byte as shown in FIG. Includes the B compensation value (B1_1) of Byte.

When transmitting compensation value data for each pixel block from the computer 200 to the first memory 30, 2 bytes of checksum data (Checksum1, Checksum2) for data error checking are stored in the first memory 30. Data for each pixel block is applied in real time to the pixel data of the input image, and checksum data (Checksum1, Checksum2) is not reflected in the pixel data.

When a screen with a resolution (1072x2560) is divided into 8x4 pixel blocks in the same manner as shown in FIGS. 16 to 18, the size of the first memory, that is, the flash memory, is (134x640x4)byte + 2byte, which is much smaller than when a compensation value is applied to each pixel. It is just a checksum. In the case of the display panel 100 having X x Y resolution, the data size stored in the first memory 30 = (X/M) x (Y/N)

FIG. 22 is a diagram showing an example of applying the compensation value of the 8x4 pixel block shown in FIG. 10 to pixel data.

In Figure 22, "R4x4" is pixel data (R data) of the input image to be written in 4x4 R subpixels existing in the left half (BLOLK1) and right half (BLOLK2), respectively, and G4x4L" is the left half (BLOLK1). is the pixel data (G data) of the input image to be written in the 4x4 G subpixels existing in . G4x4R" is the pixel data (G data) of the input image to be written in the 4x4 G subpixels existing in the right half (BLOLK2) data). And “B4x4” is pixel data (B data) of the input image to be written in 4x4 B subpixels existing in the left half (BLOLK1) and right half (BLOLK2), respectively. “R1_1_OFFSET” is one R compensation value to be applied collectively to R subpixels. “GL1_1_OFFSET” is one G compensation value (GL) to be applied collectively to the G subpixels of the left half (BLOLK1). “GR1_1_OFFSET” is one G compensation value (GR) to be applied collectively to the G subpixels of the right half (BLOLK2). “B1_1_OFFSET” is one B compensation value to be applied to all B subpixels. A weight set in a lookup table may be added to each of the compensation values, but the method is not limited to this.

FIG. 23 is a diagram showing an example of applying the compensation value of the 8x4 pixel block shown in FIG. 16 to pixel data.

In FIG. 23, “R8x4” is pixel data (R data) of an input image to be written in 8x4 R subpixels, and “G8x4” is pixel data (G data) of an input image to be written in 8x4 G subpixels. "B8x4" is the pixel data (B data) of the input image to be written to 8x4 B subpixels. "R1_1_OFFSET" is one R compensation value to be applied to the R subpixels at once. "G1_1_OFFSET" is the G subpixels. This is one G compensation value to be applied collectively to B subpixels. “B1_1_OFFSET” is one B compensation value to be applied collectively to B subpixels. A weight set in a lookup table may be added to each of the compensation values, but is not limited to this.

In FIGS. 22 and 23, “Red Gray Output” is compensation applied R data written to R subpixels in a pixel block to which an R compensation value (R1_1_OFFSET) is added. “Green Gray Output” is compensated G data written to G subpixels in a pixel block to which G compensation values (GL1_1_OFFSET, GR1_1_OFFSET) are added. “Blue Gray Output” is compensated B data written to B subpixels in a pixel block to which the B compensation value (B1_1_OFFSET) is added.

The calculation unit 321 adjusts the calculation results of pixel data that overflows and underflows during data calculation, as shown in FIG. 24.

Referring to FIG. 24, when the compensation value is added to the pixel data, if there is data with a maximum value of 255 or more in the calculation result (S241, S242), the data is adjusted to "255" and the gray gap between the pixel data is adjusted. ) in order to keep it the same as the input image, the other pixel data are adjusted by adding 255-maximum value to each of the pixel data other than the maximum value in the overflow calculation process (S243). In Figure 24, "flash data" is the compensation value for each pixel block. “LUT data” is the weight.

As an example, as a result of adding a compensation value OFFSET=10 to 4x1 input R data (246, 252, 249, 250) within a pixel block, (246, 252, 249, 250) becomes (255, 255, 255, 255) ), the gray level difference between pixel data disappears and the gray level difference (original gray gap) of the input image cannot be expressed. In this case, the operation unit 32 adds +3 to the maximum value of 252 among the input R data (246, 252, 249, 250) in the overflow calculation process (S243) to adjust it to 255, and adds +3 to the remaining data instead of 10. By adding and adjusting to (249, 255, 252, 253), the difference in gradation of the input image is expressed. In the overflow calculation process, calculated values less than or equal to 0 are treated as 0 (S244, S245).

When the compensation value is added to the pixel data, if there is data with a minimum value of 0 or less in the calculation result (S246, S247), the data is adjusted to "0" and the gray gap between the pixel data is made the same as the input image. In order to maintain the underflow calculation process, other pixel data are adjusted as a result of adding the minimum value to each of the pixel data other than the minimum value (S248).

For example, as a result of adding -10 to 4x1 input R data (9, 5, 7, 4) within a pixel block, (9, 5, 7, 4) becomes (0, 0, 0, 0). The gray level difference between pixel data disappears, so the gray level difference of the input image cannot be expressed. In this case, the operation unit 32 adds -3 to the minimum value of 4 among the input R data (9, 5, 7, 4) in the underflow calculation process (S248) and adjusts it to 0, and adds -4 instead of -10 to the remaining data. By adding and adjusting to (5, 1, 3, 0), the difference in gradation of the input image is expressed.

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to what is described in the detailed description of the specification, but should be defined by the scope of the patent claims.

10: display panel 20: driver IC
21: timing control unit 22: data driver
30: first memory (flash memory) 31: second memory (SRAM)
32: Compensation unit 33: Register
81: Image quality improvement unit 82: Real/Pentile conversion unit

Claims (30)

A first memory storing a plurality of compensation values for each pixel block applied to the pixels in units of pixel blocks including M x N (M and N are each positive integers of 2 or more) pixels;
a second memory that receives compensation values for each of the plurality of pixel blocks from the first memory;
a compensation unit that modulates the data of an input image by adding a compensation value for each pixel block to the data; and
A data driver converts the compensated pixel data received from the compensation unit into a data voltage,
A plurality of pixel blocks are divided into a pixel array of a display panel having a resolution of
The compensation value for each pixel block applied to each of the pixel blocks is,
One first compensation value collectively applied to subpixels of the first color;
One or two second compensation values collectively applied to subpixels of a second color; and
Contains one third compensation value collectively applied to subpixels of the third color,
In each of the pixel blocks,
The first compensation value is added to the data to be written in the subpixels of the first color,
The second compensation value is added to the data to be written in the subpixels of the second color,
A real-time compensation circuit in which the third compensation value is added to data to be written in subpixels of the third color. According to claim 1,
A real-time compensation circuit in which the compensation value for each pixel block is set to a value that compensates for stains obtained through image capture of the display panel. According to claim 1,
The pixel block is
At least one first pixel including a subpixel of the first color and a subpixel of the second color; and
A real-time compensation circuit comprising at least one second pixel including a subpixel of the third color and a subpixel of the second color. According to claim 1,
The pixel block is
at least one first pixel including a subpixel of the first color, a subpixel of the second color, and a subpixel of the third color; and
A real-time compensation circuit comprising at least one second pixel including a subpixel of the first color, a subpixel of the second color, and a subpixel of the third color. According to claim 1,
Further provided with a real/pentile conversion unit,
The Real/Pentile conversion unit,
First real pixel data including the first color data, the second color data, and the third color data. First pentile pixel data including the first color data and the second color data. Convert to
Second real pixel data including the first color data, the second color data, and the third color data. Second pentile pixel data including the third color data and the second color data. Convert to
A real-time compensation circuit wherein the compensation unit applies the compensation value for each pixel block to each of the first and second PenTile pixel data received from the Real/Pentile conversion unit. delete According to claim 3,
The pixel block is
a left half sub-block including the first and second pixels located in the left half of the pixel block; and
A right half sub-block including the first and second pixels located in the right half of the pixel block,
The compensation value for each pixel block is,
a first compensation value collectively applied to subpixels of the first color;
a 2-1 compensation value collectively applied to subpixels of the second color existing in the left half subblock;
A 2-2 compensation value collectively applied to subpixels of the second color present in the right half subblock; and
A real-time compensation circuit including a third compensation value collectively applied to subpixels of the third color. A memory storing a plurality of pixel block-specific compensation values applied to the pixels in units of pixel blocks including M x N (where M and N are positive integers of 2 or more);
a compensation unit that modulates the data of an input image by adding a compensation value for each pixel block to the data; and
A data driver converts the compensated pixel data received from the compensation unit into a data voltage,
A plurality of pixel blocks are divided into a pixel array of a display panel having a resolution of
The compensation value for each pixel block applied to each of the pixel blocks is,
One first compensation value collectively applied to subpixels of the first color;
One or two second compensation values collectively applied to subpixels of a second color; and
Contains one third compensation value collectively applied to subpixels of the third color,
In each of the pixel blocks,
The first compensation value is added to the data to be written in the subpixels of the first color,
The second compensation value is added to the data to be written in the subpixels of the second color,
A real-time compensation circuit in which a third compensation value of a phase input imager is added to data to be written in the subpixels of the third color. a display panel on which data lines, gate lines crossing the data lines, and pixels are arranged;
A first memory storing a plurality of compensation values for each pixel block applied to the pixels in units of pixel blocks including M x N (M and N are each positive integers of 2 or more) pixels; and
A drive integrated circuit generates compensated pixel data by adding compensation values for each pixel block read from the first memory to data of the input image, converts the compensated pixel data into a data voltage, and applies it to the data lines. do,
A plurality of pixel blocks are divided into a pixel array of a display panel having a resolution of
The compensation value for each pixel block applied to each of the pixel blocks is,
One first compensation value collectively applied to subpixels of the first color;
One or two second compensation values collectively applied to subpixels of a second color; and
Contains one third compensation value collectively applied to subpixels of the third color,
In each of the pixel blocks,
The first compensation value is added to the data to be written in the subpixels of the first color,
The second compensation value is added to the data to be written in the subpixels of the second color,
An electroluminescent display device in which the third compensation value is added to data to be written in subpixels of the third color. According to clause 9,
The drive integrated circuit,
a second memory that loads the compensation value for each pixel block from the first memory; and
An electroluminescent display device comprising a compensation unit that adds the compensation value for each pixel block to data of the input image and outputs the compensated pixel data. According to claim 10,
The data size stored in the first memory is (X/M)x(Y/N) x compensation value data size + checksum data size,
An electroluminescent display device in which the data size stored in the second memory is (X/M)x(Y/N)xcompensation value data size. According to clause 9,
An electroluminescent display device in which the compensation value for each pixel block is applied only to on-pixels among all pixels of the display panel when the display panel operates in a partial mode. According to claim 10,
The compensation department
An electroluminescent display device that adds the result of adding weight to the compensation value for each pixel block to data of the input image. According to claim 13,
The compensation department
An electroluminescence display device comprising one or more lookup tables where the weight is individually set according to a luminance value received from a host system and a grayscale value of data of the input image. According to claim 14,
The compensation department,
The result of adding weight to the compensation value for each pixel block is added to the data of the input image,
An electroluminescence display device that adds a relatively large weight among weights to the compensation value for each pixel block when the display panel is driven in HBM (high brightness mode) mode. According to clause 9,
An electroluminescent display device, wherein each of the pixels includes a compensation circuit that samples the threshold voltage of a driving element for driving the light-emitting element and adds the threshold voltage to the data voltage of the pixel data. delete delete delete delete delete delete delete delete delete delete delete delete delete delete