KR102593330B1 - Thin Film Transistor Substrate For Display Device - Google Patents

Abstract

The present invention relates to a thin film transistor substrate for a display device having a plastic substrate. The thin film transistor substrate for a display device according to the present invention includes a base layer, a first buffer layer, an electric field shielding layer, a second buffer layer, a first semiconductor layer, and a second semiconductor layer. The first buffer layer is applied over the entire surface of the base layer. The electric field shielding layer is applied over the entire surface of the first buffer layer. A second buffer layer is applied over the entire surface of the electric field shielding layer. The first semiconductor layer is disposed over the second buffer layer. The second semiconductor layer is disposed over the second buffer layer. The first semiconductor layer has a larger band gap than the second semiconductor layer.

Description

Thin film transistor substrate for display device {Thin Film Transistor Substrate For Display Device}

The present invention relates to a thin film transistor substrate for a display device having a plastic substrate. In particular, the present invention relates to a thin film transistor substrate for a display device having a structure capable of shielding parasitic electric fields generated from a plastic substrate.

The display device field has been rapidly changing toward thin, light, large-area flat panel displays (FPDs) replacing bulky cathode ray tubes (CRTs). Flat panel displays include liquid crystal display devices (LCD), organic light emitting display devices (OLED), and electrophoretic display devices (ED).

In the case of actively driven liquid crystal displays, organic light emitting displays, and electrophoresis displays, they include a thin film transistor substrate on which allocated thin film transistors are disposed in pixel areas arranged in a matrix manner. Liquid crystal display devices (LCDs) display images by controlling the light transmittance of liquid crystals using an electric field. Organic light emitting display devices display images by forming organic light emitting elements in pixels arranged in a matrix manner.

In particular, electroluminescent display devices such as organic light emitting diode displays provide excellent image quality by using self-luminous elements. In addition, there are various fields of application, such as development into flexible display devices.

Display device technology to date has developed around technology for forming display elements on glass substrates. Therefore, in order to develop various display devices such as flexible display devices, the structure and physical properties of the product must be newly developed to suit the intended environment. For example, if the structure of a thin film transistor substrate for a display device based on a glass substrate is applied to a flexible display device, display quality or device lifespan cannot be guaranteed due to unexpected problems.

The purpose of the present invention is to overcome the above problems and to provide a display device with high mobility characteristics and/or low power consumption characteristics. Another object of the present invention is to provide a display device having a structure that can shield the channel characteristics of a semiconductor layer with high mobility characteristics from external parasitic electric fields.

To achieve the above object, the thin film transistor substrate for a display device according to the present invention includes a base layer, a first buffer layer, an electric field shielding layer, a second buffer layer, a first semiconductor layer, and a second semiconductor layer. The first buffer layer is applied over the entire surface of the base layer. The electric field shielding layer is applied over the entire surface of the first buffer layer. A second buffer layer is applied over the entire surface of the electric field shielding layer. The first semiconductor layer is disposed over the second buffer layer. The second semiconductor layer is disposed over the second buffer layer. The first semiconductor layer has a larger band gap than the second semiconductor layer.

For example, the thin film transistor substrate for a display device further includes a gate insulating film, a scan line, a gate electrode, an intermediate insulating film, a data line, a source electrode, a drain electrode, a planarization film, and a pixel electrode. The gate insulating film covers the second semiconductor layer. The scan wiring is arranged in the first direction of the base layer over the gate insulating film. The gate electrode branches off from the scan wiring on the gate insulating film and overlaps the central part of the second semiconductor layer. The intermediate insulating film covers the scan wiring and gate electrode. The data wires are arranged in the second direction of the base layer over the intermediate insulating film. The source electrode branches off from the data line over the intermediate insulating film and contacts one side of the second semiconductor layer. The drain electrode contacts the other side of the second semiconductor layer over the intermediate insulating film. The planarization film covers the source electrode and drain electrode. The pixel electrode is in contact with the drain electrode on the planarization film.

In one example, the electric field shielding layer includes a semiconductor material having a band gap greater than or equal to that of the first semiconductor layer.

In one example, the first semiconductor layer has a maximum thickness of half the thickness of the second semiconductor layer.

In one example, the electric field shielding layer has the same thickness as the first semiconductor layer.

In one example, the first semiconductor layer includes an amorphous silicon material. The second semiconductor layer includes a polycrystalline semiconductor material.

In one example, the electric field shielding layer and the first semiconductor layer include an amorphous silicon material.

The present invention provides a display device having a parasitic electric field shielding structure under a semiconductor layer to prevent back channel bias caused by an external parasitic electric field. In particular, the semiconductor layer to be used as a channel is formed of a material with a small band gap to ensure high mobility characteristics. The shielding semiconductor layer to prevent parasitic electric fields is formed at the bottom of the semiconductor layer using a semiconductor material with a larger band gap than the channel semiconductor layer. As a result, the characteristics of the semiconductor layer with high mobility characteristics can be protected from parasitic electric fields induced in the plastic substrate of the display device. Therefore, the display device according to the present invention can ensure excellent image quality while maintaining high mobility characteristics even when used for a long time.

1 is a plan view showing the structure of an organic light emitting diode display device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along line II' in FIG. 1, showing the structure of the organic light emitting diode display device according to the first embodiment.
Figure 3 is a cross-sectional view showing the effect of a parasitic electric field on an organic light-emitting diode display device according to the first embodiment of the present invention.
Figure 4 is a cross-sectional view showing the structure of an organic light emitting diode display device having a parasitic electric field shielding structure according to a second embodiment of the present invention.
Figure 5 is a cross-sectional view showing the structure of an organic light emitting diode display device having a parasitic electric field shielding structure according to a third embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. The present invention is not limited to the embodiments disclosed below and may be implemented in various forms. These embodiments are provided to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the present invention of the scope of the invention.

The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining embodiments of the present invention are illustrative, and the present invention is not limited to the matters shown. Like reference numerals refer to like elements throughout the specification.

In describing the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When 'includes', 'has', 'consists of', etc. mentioned in the specification are used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, the plural is included unless specifically stated otherwise.

When interpreting a component, it is interpreted to include the margin of error even if there is no separate explicit description. In the case of a description of a positional relationship, for example, if the positional relationship between two parts is described as 'on top', 'on top', 'at the bottom', 'next to ~', 'right next to' Alternatively, there may be one or more other components placed between the two parts, unless 'directly' is used.

In the description of the embodiments, 'first', 'second', etc. are used to describe various components, but the components are not limited by these terms. These terms are merely used to distinguish one component from another. Additionally, the component names used in the following description may have been selected in consideration of ease of specification preparation, and may be different from the component names of the actual product.

Each feature of various embodiments of the present invention can be partially or fully combined or combined with each other, and various technological interconnections and operations are possible. Additionally, each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. In the following embodiments, the description will focus on an organic light emitting display device including an organic light emitting material. However, it should be noted that the technical idea of the present invention is not limited to organic light emitting display devices, but can also be applied to inorganic light emitting display devices including inorganic light emitting materials.

<First embodiment>

Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. 1 is a plan view showing the structure of an organic light emitting diode display device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II' in FIG. 1, showing the structure of the organic light emitting diode display device according to the first embodiment.

The organic light emitting diode display device according to the first embodiment of the present invention includes a scan line (SL) running in a first direction (or horizontal direction) and data running in a second direction (or vertical direction) on a flexible substrate. It is provided with a wiring (DL) and a driving current wiring (VDD). The flexible substrate includes a barrier film (BF) and a base layer (PI). The base layer (PI) is laminated on a rigid substrate (not shown), forms devices, and then separated from the rigid substrate. The base layer (PI) preferably includes a plastic material such as polyimide. After separating the base layer (PI) on which the devices are formed from the rigid substrate, a barrier film (BF) is attached.

The pixel area is defined by a structure in which scan lines (SL), data lines (DL), and driving current lines (VDD) intersect. Thin film transistors (ST, DT) and organic light emitting diodes (OLE) are disposed in the pixel area. A switching thin film transistor (DT) is disposed at the intersection of the scan line (SL) and the data line (DL). A driving thin film transistor (DT) is disposed between the switching thin film transistor (ST) and the driving current line (VDD). An organic light emitting diode (OLE) connected to a driving thin film transistor (DT) is disposed in the pixel area.

The switching thin film transistor (ST) includes a switching gate electrode (SG), a switching semiconductor layer (SA), a switching source electrode (SS), and a switching drain electrode (SD). The driving thin film transistor (DT) includes a driving gate electrode (SG), a driving semiconductor layer (DA), a driving source electrode (DS), and a driving drain electrode (DD). An organic light emitting diode (OLE) includes an anode electrode (ANO), an organic light emitting layer (OL), and a cathode electrode (CAT).

The switching drain electrode (SD) of the switching thin film transistor (ST) is connected to the driving gate electrode (DG) of the driving thin film transistor (DT) through the gate contact hole (GH). The driving drain electrode (DD) of the driving thin film transistor (DT) is connected to the anode electrode (ANO) of the organic light emitting diode (OLE) through the pixel contact hole (PH).

Looking at the cross-sectional structure, a buffer layer (BUF) is stacked on the entire surface of the base layer (PI). A switching semiconductor layer (SA) and a driving semiconductor layer (DA) are formed on the buffer layer (BUF). A gate insulating film (GI) is stacked on these semiconductor layers (SA, DA). A gate element is formed on the gate insulating film (GI). The gate element includes a scan line (SL), a switching gate electrode (SG), and a driving gate electrode (DG). An intermediate dielectric layer (ILD) is deposited on the gate element. A source-drain element is formed on the intermediate insulating layer (ILD). The source-drain elements include a data line (DL), a driving current line (VDD), a switching source electrode (SS), a switching drain electrode (SD), a driving source electrode (DS), and a driving drain electrode (DD).

The central portion of the semiconductor layers (SA, DA) overlaps the gate electrodes (SG, DG) with the gate insulating film (GI) interposed therebetween. This overlapping area is the channel area. One side of the semiconductor layer (SA, DA) is in contact with the source electrodes (SS, DS), and the other side is in contact with the drain electrodes (SD, DD).

A planarization film (OC) is stacked on the thin film transistors (ST, DT) to cover the entire surface of the base layer (PI). A pixel contact hole (PH) exposing the driving drain electrode (DD) is formed in the planarization film (OC). An anode electrode (ANO) is formed on the planarization film (OC) and connected to the driving drain electrode (DD) through the pixel contact hole (PH). A bank (BN) is formed on the anode electrode (ANO). The bank BN has an opening area that exposes most of the anode electrode ANO. An organic light emitting layer (OL) and a cathode electrode (CAT) are sequentially stacked on the base layer (PI) on which the bank (BN) is formed. In the opening area, an anode electrode (ANO), an organic light emitting layer (OL), and a cathode electrode (CAT) are stacked to form an organic light emitting diode (OLE). This opening area becomes a light emitting area.

Additionally, a portion of the anode electrode (ANO) overlaps with the driving gate electrode (DG) to form a storage capacitance (STG). In addition to these structures, auxiliary capacity (STG) can be formed in various structures.

The display device according to the present invention is applied to a wearable display device. Therefore, it is desirable to use a device that is advantageous for high-speed operation and low power consumption. In particular, polycrystalline silicon materials show many advantages in display devices. When implementing a thin film transistor with a semiconductor layer containing polycrystalline silicon, a top gate structure as shown in FIG. 2 is advantageous.

When the top-gate structure is applied to a display device with a glass substrate structure rather than a display device, the special advantages of polycrystalline silicon can be secured without any major problems. However, in the case of display devices, especially under ultra-high resolution conditions of Full High Density (Full High Density) level or higher, the base layer (PI) and barrier film (BF) may cause disturbances due to parasitic electric fields in the semiconductor layer.

Hereinafter, with reference to FIG. 3, problems with parasitic electric fields that may occur in a display device will be described. Figure 3 is a cross-sectional view showing the effect of a parasitic electric field on the organic light emitting diode display device according to the first embodiment of the present invention.

In Figure 3, for convenience, only the thin film transistor (T) is shown and only the base layer (PI) is shown. The thin film transistor (T) includes a switching thin film transistor (ST) and a driving thin film transistor (DT). Referring to FIG. 3, a buffer layer (BUF) is stacked on the base layer (PI). A semiconductor layer (A) containing polycrystalline silicon is formed on the buffer layer (BUF). A gate insulating film (GI) is stacked on the semiconductor layer (A). A scan line (SL) and a gate electrode (G) are formed on the gate insulating film (GI).

The gate electrode (G) functions to turn the channel on and off by providing an electric field to the semiconductor layer (A). The gate electrode G is branched from the scan wiring SL, and the scan wiring SL is disposed adjacent to the semiconductor layer A. The gate electrode (G) receives a gate signal through the scan line (SL). Accordingly, when a gate signal is transmitted to the gate electrode (G) to operate the channel, the same gate signal is also applied to the scan line (SL).

The gate signal of the scan line SL may provide an electric field to the adjacent semiconductor layer A through the base layer PI located below the buffer layer BUF. That is, the parasitic electric field (E-field) generated from the scan line (SL) affects the backside of the semiconductor layer (A) through the base layer (PI). This is called back channel bias. Due to back channel bias, a problem may occur in which the semiconductor layer (A) does not operate normally.

In particular, when the base layer (PI) is formed with a plastic material such as polyimide, parasitic electric fields can be more easily induced/generated due to the dipole structure of polyimide. Below, we propose structures with additional components that solve the back channel bias problem that may occur in the first embodiment of the present invention.

<Second Embodiment>

Referring to Figure 4, a second embodiment of the present invention will be described. Figure 4 is a cross-sectional view showing the structure of an organic light emitting diode display device having a parasitic electric field shielding structure according to a second embodiment of the present invention. FIG. 4 is a diagram for comparison with FIG. 3, and for convenience, only the thin film transistor (T) and the base layer (PI) are shown.

The organic light emitting diode display device having a parasitic electric field shielding structure according to the second embodiment of the present invention includes a thin film transistor (T) disposed on the base layer (PI). Looking at the cross-sectional structure, a buffer layer (BUF) is stacked on the entire surface of the base layer (PI). A semiconductor layer (A) is formed on the buffer layer (BUF).

The semiconductor layer (A) has a structure in which a first semiconductor layer (AM) and a second semiconductor layer (LT) are sequentially stacked. In particular, the first semiconductor layer (AM) is formed of amorphous silicon, and the second semiconductor layer (LT) is formed of polycrystalline silicon. It has a larger band gap than the first semiconductor layer (AM) including amorphous silicon and the second semiconductor layer (LT) including polycrystalline silicon. That is, the first semiconductor layer LT, which has high mobility characteristics and will be used as a channel region, is formed of a material with a small band gap. On the other hand, a material with a large band gap is stacked on the bottom of the first semiconductor layer LT to shield the parasitic electric field.

In order to maintain high mobility characteristics in the semiconductor layer (A), the first semiconductor layer (AM) must be formed so as not to have any influence other than protecting the second semiconductor layer (LT) including a polycrystalline semiconductor material. For this purpose, the first semiconductor layer (AM) preferably has a thickness of 1/2 or less than the thickness of the second semiconductor layer (LT). If the thickness of the first semiconductor layer (AM) is too thick, it may affect the band gap of the second semiconductor layer (LT), thereby impeding high mobility characteristics.

The semiconductor layer (A) has a structure in which materials having different band gaps are joined. Therefore, by forming an electric field inside the semiconductor layer (A), it is possible to obtain the effect of canceling out the parasitic electric field caused by charge movement or dipole rearrangement inside the base layer (PI) containing polyimide. By disposing amorphous silicon with a large band gap on the lower surface of the second semiconductor layer LT in the direction in which the influence of the back channel is transmitted, charge movement into the channel region can be blocked. That is, due to the low mobility characteristics of amorphous silicon, it is possible to prevent excessive charges from moving into the channel region, resulting in excessive channel on-off characteristics. Additionally, since there is no need to form a separate shielding layer, there is no problem of increasing the number of mask processes.

In this way, the semiconductor layer (A) has a structure in which the first semiconductor layer (AM) for shielding parasitic electric fields is stacked on the lower part of the second semiconductor layer (LT) to be used as a channel, so that the second semiconductor layer (LT) Characteristics can be prevented from being changed by parasitic electric fields. The structure according to the second embodiment shows better shielding performance than when the buffer layer (BUF) is applied as a multi-layer in the structure of FIG. 3.

<Third Embodiment>

Hereinafter, a third embodiment of the present invention will be described with reference to FIG. 5. Figure 5 is a cross-sectional view showing the structure of an organic light emitting diode display device having a parasitic electric field shielding structure according to a third embodiment of the present invention.

An organic light emitting diode display device having a parasitic electric field shielding structure according to a third embodiment of the present invention includes a thin film transistor (T) disposed on a base layer (PI). Looking at the cross-sectional structure, the first buffer layer (B1) is stacked on the entire surface of the base layer (PI). An electric field shielding layer (EFS) is laminated on the entire surface of the first buffer layer (B1). A second buffer layer (B2) is laminated on the entire surface of the electric field shielding layer (EFS).

The electric field shielding layer (EFS) is used to shield the electric field generated from the scan wiring (SL) disposed around the semiconductor layer (A) from influencing the back side of the semiconductor layer (A). Therefore, it is preferable to form the semiconductor layer (A) of a semiconductor material with a larger band gap than the channel material. For example, when the semiconductor layer A is formed of a polycrystalline silicon material with high mobility characteristics, the electric field shielding layer (EFS) can be formed of amorphous silicon, which has a larger band gap than polycrystalline silicon. However, it is not limited to amorphous silicon, and semiconductor materials with a larger band gap than the semiconductor layer (A) can be selected. In order to apply it over the entire base layer (PI) and ensure high transparency so as not to affect the display function, when forming a semiconductor layer with polycrystalline silicon having high mobility characteristics, it is preferable to use amorphous silicon.

A semiconductor layer (A) is formed on the second buffer layer (B2). The semiconductor layer (A) has a structure in which a first semiconductor layer (AM) and a second semiconductor layer (LT) are sequentially stacked. In particular, the first semiconductor layer (AM) is formed of amorphous silicon, and the second semiconductor layer (LT) is formed of polycrystalline silicon. It has a larger band gap than the first semiconductor layer (AM) including amorphous silicon and the second semiconductor layer (LT) including polycrystalline silicon. That is, the first semiconductor layer LT, which has high mobility characteristics and will be used as a channel region, is formed of a material with a small band gap. On the other hand, a material with a large band gap is stacked on the bottom of the first semiconductor layer LT to more completely shield the parasitic electric field.

In this way, the electric field shielding layer (EFS) is disposed below the semiconductor layer (A), and the semiconductor layer (A) has a first semiconductor layer (AM) for shielding parasitic electric fields below the second semiconductor layer (LT) to be used as a channel. By having a stacked structure, it is possible to prevent the characteristics of the second semiconductor layer LT from being changed by a parasitic electric field. The structure according to the third embodiment shows better shielding performance than that of the second embodiment.

The third embodiment, which further includes an electric field shielding layer (EFS), may have a slightly more complicated manufacturing process than the second embodiment. However, since the electric field shielding layer (EFS) is formed to cover the entire surface of the base layer (PI), a separate patterning process is not required. Since it covers the entire surface of the base layer (PI), it is preferable to have a thin thickness in order to avoid interfering with the display function. For example, the electric field shielding layer (EFS) preferably has the same thickness as the first semiconductor layer (AM). That is, it is preferable that the electric field shielding layer (EFS) and the first semiconductor layer (AM) have a maximum thickness of 1/2 the thickness of the second semiconductor layer (LT).

Through the above-described content, those skilled in the art will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the present invention should not be limited to what is described in the detailed description, but should be defined by the scope of the patent claims.

PI: Base layer BF: Barrier film
BUF: buffer layer EFS: electric field shielding layer
A: semiconductor layer AM: first semiconductor layer
LT: second semiconductor layer GI: gate insulating film
SL: Scan wiring G: Gate electrode
ILD: Intermediate insulation layer DL: Data wiring
S: source electrode D: drain electrode

Claims (7)

basal layer;
a first buffer layer applied over the entire surface of the base layer;
an electric field shielding layer applied over the entire surface of the first buffer layer;
a second buffer layer applied over the entire surface of the electric field shielding layer; and
comprising a semiconductor layer disposed on the second buffer layer,
The semiconductor layer includes: a first semiconductor layer on the second buffer layer; and
A second semiconductor layer disposed on the first semiconductor layer,
The first semiconductor layer has a larger band gap than the second semiconductor layer,
The electric field shielding layer is a thin film transistor substrate for a display device including a semiconductor material having a band gap greater than or equal to that of the first semiconductor layer.

delete delete According to claim 1,
The first semiconductor layer is,
A thin film transistor substrate for a display device whose maximum thickness is 1/2 of the thickness of the second semiconductor layer.
According to claim 1,
The electric field shielding layer is,
A thin film transistor substrate for a display device having the same thickness as the first semiconductor layer.
According to claim 1,
The first semiconductor layer includes an amorphous silicon material,
The second semiconductor layer is a thin film transistor substrate for a display device including a polycrystalline silicon material.
According to claim 1,
The electric field shielding layer and the first semiconductor layer include a thin film transistor substrate for a display device including an amorphous silicon material.

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