KR102565238B1 - Address mapping apparatus and method considering shared memory and cache interleaving - Google Patents

Abstract

The present invention relates to an address mapping apparatus and method, comprising the steps of: a) creating a linear address map for n caches, which are positive integers; b) exchanging addresses of each of the n caches according to a rule; The method may include converting the address map so that caches designated by addresses of different columns adjacent to each other in the same row are disposed differently.

Description

Address mapping apparatus and method considering shared memory and cache interleaving

The present invention relates to an address mapping apparatus and method considering shared memory and cache interleaving, and more particularly, to an address mapping apparatus and method capable of reducing image processing time by interleaving images in a plurality of cache memories.

Recently, the use of portable information devices or computing devices such as smart phones, smart pads, laptops, and tablet PCs has increased, and shooting and sharing of images or videos using portable information devices has become common.

The performance of portable information devices experienced by users is an important criterion for displaying images and how quickly edited images can be displayed on the screen.

In particular, as the capacity of a single image continues to increase due to the high quality of images taken using portable information devices, optimized address mapping of memory has become an important issue even when the same hardware is used.

Regarding address mapping, Patent Publication No. 2013-0122417 (Address Generator of Image Processing Apparatus and Operation Method of Address Generator) describes a technical configuration for mapping an image to a plurality of memories, but data is stored in slave memories such as DRAM. There is a limit to improving the speed of image processing by distributing and storing , and calling and displaying partial pixel data of the same image stored in respective memories in an image processor.

FIG. 1 is a block diagram of an image processing unit using a plurality of caches for image processing, and FIG. 2 is an exemplary diagram of conventional cache address mapping.

The image processing unit 1 may perform processing of reading or writing data for image processing on specific coordinates of the image coordinate system of the image, and transfers address information and transactions to the cache and the image processing unit through a set address map. (1) is provided to interconnect 2, and interconnect 2 identifies and accesses cache addresses corresponding to addresses requested in the cache maps of the first through fourth caches C0, C1, C2, and C3. .

An example of the cache map of the interconnect 2 is shown in FIG. 2 .

In FIG. 2, C0, C1, C2, and C3 denote first to fourth caches, respectively, and the original letter numerals are assigned transaction numbers for convenience of description. It does not indicate the order of numeric original character transactions, and is intended to indicate which address of which cache, among the first to fourth caches C0, C1, C2, and C3, the image processing unit 1 requested a transaction. can be understood

A sequence of numbers such as 000 and 0040 is hexadecimal data that is an address of a memory.

In the above example, the cache map is a linear address map, and means that pixel data of an image is sequentially stored in the first to fourth caches C0, C1, C2, and C3 in a column direction.

That is, adjacent transaction numbers are sequentially and linearly arranged in different caches.

In this state, when transactions of the image processing unit 1 sequentially specify addresses in the vertical direction on the drawing, only the first cache C0 is used and the second to fourth caches are not used.

For example, when the data designated by the transaction is designated in the order of the original numbers 0, 8, 16, and 24, traffic occurs only in the first cache C0 that stores the data, and the second to fourth caches ( C1, C2, and C3) are not used at all, which causes a relatively slow image processing speed.

In the portable information device that performs image processing, the image processing unit 1, the scaler or rotator responsible for resizing or rotating images, and the display controller displaying images on the display operate as masters sharing a cache, so that the above The delay in image processing is further intensified.

In view of the above problems, an object to be solved by the present invention is to provide a cache address mapping method capable of solving a phenomenon in which transactions are concentrated in one cache in the conventional linear address mapping.

Another object of the present invention is to provide an apparatus capable of appropriately performing the cache address mapping method of the present invention in a system environment in which a plurality of master units share a memory.

An address mapping method according to an aspect of the present invention for solving the above technical problem includes the steps of a) creating a linear address map for n caches that are positive integers, and b) each of the n caches according to a rule. The method may include converting the address map so that addresses are mutually exchanged, but caches designated by addresses of different columns located vertically and adjacently in the same row of the address map are differently disposed.

In an embodiment of the present invention, in step b), addresses of different caches may be interchanged or a specific column of the linear address map may be shifted in a direction in which rows decrease or increases.

In an embodiment of the present invention, addresses of different caches may be exchanged for each column of the linear address map.

In an embodiment of the present invention, the linear address map may shift to a different degree for each column of the linear address map.

In an embodiment of the present invention, the interchange of addresses or the shift of addresses may be performed from the second column except for the first column.

In an embodiment of the present invention, address interchange or address shift is performed for n columns including the first column, and the same is repeatedly applied to subsequent columns, so that the n+1 column corresponds to the first column. Likewise, exchanges or shifts may not be made.

Further, an address mapping apparatus according to another aspect of the present invention includes a linear address calculation unit that calculates a linear address in order to map image coordinates to a cache, and receives a calculation result of the linear address calculation unit and performs one of the above methods. It may include an address conversion unit that changes an address according to a rule of a method, and a multiplexer that selects and outputs an address of the linear address calculation unit or the address conversion unit.

The present invention proposes a new method of exchanging cache addresses by determining rules in a linear address mapping state, and has an effect of preventing traffic from being concentrated in one cache regardless of a direction specified by a transaction.

The present invention provides an address mapping device capable of matching the address mapping information of each master in a state in which a plurality of master units share a memory, so that even if some of the plurality of master units have only linear address mapping information, cache time Since an address exchange method can be applied, it is possible to prevent traffic from being concentrated in one cache regardless of the direction specified by a transaction, thereby preventing image processing speed deterioration.

1 is a block diagram of a conventional image processing unit including a plurality of caches.
2 is an exemplary view of a conventional cache address map, which is an example of linear address mapping.
3 is an exemplary view of an address map created by the address mapping method of the present invention.
4 is an exemplary diagram of a shift method.
5 is an exemplary diagram of the cache address exchange of the present invention.
6 is an exemplary view of a system to which an address mapping device to which the present invention is applied is applied.
7 is an exemplary diagram of a hardware configuration that converts LIAM to CIAM or maintains LIAM according to conditions.

In order to fully understand the configuration and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various forms and various changes may be made. However, the description of the present embodiment is provided to complete the disclosure of the present invention and to completely inform those skilled in the art of the scope of the invention to which the present invention belongs. In the accompanying drawings, the size of the components is enlarged from the actual size for convenience of description, and the ratio of each component may be exaggerated or reduced.

Terms such as 'first' and 'second' may be used to describe various elements, but the elements should not be limited by the above terms. The above terms may only be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a 'first element' may be named a 'second element', and similarly, a 'second element' may also be named a 'first element'. can Also, singular expressions include plural expressions unless the context clearly indicates otherwise. Terms used in the embodiments of the present invention may be interpreted as meanings commonly known to those skilled in the art unless otherwise defined.

Hereinafter, an address mapping apparatus and method according to an embodiment of the present invention will be described with reference to the drawings.

3 is a block diagram of a cache address map created by an address mapping method according to a preferred embodiment of the present invention.

Referring to FIG. 3, in the present invention, cached address exchange is performed in linear address mapping according to a specific rule.

2 described above is a linear address mapped cache address map, and the map of FIG. 3 shows a state in which transactions 8 and 9 denoted by original numbers are exchanged with each other and transactions 10 and 11 are exchanged with each other.

Also, it can be seen that transactions 16 and 18 and 17 and 19 are exchanged.

The example of FIG. 3 is an example when the first to fourth caches C0, C1, C2, and C3 are used, and rules applied according to the number of caches may be varied and applied.

A more detailed look at these exchange rules is as follows.

First, FIG. 3 shows a matrix-type cache address map having 8 rows (COL) and 32 columns (ROW), and the 8 rows are 2 from the first cache (C0) to the fourth cache (C3). An address designated repeatedly is described. This arrangement is an example of addressing image data of 128 pixels in one row.

In FIG. 3, the first column (ROW 0) has the same arrangement as the linear address map, the second column (ROW 1) exchanges the address arrangements of the first cache C0 and the second cache C1, and the third Address arrangements of the cache C2 and the fourth cache C3 are interchanged.

Further, in the third column ROW 2 , the addresses of the first cache C0 and the third cache C2 are exchanged, and the addresses of the second cache C1 and the fourth cache C3 are exchanged.

In the fourth column ROW 3 , the addresses of the first cache CO and the fourth cache C3 and the second cache C1 and the third cache C2 are interchanged.

Accordingly, even if consecutive transactions occur in the vertical direction (column direction) in the same row in the cache address map, traffic concentration in one cache can be prevented.

For example, even if transactions 0, 9, 18, and 27 occur sequentially, traffic is sequentially generated in the first cache (C0), the second cache (C1), the third cache (C2), and the fourth cache (C3). Therefore, it is possible to prevent a decrease in processing speed due to concentration of traffic.

Generalizing this, it can be defined as: In a system with n caches, different cache addresses are exchanged for columns other than the first column of the linear address map, but caches designated by adjacent columns in the same row of each column are arranged differently. .

That is, in the example of FIG. 3, the address exchange method of the fourth column (ROW3) exchanges the addresses of the first cache (CO) and the fourth cache (C3), and exchanges the addresses of the second cache (C1) and the third cache (C2). , but as shown in the second column, the address arrangements of the first cache (C0) and the second cache (C1) are exchanged, and the address arrangements of the third cache (C2) and the fourth cache (C3) are mutually exchanged. can also be exchanged.

At this time, traffic is generated in the order of the first cache (C0), the second cache (C1), the third cache (C2), and then the second cache (C1) due to transactions that occur consecutively in the column direction of the same row. Compared to the example described above, processing speed may be reduced, but traffic may be prevented from being concentrated in one cache compared to the linear address map.

Also, in the example of FIG. 3, it has been described that addresses of different caches are mutually exchanged according to a rule, but a shift method may be used in a corresponding column.

4 is an exemplary diagram of a shift method.

Referring to FIG. 4, as another example of the cache address mapping method of the present invention, in the linear address map, the first column is the same as in the linear address map, and the address is shifted with a different shift value for each column from the second address map to a specific row. Even when a transaction in the vertical direction occurs, traffic concentration on a specific cache can be prevented.

For example, the second column (ROW 1) indicates a state in which the address is shifted by 1 in a decreasing row number direction, and the third column (ROW 2) indicates a state in which an address is shifted by 2 in a decreasing row number direction.

The fourth column (ROW 3) is also a state in which the address is shifted by 3 in the direction of decreasing row numbers.

Although not shown in the figure, as described above, the example of the present invention uses four caches, the first to fourth caches (C0, C1, C2, C3), the fifth column (ROW4 is the first column (ROW 0) ), the linear address map is used as it is, and the sixth column (ROW 5) can be processed identically to the second column (ROW 1).

Such a shift method may be performed in a direction in which row numbers increase instead of in a direction in which row numbers decrease, and a shift degree may be applied differently for each column as necessary.

Even if the shift method is used, it is assumed that at least the addresses of adjacent positions among the addresses of each column belonging to the same row are addresses of different caches.

In the example of FIG. 4 , even if consecutive transactions occur in the column direction in the second row (COL 1), the caches used are the second cache C1, the third cache C2, the fourth cache C3, and the first cache. In the order of (C0), traffic concentration in one cache can be prevented.

As such, the present invention can prevent traffic from being concentrated in one cache by exchanging cache addresses even when consecutive transactions occur in the column direction in the linear address map.

5 is an exemplary diagram of the cache address exchange of the present invention.

Referring to FIG. 5, the address of the cache linear address map (LIAM) has tag, index, cache, and offset values, and the address of the second cache C1 corresponding to transaction 9 in FIGS. 3 and 4 is the first. It shows the process of exchanging with the address of the cache (C0).

The physical address of the memory corresponding to the transaction 9 is 0X240, which means exchange with the address of the first cache C0 in the cache 01 representing the second cache C1. This is the same as the example of FIG. 3 .

In FIG. 5, the CIAM address represents a cache interleaved address map proposed and named in the present invention. Flip means to change the cache.

As described above, the present invention compensates for the disadvantages of the conventional linear address map (LIAM) and prevents traffic from being concentrated in a specific cache even when continuous transactions in a specific direction occur.

The above example is an example of using one master unit (image processing unit) as shown in FIG. 1, and in order to apply the present invention to a general system in which a plurality of master units share memory, LIAM and the present invention Technical means to interconvert CIAM are required.

6 is an exemplary view of a system to which an address mapping device to which the present invention is applied is applied.

As shown in FIG. 6, the present invention can be applied to a system including multiple masters.

Examples of multiple masters may include an image processor 10, an editor 20 including a scaler or rotator, and a display controller 30, respectively.

The image processor 10, the editor 20, and the controller 30 each use a linear address map (LIAM), which is an existing cache address mapping method, and LIAM and CIAM proposed in the present invention are mutually used in each address map. It is assumed that a technical means capable of conversion is added.

The address map 11 of the image processor 10 includes the CIAM converter 12, and the CIAM converter 12 can be used for mapping using LIAM or CIAM.

In FIG. 6, the image processor 10 generates a transaction for writing to a specific address of the shared memory 40 in the CIAM method, and the address map 21 of the editor 20 that reads the transaction is read in the CIAM method (22), A write transaction 23 may be generated in the LIAM method so that mapping is possible in the address map 31 of the display controller 30 that performs only the read 32 transaction in the LIAM method.

As such, when a plurality of masters share the shared memory 40, the present invention can perform communication between the masters while appropriately changing the LIAM method and the CIAM method.

Technical means for changing the LIAM and CIAM may be hardware or software.

CIAM performs mutual exchange or shift of addresses according to predetermined rules in LIAM, and any configuration that can apply these rules as needed is applicable to the present invention.

7 is an exemplary diagram of a hardware configuration that converts LIAM to CIAM or maintains LIAM according to conditions.

Referring to FIG. 7 , an address calculator 100 that converts coordinates of an image into a LIAM address and a CIAM address converter that interchanges or shifts some of the linear addresses of the LIAM address calculator 100 according to given conditions ( 200) and a multiplexer 300 that selects an address of the LIAM address calculation unit 100 or the CIAM address conversion unit 200 according to input conditions.

With this configuration, the present invention can quickly convert LIAM to CIAM, and address mapping according to a set rule is possible without slowing down.

Embodiments according to the present invention have been described above, but these are merely examples, and those skilled in the art will understand that various modifications and embodiments of equivalent range are possible therefrom. Therefore, the true technical protection scope of the present invention should be defined by the following claims.

10: image processor 20: editor
30: display controller

Claims (7)

In the address mapping method performed in the image processor,
a) creating linear address maps for n caches which are positive integers; and
b) exchanging the addresses of each of the n caches according to a rule, but converting the address map so that caches designated by addresses of different columns located vertically and adjacently in the same row of the address map are disposed differently from each other; mapping method. According to claim 1,
In step b),
exchange addresses of different caches, or
and shifting a specific column of the linear address map in a direction in which rows decrease or in a direction in which rows increase. According to claim 2,
The mutual exchange of addresses is
and exchanging addresses of different caches for each column of the linear address map. According to claim 2,
The shift of the linear address map,
The address mapping method characterized in that each column of the linear address map shifts to a different degree. According to claim 2,
The interchange of addresses or shifts of addresses is
Address mapping method performed from the second column, excluding the first column. According to claim 5,
The interchange of addresses or shifts of addresses is
It is done for n columns including the first column,
The same is repeatedly applied to subsequent columns,
An address mapping method characterized in that the n+1th column is not exchanged or shifted like the first column. a linear address calculation unit that calculates a linear address to map image coordinates to a cache;
an address conversion unit receiving the calculation result of the linear address calculation unit and changing an address according to the rule of any one of claims 1 to 6; and
and a multiplexer configured to select and output an address of the linear address calculation unit or the address conversion unit.