KR100479623B1 - Cache tag memory and driving system thereof - Google Patents

Abstract

The present invention relates to a cache tag memory, wherein the address of the cache tag memory is set to 'm + p' bits, and the lower m bits are used as addresses of each way cache memory, and the way is defined by the remaining upper p bits. In this case, the plurality of cache tag memories are implemented in one cache tag memory to drive the MATCH signal in an active state when at least one cache tag match occurs.

The present invention stores the cache tag data corresponding to the cache data, and sets the same associator to generate the cache tag data hit signal according to the comparison result of the cache tag data whether or not the data required by the CPU exists in the cache memory. One to one way cache tag memory used for the creative cache is composed of one cache tag memory.

Description

Cache tag memory and driving system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache tag memory suitable for a set associative cache. In particular, the present invention relates to a cache tag memory by implementing a plurality of cache tag memories into one cache tag memory. The present invention relates to a cache tag memory and a driving system for reducing the number and reducing the circuit area occupied by the cache tag memory on a board.

In general, the cache tag memory is almost similar to the structure of the static random access memory (SRAM), but the cache tag memory has a match (MATCH) which is an output signal indicating whether or not the cache tag data is hit. Of course, the signal name and the signal value at the time of activation may be different depending on the type of integrated circuit (IC), but the basic operation is the same.

FIG. 1A is a connection diagram of a cache tag memory according to the related art. As shown in FIG. 1A, a cache is updated or invalidated to maintain cache coherence by performing a bus monitoring function on all cache memories attached to a bus. A snoop control unit 101; In accordance with the signal output from the snoop control unit 101 stores the address of the data stored in the cache memory (not shown), and hitting the data requested by the CPU (not shown) (Hit) 1 to 1 way cache tag memories 111a to 111n for generating whether or not a signal MATCH is generated.

Here, reference numeral 'A [m-1: 0]' is a cache tag address bus, 'D [n-1: 0]' is a cache tag data bus, and 'CS_' is a selection signal of a cache tag memory. , 'WE_' is a write enable signal of the cache tag memory, and 'CLR_' is a clear signal for clearing all cache tag data stored in the cache tag memory to '0'.

FIG. 1B is a configuration diagram of an address map of each cache tag memory, in which cache tag data, which is an address of corresponding cache data, is mapped to each address (Add0 to Add ( ^2m- 1)).

Referring to the operation of the cache tag memory according to the prior art configured as described in more detail as follows.

First, in FIG. 1A, n and m are integers, and their values are determined according to the size of cache data and the type of CPU used.

In fact, the cache tag address bus is part of the lower address on the CPU-generated address bus, and the cache tag data bus is part of the upper address on the CPU-generated address bus.

The 1 to 1 cache tag memories 111a to 111n serve to store addresses of data stored in the cache memory, and determine whether or not data required by the CPU exists in the cache.

If the data required by the CPU is stored in the cache memory, a cache tag data hit occurs at the address of the data.

However, if the data required by the CPU does not generate cache tag data hits in the address (Miss), the desired data is not stored in the cache memory.

In more detail, the cache tag memory may drive data corresponding to the address of 'A [m-1: 0]' through the cache tag data bus when a read operation is performed and 'A [when a write operation is performed. The value 'D [n-1: 0]' of the cache tag data bus is used in an area corresponding to the address of m-1: 0] '.

Here, when a hit of cache tag data occurs, the corresponding cache memory activates the 'MATCH' signal. The conditions are as follows.

First, when the cache tag is compared, the cache tag memory selection signal CS_ and the writable signal WE_ are inactive, and are lower than the address to be referred to the cache tag address bus A [m-1: 0]. A part is driven, and an upper part of an address to be referred to the cache tag data bus D [n-1: 0] is driven.

At this time, if the address value driven on the cache tag address bus A [m-1: 0] is' x 'in decimal, the cache tag data value stored at the address' x' in the cache tag memory and 'D [n- If 1: 0] 'matches, the cache tag hit signal MATCH is driven in an active state, and if it does not match, the cache tag hit signal MATCH is deactivated.

In addition, during the read / write operation, the cache tag memory selection signal CS_ is activated to read or write cache tag data of an area addressed with 'A [m-1: 0]'.

Thus, by ORing the cache tag hit signals MATCH1 to MATCH1 output from the respective cache tag memories 111a to 111n, it is possible to know whether or not the cache tag data is hit.

That is, when the cache tag hit signal MATCH is activated in any one of the 1 to 1 way cache tag memories 111a to 111n, it can be seen that the cache tag data hit has occurred.

However, the cache tag memory according to the related art requires l cache tag memory integrated circuits when implementing the cache tag memory of the l-way set associative cache, which causes the cache tag memory unit to occupy a large circuit area.

Therefore, in order to improve the above-described problems of the prior art, the address of the cache tag memory is set to 'm + p' bits, the lower m bits of which are addresses of the respective way cache memories, and the way is determined by the remaining upper p bits. The present invention provides a cache tag memory and a driving system for implementing the plurality of cache tag memories in one cache tag memory to drive a MATCH signal in an active state when at least one cache tag match occurs. have.

The cache tag memory for achieving the object of the present invention is a compact cache tag memory that implements a plurality of way cache tag memory functions suitable for a set associative cache,

an address area composed of predetermined bits of 'm + p', of which the lower m bits are addresses of each way cache memory and each way is determined by the upper p bits;

And a plurality of match signal output units configured to output a cache tag data hit signal when data required by the CPU corresponding to each way determined in the address area exists in the cache memory.

Preferably, the plurality of match signal output units for outputting the cache tag data hit signal outputs the cache tag hit signal by logically adding to each match signal when at least one cache tag data match in each way cache tag memory occurs. It features.

The cache tag memory driving system according to the present invention is a single cache tag memory driving system that implements a plurality of cache tag memory functions suitable for a set associative cache, and performs a bus monitoring function on a cache memory attached to a bus. A snoop controller for updating or invalidating cache data to maintain cache coherency; In response to a signal from the snoop controller, a cache tag memory configured to drive a plurality of match signals in an activated state when the data requested by the CPU matches a cache tag data value stored at a predetermined address.

Preferably, the cache tag memory includes an address of a predetermined bit of the cache tag memory, a way determination signal of the predetermined bit, a selection signal of the cache tag memory, a writable signal of the cache tag memory, and a clear signal of the cache tag memory. Accordingly, the match signal is driven in an activated state.

 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2A is a connection diagram of a cache tag memory according to an exemplary embodiment of the present invention. As shown in FIG. 2A, a bus monitoring function is performed on all cache memories attached to a bus to update or invalidate cache data to maintain cache coherency. A snoop control unit 201; From the snoop control unit 201, the address A [m + p-1: m] of the m bit cache tag memory, the way decision signal A [m-1: 0] of the p bit and the cache tag memory A corresponding cache tag data value stored at an address according to the selection signal CS_, the write enable signal WE_ of the cache tag memory, and the clear signal CLR_ of the cache tag memory, and 'D [n-1: 0' ]) ', The cache tag memory 210 drives the' MATCHi '(i = 1, 2, ..., L) signal in an activated state.

In the address map of the cache tag memory 210, as shown in FIG. 2B and the following Table 1, the address (0 to 2 ^{m + p-} 1) is addressed as 'A [m + p-1: m]'. 1 to 1 way cache tag memories 210-1 to 210-L.

TABLE 1

 Cache tag memory internal separator  Addressing  Cache tag match signal   1 way cache tag memory     A [m + p-1: m] = 0       MATCH 1   2 way cache tag memory     A [m + p-1: m] = 1       MATCH 2             · · ·         · · ·         · · ·   ℓ way cache tag memory    A [m + p-1: m] = ℓ-1      MATCH ℓ

The operation of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, in the cache tag memory according to the present invention, the selection signal CS_ is activated and the writable signal WE_ is deactivated when the read operation is performed. The cache tag data stored at the cache tag address A [m + p-1: 0] is read through the cache tag data bus D [n-1: 0].

If the cache tag memory performs a read operation, both the selection signal CS_ and the write enable signal WE_ are activated so that the cache tag data value of the cache tag data bus D [n-1: 0] is addressed. Stored in (A [m + p-1: 0]).

Read / write is similar to a normal static RAM (SRAM) with an address bus of 'A [m + p-1: 0]' and a data bus of 'D [n-1: 0]'. That is, the selection signal CS_ is activated and reads or writes cache tag data addressed with 'A [m + p-1: 0]'.

When comparing the cache tag memory, if the selection signal CS_ and the writeable signal WE_ are both inactive and the value of 'A [m-1: 0]' is 'x' in decimal, the cache tag data bus D The value of [n-1: 0]) is compared with each cache tag data value stored at the address '(i-1) 2 ^m + x' (i = 1, 2, ..., l). If the value of 'D [n-1: 0]' is equal to the value of the cache tag data stored at address '(i-1) 2 ^m + x' (i = 1, 2,…, l), the cache The 'MATCHi' output signal from the match signal output unit to which the match signal of the tag memory is output is driven in an active state.

For example, if 'i' is 2, 'MATCH2' is activated when the cache tag data value stored at address '2 ^m + x' matches 'D [n-1: 0]'. .

Here, when 'MATCHi' is activated, it means that cache tag data hit has occurred in the i-way cache tag memory. When the output signals MATCH1 to MATCHℓ output from each match signal output unit are all inactive, the MATCH signal is inactive.

That is, the 'MATCH' signal is a result of logical sum of the output signals from 'MATCH1' to 'MATCHℓ' output from each of the plurality of match signal output units.

As a result, the hit of the cache tag data can be known through the 'MATCH' signal. As shown in Table 1, the division of the 1 to 1 way cache tag memories 210-1 to 210-1 is represented by the address A [m. + p + 1: 0]) values. That is, if the value of 'A [m + p + 1: 0]' is 'j' in decimal, it indicates 'j + 1' way cache tag memory address area.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Therefore, the above description is not limited to the scope of the present invention by the limitation of the claims.

As described above, the cache tag memory and its driving system according to the present invention implement a 1 to 1 cache tag memory used for the set associative cache as one cache tag memory, thereby enabling the cache to be used for the set associative cache. Since the number of tag memories can be reduced, the physical area occupied on the board can be reduced.

1A is a connection configuration diagram of a cache tag memory according to the related art.

1B is a configuration diagram of an address map of a cache tag memory according to the prior art.

2A is a diagram illustrating a connection configuration of a cache tag memory in a cache tag memory driving system according to an exemplary embodiment of the present invention.

2B is an address map configuration diagram of a tag memory according to an embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

201: snoop control unit 210: cache tag memory

210-1 to 210-L: 1 to 1 way cache tag memory

Claims (4)

A single cache tag memory that implements multiple way cache tag memory functions suitable for set associative cache,  an address area composed of predetermined bits of 'm + p', of which the lower m bits are addresses of each way cache memory and each way is determined by the upper p bits; And a plurality of match signal output units configured to output a cache tag data hit signal when data required by the CPU corresponding to each way determined in the address area exists in the cache memory. The method of claim 1, The plurality of match signal output units for outputting the cache tag data hit signal may output a cache tag hit signal by performing a logical OR on each match signal when at least one cache tag data match among each way cache tag memory occurs. Cache tag memory. In a single cache tag memory driving system implementing a plurality of cache tag memory functions suitable for a set associative cache, A snoop control unit performing a bus monitoring function on the cache memory attached to the bus to update or invalidate cache data to maintain cache coherency; A cache tag memory configured to drive a plurality of match signals in an activated state when data requested by a CPU matches a cache tag data value stored at a predetermined address according to a signal from the snoop controller Memory driven system. The method of claim 3, wherein The cache tag memory includes a match signal according to an address of a predetermined bit of the cache tag memory, a way determination signal of the predetermined bit, a selection signal of the cache tag memory, a writable signal of the cache tag memory, and a clear signal of the cache tag memory. Is driven in an activated state.

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