KR102556115B1 - Delay post-write in memory with calibration support - Google Patents

Abstract

A memory with delay post-write into an array of data corresponding to a previously opened page allows delays associated with post-write operations to be avoided. After every initial activation opens a first page and read/write operations to that page have completed, post-write of the opened page to the array of memory cells is delayed until after the completion of a subsequent activation operation that opens a new page. Techniques for forcing post-recording in the absence of another activating action are also disclosed. Calibration and testing sequences are also supported, where a non-destructive mode protects the data stored in the non-volatile memory array and the status bits used to indicate that open pages have been cleared, thereby enabling the end of calibration or testing. The resultant later unintended delay post-write operations do not corrupt the non-volatile data.

Description

Delay post-write in memory with calibration support

Cross-reference to related application(s)

This patent application provides the benefit of 35 U.S.C. § 365, the entirety of which is incorporated herein by reference.

technical field

This posting herein relates generally to memory devices with write-delay for arrays, and in particular to support such write-delay operations within memory devices where calibration procedures are used. circuits and methods.

Spin-torque magnetic memory devices operate in such a way that a read current across a magnetic tunnel junction (MTJ) results in a voltage drop whose magnitude is based on the state of the magnetoresistive stack. It stores information by controlling the resistance across the tunnel junction. The resistance within each magnetic tunnel junction can vary based on the relative magnetic states of the magnetoresistive layers in the magnetoresistive stack. Within these memory devices, typically one portion of the magnetoresistive stack has a fixed magnetic state and another portion has a free magnetic state that is controlled to be in one of two possible states for the portion with a fixed magnetic state. there is Since the resistance through the magnetic tunnel junction changes based on the orientation of the free part relative to the fixed part, information can be stored by setting the orientation of the free part. Information is later retrieved by sensing the orientation of the free part. Such magnetic memory devices are well known in the art.

Some magnetoresistive memory devices, such as magnetic random access memory (MRAM), support access protocols also used by other memory devices. For example, dynamic random access memory (DRAM) devices using synchronous double data rate protocols (eg, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, etc.) are well suited to the present technology. It is known. Some MRAM devices support these protocols, where identical operating codes for DDR SDRAM devices result in identical or similar operations within the MRAM devices.

The detailed description that follows is illustrative in nature only and is not intended to limit the subject matter or embodiments of the present application or uses of such embodiments. Any implementation illustratively described herein is not necessarily preferred or constituted advantageous over other implementations.

For purposes of simplicity and clarity, the drawings depict the general structure and/or manner of construction of various embodiments. Descriptions and details of well-known features and techniques may be omitted so as not to unnecessarily obscure other features. Elements in the drawings are not necessarily drawn to scale: to help improve understanding of the example embodiments, the sizes of some features may be exaggerated relative to others.

The terms “comprise, include” and “have” and any variations thereof are used synonymously to indicate a non-exclusive inclusion. The term "exemplary" is used in the sense of "example" rather than "ideal".

For brevity, prior art, structure, known to those skilled in the art, including, for example, standard magnetic random access memory (MRAM) processing techniques, generation of bias voltages, magnetic fundamentals, and basic operating principles of memory devices. , and principles may not be described herein.

While this description proceeds, like drawing reference numbers may be used to identify like elements along different drawings representing various exemplary embodiments.

For brevity, prior art techniques relating to reading and writing memory and other functional aspects of certain systems and subsystems (and their individual operating components) may not be described in detail herein. Moreover, the connecting lines shown in the various figures included herein are intended to represent exemplary functional relationships and/or physical connections between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in an embodiment of the subject matter.

Magnetic memory devices and other memory devices often include an array of memory cells divided into a plurality of banks or subarrays. Within these memory devices, each bank can be accessed individually so that accesses between the banks can be interleaved to optimize data throughput. Some magnetic memory devices support DDR memory protocols, where an activate operation opens a page of memory cells within a particular bank. A "page" of memory cells is understood to be a group of memory cells that are accessed together as a unit. In some examples, a “page” may consist of a “row” of memory cells. When a page is opened, the data for the page is moved from the array of memory cells to a cache or other form of temporary storage where the data is more easily accessed. When a page is activated (opened), read and write operations to the page can be performed. Upon completion of read/write operations to an open page, the page is closed. When a page is closed, the array is returned ready for subsequent page activation, and the data within the closed page cannot be accessed again for reads and writes without reopening the page. Within some memory devices, data moved to temporary storage during an activate command is immediately written back to the array, and in some cases, data corresponding to write operations performed while a page is open is also immediately written to memory cells in the array. It is recorded. In these memory devices, a pre-charge operation may pre-charge only bit lines and de-assert a word line corresponding to a page. Within other memory devices, data moved to temporary storage during activation and data written to an open page are not stored in the array until immediately before closing the page. As such, within such memory devices, a pre-charge operation will also include performing a post-write of data from temporary storage to the array. By waiting until just before a page closes to write data back to the array, the memory device can conserve power or improve timing specifications associated with moving or modifying data.

Having multiple banks allows multiple pages to be opened, thus enabling interleaving of accesses. This is because each bank has its own temporary storage or corresponding cache allowing separate reads and writes. Figure 1 shows the interleaving of multiple memory reads corresponding to three different pages in three different banks. Each block represents the time consumed by a particular operation relative to other ongoing operations. An upper row of blocks represents read access to BANK1 PAGE1. At block 110, activation of BANK1 takes place. During an activation operation, data corresponding to PAGE1 is retrieved from the portion of the array corresponding to BANK1 and stored in the cache for read/write access. As discussed in more detail below, the activation operation can be very time consuming, particularly within magnetoresistive memory devices that use a self-referencing read operation to sense data stored in an array.

After activation, read requests require read access time to fetch the specific data to output. This corresponds to block 111 labeled CL for "CAS latency". CAS latency is a term used primarily to indicate the time between the receipt of a read request and the output of data corresponding to the read request. That time corresponds to selecting particular data in the open page and routing that data to the outputs of the memory device. Read data is output during block 112 . In particular, while only a single read access to BANK1 PAGE1 is shown, it is understood that many read and write accesses may occur while the page is open. Within the prior art memory devices associated with Figures 1 and 2, once all accesses to the page have been completed, the pre-fill command at block 113 closes the page and writes the data in the cache back to the array. This post-write operation to the array can also be very time consuming compared to the time required to perform read and write operations while the data is in the cache.

1 and 2 are block diagrams illustrating the relative timing of various aspects of data access operations within a prior art memory device.
3 are block diagrams illustrating the relative timing of various aspects of data access operations within a memory device in accordance with an illustrative embodiment.
Fig. 4 is a schematic diagram of a portion of a magnetic memory device according to an exemplary embodiment;
5-7 are flow diagrams corresponding to methods for performing and supporting write-delay in a magnetic memory according to example embodiments.
Fig. 8 is a schematic diagram of a portion of a magnetic memory device with an associated timing diagram according to another exemplary embodiment.
9 and 10 are flow charts corresponding to methods for performing and supporting non-destructive calibration within memories supporting write-delay according to exemplary embodiments.

As shown in Figure 1, multiple pages can be opened within multiple banks to "hide" some of the delays associated with various operations. This allows the most efficient use of the various signal lines used to carry commands, addresses, and data to and from the memory device. For example, even if an activation command for BANK1 is received by the memory, a second activation command corresponding to BANK2 may be transmitted. Since BANK2 has its own cache, activation of individual pages within BANK2 allows BANK1's PAGE1 to be opened simultaneously with BANK2's PAGE1. The second row of blocks in FIG. 1 shows that the time for activation of BANK2 PAGE1 at block 120 overlaps portions 110-112 of activation and readout within BANK1. The read operation of BANK2 is similar in timing to that of BANK1, and is shown to include a read access time 121, a read data output 122, and a pre-fill block 123. The third row of FIG. 1 shows similar operations 130-133 for BANK3.

As shown in Figure 1, since the sequential accesses are in different banks (e.g. read first from BANK1, then from BANK2, and then from BANK3), the interleaving of the accesses ensures that the read data is stored in the memory device By this, it can be output relatively continuously. Read data 112 for BANK1 is immediately followed by read data 122 for BANK2, and read data 122 is eventually followed by read data 132 for BANK3. High throughput can be achieved because interleaving between banks can at least somewhat hide the delays associated with activation, read access time, and pre-charge.

However, as shown in FIG. 2 , in some instances sequential accesses may be to different pages within the same bank. In the illustrated example, BANK1 PAGE1 is activated at block 210 and after read access time 211 , read data 212 is output. If the next access is a read to BANK1 PAGE2, then PAGE1 of BANK1 must be closed via prefill 213 before PAGE2 of BANK1 can be opened via activation 220. Following activation (220), read data (222) is not output until after the read access time (221). Then pre-charge 223 closes PAGE2 of BANK1. As will be clear from FIG. 2, these back-to-back accesses to the same bank do not sufficiently hide the activation, read access time, and time associated with pre-charge. Although the pre-charge operation may start when the last read data is output (i.e., slightly before the completion of the read data block 212), as shown, the read data output 212 from the first page and the second page The time delay between reading data output 222 from

In current dynamic random access memories (DRAM), the timing associated with the activation and pre-charge operations is not much greater than the timing of the data access cycle of other aspects, so the delay of the back-to-back operation as shown in FIG. is permissible However, in MRAMs, activation and post-write operations often take much longer, resulting in greater undesirable delay between data accesses for these same-bank sequential accesses.

In some MRAMs, a self-referencing read operation is used to sense the data stored in the array for the page to be accessed. In an exemplary self-referencing read, the initial resistance through each memory cell in the page is sensed, then all memory cells in the page are written to a known state, and finally, the post-write resistance through each cell is It is sensed again and compared to the initial resistance that was sensed before recording. Whether the resistances are the same after writing to a known state indicates the initial state of the memory cell. In particular, self-referencing reads are destructive, leaving all memory cells in a known state written between two sense operations. This self-referencing read operation often takes significant time compared to other aspects of memory accesses. For example, activating a page in MRAM may require on the order of hundreds of nanoseconds, whereas a read operation to an open page may take on the order of tens of nanoseconds.

Likewise, the time required to post-write a page of data to the array upon completion of read/write accesses can be significant. For example, to prolong the lifetime of MRAM devices, large-magnitude write current pulses that can rapidly change the state of a free layer in a spin-torque memory cell are typically avoided because such large pulses are magnetoresistive. This is because it can damage sensitive layers in the stack. To avoid collapse of the layers, lower magnitude and longer duration write pulses are often used because they allow the free layer to be switched with little adverse effect on the device layers. Although promoting longer lifetimes for memory devices, these long-duration write pulses increase the time required for post-write operations.

Embodiments disclosed herein use delay-post-write of closed-page data to help improve overall throughput in magnetoresistive memory devices. This is accomplished by delaying post-writing of data corresponding to a closed page until the performance of writing back does not adversely affect the timing of other ongoing operations associated with reads and writes. As disclosed herein, in some embodiments, a post-write corresponding to a previously opened page is performed following an activation operation for the next page to be accessed. In some embodiments, supporting such delay-post-write within memory may require additional circuitry or techniques to implement other memory support functions. For example, some memory protocols use calibration sequences at startup to optimize the timing associated with signaling between the memory and other integrated circuits such as, for example, a memory controller. do. As discussed further below, supporting such calibration operations in the context of a memory that includes delay post-write operations is such that such calibration operations do not negatively affect the non-volatile nature of data stored on such memory devices. You can benefit from additional circuits and techniques that ensure

Figure 3 helps illustrate the delay-after-write concept. As shown in Figure 3, at block 320, activation of BANK1 PAGE2 occurs. Following read access time 321, read data 322 is output. When the activation operation corresponding to BANK1 PAGE2 is complete and the PAGE2 data is transferred from the array to the cache used for read and write operations, BANK1 in the array is no longer active. In this way, a post-write operation corresponding to a previously opened bank can be performed during a time when read and write operations for a newly activated bank occur. As shown in FIG. 3, the post-write operation on BANK1 PAGE1 at block 313 occurs once the activation operation 320 on BANK1 PAGE2 is complete. 3 labels block 313 as "pre-charge post-write BANK1 PAGE1", in some cases, the post-write operations performed in block 313 are not the result of a pre-charge command received by the memory. It should be recognized that no In some embodiments, the indication that read/write operations to the page have completed is based on receipt of a pre-charge command by the memory device. In other embodiments, post-writing of data occurs in response to a subsequent activation operation to the same bank. As described in additional detail below, additional commands or signals are used in some embodiments to trigger post-write operations such as shown in block 313.

As noted above, post-write operations to a bank that is closed typically occur as soon as read and write accesses to that bank are complete, and such post-write operations typically occur in response to a pre-charge command received by the memory device. is promoted by As described herein, rather than performing post-write immediately upon completion of read and write accesses to prevent subsequent activation operations from fetching data from the array until after the post-write operation has completed, as described herein, Embodiments delay the post-write operation until the post-write can be hidden and not affect the timing of the subsequent activation operation. Since post-write to a previously opened page is to write the data corresponding to the closed page to the array, there is no unfavorable delay by shifting the post-write operation so that it occurs after the next page is opened. also does not result in That is, since another, different page is currently being accessed, there is no rush to place the data back into the array.

As shown in FIG. 3, by delaying post-write corresponding to a previously opened page in a bank until after the next activation operation for that bank has completed, the pre-charge time associated with that bank can be hidden, thereby enabling the memory device Latency and throughput characteristics for are greatly improved. Indeed, as shown in FIG. 3, the memory may read and write data while post-writes to previously opened pages in its bank occur (e.g., block 322). 3, the initial state of the memory device corresponds to the point at which BANK1 PAGE1 has been previously opened, but read and write operations corresponding to that page have been completed, and PAGE1 data is ready to be written back to the array. With PAGE1 data ready to be post-written, an activation command corresponding to BANK1 PAGE2 has been received, thereby indicating that PAGE2 will be opened for read and write accesses. Instead of completing post-write operations on PAGE1 prior to activation of PAGE2, PAGE2 is opened first, and upon completion of its activation, unless it delays any operation associated with activating PAGE2 or accessing data within the newly-opened PAGE2. At (e.g., read access time 321 and read data 322), a post-write operation to PAGE1 may occur. This provides a significant timing advantage over systems where this post-delay write is not used.

Following accesses to BANK1 PAGE2, activation of BANK1 to PAGE3 occurs at block 330 . Upon completion of activation on PAGE3, a post-write to BANK1 PAGE2 can occur, with read access time 331 and read data 332 to PAGE3 occurring simultaneously. Likewise, post-write for PAGE3 begins when activation of BANK1 PAGE4 is complete at block 340 . In particular, a post-write operation for a previously opened page can occur as soon as all parts of the next activation command that will prevent post-write from occurring have completed. For example, while some parts of post-write and activation use the same circuitry on the memory device (e.g., write drivers, column decoders, etc.), other parts of the activation operation when the post-write operation begins. Independent circuits can be used so that some aspects of .

Embodiments described herein use the time after the activation operation (when reads and writes to the newly opened page are taking place) to post-write data corresponding to the previously opened page to the array. To accomplish this, data corresponding to previously opened pages must be stored in a location that will not interfere with the activation of the new page being accessed. In some embodiments, each bank of a memory device includes two cache structures, where a first cache acts as a primary or active cache for read/write operations to an open page and a second cache serves as an access cache. It acts as a temporary storage location for data corresponding to pages on which pages have been completed but post-write has not yet occurred.

Turning to FIG. 4 , a schematic diagram of a portion of a memory device 400 in accordance with various embodiments is provided. The memory device 400 includes an array 405 of memory cells. In some embodiments, the memory cells are non-volatile spin-torque MRAM cells, while in other embodiments the memory cells are other types of memory cells, such as DRAM cells or other resistive memory cells, for example. As shown in FIG. 4 , the array 405 includes a plurality of banks including BANK1 410 and BANK2 420 . Each BANK1 410 and BANK2 420 has a corresponding set of circuitry 414 and 424 used to temporarily store data for read and write accesses to pages within banks 410 and 420. includes each Circuitry 414 for BANK1 410 includes a first cache 415 , a second cache 416 , and an update circuit 417 . Update circuitry 417, which may include parity calculator 418 and/or majority detection circuitry 419, is described in additional detail below.

As shown in FIG. 4 , caches 415 and 416 are coupled to BANK1 410 such that data is passed between BANK1 410 and caches 415 and 416 in array 405 . In some embodiments, each of caches 415 and 416 includes static random access memory (SRAM) memory cells, while in other embodiments, caches 415 and 416 store data Registers, flip-flops, or other storage circuits used to store . Caches 415 and 416 include storage sufficient to accommodate a page of data from BANK1, and include the address of the page, parity or other error correction code (ECC) information for the page, and information associated with the page. It may also include additional storage for storing any inversion or other information. In some exemplary embodiments, caches 415 and 416 are approximately 64 data words at 8 or 16 bits/word. In other exemplary embodiments, caches store 128 or 256 words. In some embodiments, as the word size increases (eg, from 8 bits to 16 bits), the banks are combined to maintain the number of data words stored. The size of caches and the size of accessed pages can be adapted to the needs of the application.

As shown in Figure 4, each bank in array 405 has a corresponding set of caches and update circuitry. BANK2 420 is shown coupled to caches 425 and 426 along with update circuit 427 . By having separate cache structures for each bank, multiple pages in different banks can be open simultaneously, allowing interleaved accesses. While the embodiment depicted in FIG. 4 shows two caches for every bank, in other embodiments three or more caches are included for each bank, so that post-writes of two or more pages are possible at a later point in time. may be delayed up to These additional caches may be suitable for embodiments where the time required for post-write is much greater than the time required for activation operations, or where access patterns benefit from the delay of write-back for large numbers of pages. In yet other embodiments, each bank has one corresponding cache for storage of pages open for read/write operations, but shares the second cache with one or more other banks, wherein the second cache is only used to store data corresponding to closed pages that have not yet been written to. It should be noted that sharing the write-back cache between banks may limit activation operations for those banks, to ensure that collisions do not occur when all banks request to use the write-back cache at the same time.

Control circuit 450 is coupled to array 405 and circuit 414 , where circuit 414 includes update circuit 417 as well as caches 415 and 416 . In the embodiment shown in FIG. 4, control circuitry 450 is coupled to all banks in array 405 and all cache structures and update circuitry for those banks. As such, control circuitry 450 in the FIG. 4 embodiment provides overall control over memory access operations. In other embodiments, a dedicated control circuit is provided for each bank so that operations for each bank are individually controlled.

Control circuitry 450, which may include, for example, a state machine, processor, microcontroller, or logic circuit, controls the movement of data and operations performed on that data for the various memory access operations supported by the memory device. is configured to Control circuit 450 receives commands 434 and a reset signal 435 . In other embodiments, control circuit 450 receives additional signals from within the memory device or from outside the memory device, which additional signals provide information to control circuit 450 to facilitate data storage and retrieval operations. or commands. For example, control circuitry 450 may receive a self-refresh signal indicating that no immediate accesses are imminent, and while this signal is asserted the memory device may perform other operations. have a chance to perform Commands 434 received by control circuitry 450 may include commands received from an external memory controller or other control device that issues commands to the memory device. For example, an external memory controller can provide commands 434 to control circuitry 450, where these commands activate, read, write, pre-charge, read with auto pre-charge, auto pre-charge. with write, and refresh commands. In other embodiments, commands directing the activities of the memory device, some shared circuitry performs some of the activities related to each command, and control circuitry 450 may perform higher-level commands received by the memory device. may be processed in a hierarchical manner, to receive more localized commands 434 derived from .

In operation, the control circuit 450 is configured to forward a first page of data from a first location in the array to the first cache in response to a first activate command received by the memory device. In the example corresponding to FIG. 4 , the first activation command causes the control circuit 450 to send the appropriate signals to the array 405 to transfer the data corresponding to the FIRST PAGE 411 in BANK1 410 to the cache 415 . and cache 415. In some embodiments, loading data for FIRST PAGE 411 into cache 415 includes performing a self-referencing read to memory cells included in FIRST PAGE 411 . In other embodiments, reference read operations (eg, where the resistance of each memory cell is compared to a criterion for determining the data stored therein) or other techniques to ascertain the data stored in each memory cell Used to load data for FIRST PAGE 411 into cache 415.

If the data for FIRST PAGE 411 is loaded into cache 415, then FIRST PAGE 411 is considered "hot" and read and write operations to FIRST PAGE 411 will cause the data in cache 415 to be read. This can happen by reading or overwriting data in the cache 415 . Each read or write command is accompanied by address information that allows specific words or sets of words in the FIRST PAGE 411 to be accessed. When all read and write accesses to FIRST PAGE 411 are complete, the data for FIRST PAGE 411, which may contain new data added by write operations, is moved from cache 415 to cache 416. do. In some embodiments, the indication that read/write operations to FIRST PAGE 411 are complete is based on receipt of a pre-charge command by the memory device. In other embodiments, the data is held in cache 415 , which may be referred to as the primary cache, until a subsequent activation operation on BANK1 410 is received by the memory device. As described in additional detail below, in some embodiments additional instructions or signals are used to cause data in cache 415 to move to cache 416 or directly back to BANK1 of array 405 .

After transferring the first page data from the first cache 415 to the second cache 416, the first cache 415 can receive data corresponding to a new page. Accordingly, in response to the second activation command corresponding to the SECOND PAGE 412 of the BANK1 410, the control circuit 450 generates the second page data corresponding to the SECOND PAGE 412 of the array 405 BANK1 ( 410) issues appropriate control signals to be delivered to the cache 415 at a location corresponding to the SECOND PAGE 412. SECOND PAGE 412 is thus “open” and read and write operations are enabled. When the activation operation for SECOND PAGE 412 is complete or has gone far enough so as not to interfere with the post-write operation for BANK1, the first page data corresponding to FIRST PAGE 411 stored in cache 416 is stored in array 405. ) can be back-recorded at an appropriate location in BANK1. As described above, since the address for the FIRST PAGE 411 can be included with the data stored in the cache 416, the location where the first page data will be written into the array 405 is also known. In other embodiments, a separate register or storage location may be used to store address information for each page along with any other suitable page-specific information such as parity information or inversion status.

In some embodiments, parity information or other form of ECC is used to prevent or reduce data errors. Parity computation is well known in the art, and storing a set of parity bits for a page in a bank with the page data will allow a parity check to verify data validity and, in some instances, the correction of data errors. can In the example described above with respect to FIG. 4, if the first page data corresponding to the FIRST PAGE 411 is later written to the array 405, the data may include parity information. Since the data contained in the FIRST PAGE 411 can be modified by write operations performed while the FIRST PAGE 411 is open, new parity calculations need not be performed before the data is written back to the array 405. there is. In some embodiments, parity calculations are performed each time each write operation to a page completes so that the parity information stored with the data in cache 415 is always up-to-date. In such embodiments, the correct parity information may later be shifted along with the data from cache 415 to cache 416 prior to writing back. However, performing these parity calculations in real time can be expensive in terms of time and resources (eg, will require extra power consumption). As such, since it is known that write operations to FIRST PAGE 411 will no longer occur when the data for FIRST PAGE 411 is moved to cache 416, parity calculations for FIRST PAGE 411 are performed in cache ( 415 to the cache 416. In FIG. 4 , parity calculator 418 is included within update circuitry 417 , where parity information is updated as data is passed from cache 415 to cache 416 .

Subversive self-referencing read operations that write all memory cells in a selected page to the first state leave all cells in the same state at the end of the activation operation, so that a number of bits in the page are written back to the first state before the page is written back. State (eg, binary “0”) or a second state (eg, binary “1”) may help reduce power consumption. For example, if an activation operation leaves all memory cells in a page in a first state corresponding to binary "0", and when data is ready to be written back, a number of bits in the page to be backwritten will be "0". ", then less than half of the memory cells will require one or more write pulses used to change the free layer within those cells to a state corresponding to the binary "1". However, if a number of bits in the page are "1", more than half of the memory cells will have to be written to change their state. In this example, it may be useful to invert all the bits for the page so that a state that previously represented a "0" now represents a "1". By inverting all the bits when the majority does not correspond to that state, the memory cells remain as activated when activation is complete, and write back will always involve writing to less than half of the memory cells in the page.

To support this inversion after majority detection, an inversion status bit is maintained for each page to indicate whether the data stored in array 405 for that page has been inverted or not. Additionally, if data within a page has been modified while the page was open, multiple detections need to occur for each page prior to post-writing of the page. As such, multiple detectors 419 are included within update circuit 417 . As is the case for parity calculation, majority detection can be performed in real time with each write operation, but it will be more efficient to perform the majority detection and setting of the invert bit when the page is in the process of being closed. Thus, in some embodiments, majority detection is performed when data for a page is passed from the first cache 415 to the second cache 416 .

To facilitate all internal operations involved in moving data between various locations and performing steps associated with parity calculation, majority detection, etc., control circuitry 450 is configured on the memory device to ensure that the correct operations are performed in the correct order and at the correct time. Generates a plurality of timing signals that instruct the circuit. In some embodiments, such timing signals are generated by delay circuit 455, which is shown as being included in control circuit 450. In some embodiments, the delay circuit includes a plurality of delay blocks or circuits used to generate timing signals associated with various functions that occur when data within memory array 405 is accessed. For example, in response to an activation operation on BANK1 in a situation where a previous page in BANK1 has not yet been written back, data from cache 415 is moved to cache 416, and any parity calculations and majority detection are performed. When the page to be opened is loaded into the cache 415 and activation is completed, a plurality of timing signals are generated to cause the data in the cache 416 to be written back to the array 405 . Thus, a single transition in the signal indicating activation may trigger multiple signal transitions spaced appropriately in time by delay circuit 455 so that appropriate actions occur at appropriate times. Intervals between the various timing signals can be programmable such that the relative times at which different operations are performed can be adjusted, for example by storing values in programmable registers.

Note that in some instances, sequential activations corresponding to the same page in the same bank may be received. For example, after the FIRST PAGE 411 is opened, and a number of read/write operations to data in the FIRST PAGE 411 have been performed, a pre-charge command may be received indicating that the FIRST PAGE 411 should be closed. there is. In some embodiments, receipt of a pre-charge command does not result in writing data back to the array, since control circuit 450 is waiting for the next activation command to do so. Thus, when a new activation operation corresponding to FIRST PAGE 411 is received, which instructs the memory to re-open FIRST PAGE 411, the data for FIRST PAGE 411 is stored in BANK1 410 of array 405. ), the transfer of data from the array 405 to the cache 415 will not place the data for the FIRST PAGE 411 into the cache 415. In some embodiments, when a re-activation command for FIRST PAGE 411 is received, the data for FIRST PAGE 411 is still in cache 415 . As such, in some embodiments, control circuit 450 includes a page address comparator configured to compare the address accompanying the activation command with the address of the last opened page. If the comparison indicates that the new page to be opened is identical to the previous page, and the data for the previously opened page is still in main cache 415, control circuitry 450 will do nothing. If the new page to be opened is the same as the previous page and the data for that page has already been delivered to cache 416, then the data is delivered directly back to cache 415, or the data is retrieved from the array again and returned to cache 415. It can be written back to the array 405 before being loaded.

Another potential problem with delayed post-writing of the previous page occurs when the previous page of data is not being written back in response to a pre-charge command, but instead is waiting for another activation command that will never come. For example, the last data accesses to the bank before power down can cause data for the accessed page to remain in cache 415 or cache 416 waiting for the next activation. Without this activation, post-write to the array 405 would normally not be initiated. As such, a power-down can occur without data being written back to the array 405 . If cache structures are volatile storage, data may be lost.

In some embodiments, this problem is addressed by using non-volatile storage for one or both caches for each bank. In other embodiments, the memory device may periodically post-write to the array when no new activation command is received. In some embodiments, a refresh command or refresh signal received by the memory device indicates that the memory controller will not issue an activation for the time being, and the memory has an opportunity to perform a “refresh” operation. These refresh operations are used within DRAMs to replenish charge on capacitors within one or more rows within an array of memory cells. To perform a refresh, all banks in DRAM are typically closed. As such, even if the MRAM does not need to perform refresh operations, it can take a refresh command or signal as an indication that all banks should be closed and data corresponding to pages currently held in caches should be written back to the array. there is. In other embodiments, a refresh command/signal can be used to initiate a post-write to one of many banks, where the memory device keeps track of which banks have been post-written to which bank the next refresh is. You know if you want to trigger a post-record.

In other embodiments, the reset signal 435 can be used as a trigger to initiate post-writes to the array. By specifying to users that they need to assert the reset signal to ensure that the data in memory is non-volatile, the user can assert the reset signal prior to events such as power down to ensure that the last opened page is Data may be passed from cache 415 to cache 416 (along with possible parity and inversion calculations) and then written back to memory array 405, for example.

In yet other embodiments, the new action code may be specifically used to cause post-write to occur without requiring another activation. For example, a “STORE” opcode may be sent to memory by the memory controller, where the STORE opcode causes the MRAM to post-write any rows awaiting post-write. This STORE opcode is either bank-specific (STORE-BANKx, where x = number of banks) in that it directs the data corresponding to only one bank to be written back to the array (the data for a subset of banks is written back). ), and the data for all banks can be stored (STORE-ALL). These new opcode(s) are used to clean up any volatile data on the memory device, causing that data to be stored within non-volatile storage of the array 405, so that the data is lost even if power is removed. don't let it happen

When post-write operations to a large page (many bits per page) or multiple banks occur, write back to subsets of memory cells to reduce power and current spikes associated with the write-back operations. It may be desirable to stagger the actions. In such staggering, portions of memory cells are written back at different times, so that the current draw and power consumption associated with writing back is spread out over time. Thus, the first data portion to be written back is written at a different time than the second data portion. For example, when writing back to a large page, half of the bits in the page are written back first, then the other half of the bits are written back later. In another example corresponding to the STORE-ALL command or action code, the data for half of the banks is first backwritten, then the data for the other half of the banks is backwritten. In another STORE-ALL example, half of the bits in each bank are first backwritten, then the other half of bits in each bank are backwritten. In yet another STORE-ALL example, post-write operations are serialized such that one bank or group of banks waits for completion of the post-write operation(s) within another bank or group of banks. . This staggering of write-back operations can be divided into many steps, can be set to be programmed, and can be bank-specific, memory cell-specific, or both.

If the delay circuit 455 is used to generate the timing signals used to perform post-write operations and these signals are delay-based signals generated in response to a trigger signal, the post-write operations will generate a clock signal. It can be achieved without the need for it. This means that after the system issues an indication that post-write should occur (e.g., a refresh, self-refresh, reset, or STORE-command), the clock is turned off without concern that data has not been written back. off) to be able to If post-writes are staggered, the delay circuit can use feedback or daisy-chain multiple delay circuits to ensure that some post-write operations occur before others.

While it has been described above with respect to Figure 4 that the newly-activated pages are transferred to the primary cache 415 and their data is moved to the secondary post-write cache 416 before writing back, in other embodiments, the data Rather than moving between caches, the roles of caches can change. For example, a first activation loads a first page of data into a first cache, and a second activation loads a second page of data into a second cache before writing back the first page of data from the first cache to the array. Can be loaded into cache. Reads and writes to the first page will occur using the first cache, and reads and writes to the second page will use the second cache.

After all pages in the bank have been back-written to the array 405, the next activation operation should not backwrite the data stored in the cache 415. As such, a flag or one or more status bits 470 and 471 may be used for each bank to indicate whether the bank has pages open and/or awaiting post-write. Thus, when the device is first turned on, a flag is cleared or status bits are updated to indicate that no pages are open and are not waiting for post-write. When the first page is opened, flag or status bits 470 are set such that subsequent activation triggers post-writing of the first page data. If a STORE or post-write indication is received, the data is written back and the flag or status bits 470 are cleared. In some embodiments, status registers that already exist in standard-compliant memory devices may be used to store these flags or status bits.

In some embodiments, flags or status bits 470 associated with whether a bank is open or has data waiting to be written back may be checked for testing, burn-in, or in a manner different from normal operation. It may be manipulated to support other operations designed to execute the memory device. For example, some testing operations want to keep accessing the same page in a bank without worrying about the actual data stored in the bank. By keeping the open indication for that bank clear and not comparing the address of the active page to the last active page, the memory device responds to an attempt to open a page that is already open, doing whatever it wants rather than doing nothing. can be executed

In yet other embodiments, startup or configuration testing is performed to optimize the timing of certain signals received or passed by the memory. For example, a data strobe (DQS) within the DDR SDRAM protocol is often calibrated for each memory to account for the time to fly a signal from the memory controller to the memory. This calibration uses multiple read/write operations to each memory to calibrate the data strobe. In the case of non-volatile memories such as MRAMs, data stored in an array of non-volatile memory cells is assumed to be stable after power is turned off. As such, if calibration procedures are performed to optimize the timing of data strobes or other signals when power is restored, read/write operations associated with such calibration may inadvertently overwrite non-volatile data. In some cases, this is because calibration procedures were originally developed for volatile memory, such as DRAM, where data in a memory array is expected to be invalid or meaningless when powered on. As such, to support calibration procedures in connection with interfaces, such as a DDR SDRAM interface, on memories using the delay-post-write techniques described herein, without disturbing the non-volatile data stored within the array 405. To ensure that this calibration can occur, additional steps can be taken in non-volatile memories such as MRAMs.

access to the memory array within these memories during calibration or startup operations so that non-volatile stored data remains undisturbed, as described in U.S. Patent No. 9,275,715, issued March 1, 2016; may be disabled. The contents of U.S. Patent No. 9,275,715 are incorporated herein by reference in their entirety. As described in U.S. Patent No. 9,275,715, a non-destructive mode for the memory is used to prevent reads from the array, writes to the array, or both reads from the array and writes to the array. can be used In some embodiments, the non-disruptive mode is a default mode that is entered at power-on, while in other embodiments, the non-disruptive mode is in response to a command received by the memory in response to one or more actions on the memory. It is entered based on the values stored in registers 480. In some embodiments, exiting non-destructive mode may be accomplished by changing a value stored in one or more registers. For example, non-destructive mode can be entered by setting a bit in a register to “1” and exited by clearing that bit to “0”. Thus, following calibration, testing, or other operations using the non-destructive mode, the memory may transition to a normal operating mode in which access to the array of non-volatile memory cells is enabled. In some embodiments, the transition from non-destructive mode to normal operating mode is based on a determination that calibration, testing, or other operations have been completed, either internally by the memory or by a memory controller or other external source ( source) may be based on a signal received by the memory. Thus, in some embodiments, the memory may default to a non-destructive mode when powered on and then automatically exit the non-destructive mode upon completion of the calibration procedure.

When the memory is in non-destructive mode, data stored in the non-volatile memory array is undisturbed. In non-destructive mode, reads and writes to memory that typically store data in or retrieve data from array 405 contain non-volatile data that is expected to survive calibration or testing. This may be done using cache structures or other on-memory storage.

In embodiments that support such a scheme in which memory accesses to the non-volatile array 405 are disabled during calibration or startup, the memory is switched from a non-destructive mode to a normal operating mode and accesses to the non-volatile array 405 are disabled. When is enabled, flags or status bits 470, 471 indicate that the so-called page that was accessed during calibration is open, and these flags or status bits 470, 471 indicate that one of the caches on memory Flags or status-bits associated with pages of memory in such arrays may be managed to prevent post-write operations in which invalid data stored in the array overwrites valid data in the array. Various embodiments supporting non-destructive modes with write-back are described in more detail below.

In one embodiment, when the memory is in non-destructive mode, flags or status bits 470 used to indicate whether a page is open and will eventually need to be written back are disabled. Thus, while the memory is in non-destructive mode, no data in the array 405 will be overwritten or changed, even if an activation operation code or command is received, and a status bit to indicate that the page of data for the activation operation is open. s 470 are not updated or set to such a state. Instead, status bits 470 are left alone or changed to indicate that no post-writes are pending or needed. Thus, when memory transitions from non-destructive mode to normal operating mode, status bits 470 indicate that no pages are open when memory enters normal operating mode, so active or caches received Any other "trigger" command or indication that could cause a post-write from one of (415, 416) to the array 405 would not result in any such post-write.

In other embodiments, flags or status bits 470 are cleared when the memory transitions from a non-destructive mode to a normal operating mode. In some cases, this is the mode change detection circuit 482 on the memory device, which detects a transition from a non-destructive mode to a normal operating mode and clears or resets flags or status bits 470 when this transition occurs. ) can be achieved. If a bit in register 480, which can be, for example, a mode register such as those used in normal DDR-compatible memories, indicates that the memory is in non-destructive mode or normal operating mode, then the memory is in non-destructive mode. Clearing flags or status bits to indicate that there are no open pages that need to be written back, using switching that bit from a state indicating that the memory is in normal operating mode to a state indicating that the memory is in normal operating mode; You can trigger a reset.

In yet other embodiments, a system including memory may ensure that flags or status bits 470 are reset or cleared before the memory is switched from a non-destructive mode to a normal operating mode. For example, a memory controller or other object controlling calibration or testing may issue commands to the memory instructing it to perform a post-write operation. As described herein, these instructions may include refresh, self-refresh, pre-charge, reset, or STORE instructions, where, after such instructions are executed, flags or status bits are in a reset or cleared state. , thereby indicating that no pages are open and no pages need to be backwritten. In particular, giving these commands while the memory is in non-destructive mode does not affect the data stored in the array, since such data is protected while the memory is in non-destructive mode. In yet another embodiment, a dedicated command or sequence of signal transitions may be provided by a memory controller, where the dedicated command or sequence of signal transitions is received by the memory, and the memory responds with flags or status bits. clear or reset them.

5-7 and 9-10 are flow diagrams illustrating aspects of example embodiments or embodiments of methods for supporting write-delay in memory devices. In one example, memory devices include an array of spin-torque magnetic tunnel junction memory cells. The actions included in the flowcharts may represent only a portion of the overall process used to operate the device. For purposes of presentation, the following description of the methods in FIGS. 5-7 and 9-10 may reference elements discussed above with respect to FIG. 4 . The method may include any number of additional or alternative operations, the operations illustrated in FIGS. 5-7 need not be performed in the order shown, and the methods may include more functions with additional functionality not detailed herein. It should be appreciated that it can be incorporated into a comprehensive procedure or process. Moreover, one or more of the tasks shown in Figures 5-7 may be omitted as long as the overall intended functionality remains intact.

Turning to FIG. 5, at step 510, a first activate command is received for a first page in a first bank of a memory device. At step 520, in response to the first activate command, the first page of data is retrieved from the array and stored in a first cache on the memory device. When a first page is activated in this way, read and write operations to data in the first page can occur by accessing the first cache. In the DDR protocol, the first page will typically be closed based on receipt of a pre-charge command corresponding to the first page. This pre-charge command will be issued before the read/write operations for the first page are complete and before the second activation command is received at step 530 . In particular, while such a pre-charge command may be issued and received by the memory in a system where the memory resides, in some embodiments post-write operations are no longer directly performed in response to such a pre-charge command because , the memory simply ignores the pre-charge command.

At step 530, a second activation command for a second page in the first bank is received. As described above with respect to FIG. 4, to move the data for the second activation instruction from the first bank of the array to the first cache for access, the data corresponding to the first page is finally written back to the array. before being moved to the second cache. However, by delaying post-writing of data corresponding to the first page until activation of the second page is completed, the time associated with writing back of the first page data can be hidden and any reading related to the second page can be hidden. Or it will not delay write operations either.

At step 540, in response to the second activate command, the memory begins retrieving the second page of data from the array. At step 550, the first page data is transferred from the first cache to the second cache. In particular, as long as the first page data is out of the first cache before the second page data is stored in the first cache, delivery of the first page data will occur at the same time as the retrieval of the second page data is initiated. can Although the flowchart of Fig. 5 indicates that the retrieval of the second page data begins prior to the delivery of the first page data, the order of these steps is not important, as long as no conflicts occur. In some embodiments, delivery is initiated in step 550 in response to a second activation command, while in other embodiments, delivery is initiated in response to a first page received prior to the second activation command, as described above. Triggered by the pre-charge command. Thus, a pre-fill instruction may trigger a movement of the first page data from the first cache to the second cache, but the data may remain in the second cache until a subsequent activate instruction causes it to be written back.

In particular, in some embodiments, a pre-charge command is not used to trigger the movement of data from the first cache to the second cache. In such embodiments, the pre-charge command may have no function, such that the memory device does nothing in response to the pre-charge command. By eliminating the need for pre-charge commands, the timing associated with providing these pre-charge commands within standard protocols, such as those used for DDR memory devices, can be modified in a way that allows memory system designers more flexibility. , can be alleviated.

The transfer of the first page data from the first cache to the second cache at step 550 is performed at step 551 such that the appropriate parity or other ECC information is available when the first page data is written back to the array. This may include performing calculations. Similarly, multiple detection and inversion at step 552 may be included as part of the data transfer from the first cache to the second cache. Performing parity calculation and majority detection at this point makes sense as any writes to the first page have completed, so the transferred data is final with respect to parity and inversion decisions related to the storage of data in the array. it is hostile Parity calculation and majority determination can be done while data is being transferred between caches, but in other embodiments these operations can be performed at other times before or after this transfer occurs.

At step 560, the second page data is stored in the first cache, thus marking completion of the second activation operation. Since the second activation operation has completed, writing back of the first page data from the second cache to the array at step 570 can occur without interfering with the second activation operation. In some embodiments, post-write of the first page data does not occur until the second page data is loaded into the first cache, but in other embodiments, the post-write does not interfere with the ongoing second activation operation. Note that post-recording at the point in time may start sooner. In some embodiments, write-back includes inverting the bits in the page and setting an inversion flag to indicate whether the page of data has been inverted.

6 is a flowchart of a scenario in which the same page in a bank is sequentially activated twice. At step 610, a first activation command for a first page in a first bank is received. At step 620, in response to the first activation command, the first page data is retrieved from the array and stored in the first cache. As described above, opening the first page includes setting a flag for the first bank to indicate that a page in that bank is open. When the first page is open, read and write accesses to data in the first page are performed using the first cache. When those read and write accesses are complete, a pre-charge command corresponding to the first page may be received, but since the delay-after-write operations are performed within the memory device, the pre-charge command will cause the data to be moved from the first cache to the second. You can prevent it from being cached or written back to the memory array.

At step 630, a second activation command for a second page in the first bank is received. Since there is already a page open for the first bank, in step 640 the address for the first page is compared to the address for the second page. If it is determined at step 650 that the address for the first page matches the address for the second page, the method proceeds to step 660 where the first page data remains in the first cache. In addition to leaving the first page data in the first cache, any post-writes that normally occur as a result of the second activation command may also be blocked. Blocking the post-write of the first page data back into the array is such that if the portion of the array corresponding to the first page data remains in an intermediate state after the activation command, the last post-write of the first page data is not corrupted. ensure that intermediate states are preserved. For example, if the first page of data is read from the array using a self-referencing read that leaves all memory cells in a page of the array in a "0" or reset state, then a write back stores a "1" or set state. Only those memory cells are requested to be written to. If post-writing of the first page data is allowed to occur in response to the second activation command even if the data remains in the first cache, later writing back can request that all 0s or 1s be written back, so that Accordingly, the later post-write operation becomes complicated.

Thus, in conventional memory devices, closing the first page with a pre-charge command causes the data for the first page to be stored back into the memory array, but the delay-post-write embodiments described herein initiate a subsequent activation operation. The first page data remains in the first cache structure until If the second activation operation is for the same page that is already open, there is no need to fetch new data to store in the primary cache. Indeed, if self-referencing reads are used during activation operations, an attempt to fetch new data from the array will cause garbage data to be loaded into the primary cache. As such, if back-to-back accesses to the same page in the same bank occur, the memory device needs to do any data transfer to prepare the first cache for read and write accesses to the first page of data. No, because the data is still in the cache.

If it is determined at step 650 that the same page is not activated by the second activation command, the method proceeds to perform the actions necessary to facilitate the second activation command. At step 670, the first page data is passed from the first cache to the second cache, which may include parity calculation and majority determination, as described above. Also, at step 670, the second page data is retrieved from the array and stored in the first cache, thus making the second page data available for read and write accesses using the first cache. Finally, when the activation operation corresponding to the second page is completed or a completion stage is reached where post-writing of the first page data will not interfere with activation, post-writing of the first page data to the array takes place.

The flow diagram of FIG. 7 helps illustrate a scenario in which a post-write indication is received by a memory device, wherein the post-write indication is data corresponding to any open pages or closed pages awaiting post-write. informs the memory device that those pages need to be cleaned up so that is returned to non-volatile memory. To ensure that data in the memory device is stored in non-volatile storage, such an indication may be provided periodically to the memory device after ceasing activity.

At step 710, an indication for post-recording is received. As described above with respect to FIG. 4, the indication for post-write may be the receipt of a reset signal in step 712, the receipt of a store command in step 714, or a self-refresh mode in step 716. Receipt of a refresh signal or command that includes entry into In some embodiments, the write-back indication is automatically provided whenever the memory device enters a power-down mode. As also described above with respect to FIG. 4, a store command such as received at step 714 may indicate that one or more banks are to be acted upon. For example, if the memory device is about to be powered-down, a store command may be received indicating that all banks should be cleaned up so that any memory data currently stored in volatile storage is written back to the non-volatile array. can

After the indication for write-back is received in step 710, it is determined in step 720 whether the specific bank to which the indication for write-back belongs has an open page. If not, then there is no data corresponding to the bank currently in volatile storage, so post-write is not required. If at step 720 it is determined that the bank has an open page, at step 730 the data stored in the primary cache is transferred to the non-volatile array. The transfer at step 730 includes a direct transfer from the primary cache to the array, or if circuitry within the memory device is built such that data is routed through the secondary cache en route to the array, transfer at step 730 and moving data from the first cache to the second cache prior to writing back from the second cache. The transfer between caches or from one of the caches to the array may include parity calculation and majority determination as described above.

When the write-back occurring at step 730 involves multiple memory cells being written, the post-write may be divided into multiple steps. For example, after the first data portion is passed to the array in step 732, the second data portion is passed to the array in step 734. In a more specific example, a STORE-ALL command may be triggered prior to device shutdown. This STORE-ALL command can cause data corresponding to multiple banks to be written back to the array. To avoid the high peak power consumption and large current spikes associated with writing to many memory cells simultaneously, the post-write operations corresponding to the first half of the banks are performed in step 732, while the Write operations corresponding to the second half are performed in step 734 . In other embodiments, a portion of the memory cells in each bank is written during respective steps 732 and 734 such that post-write operations within each bank are staggered in time.

9 provides a flowchart corresponding to an operation of a memory device in which write-delay is supported and structural testing or calibration is performed. This calibration or testing typically occurs at startup. At step 572, a first command to access data in memory is received. In response to the first command, the memory determines at step 574 whether it is in a non-destructive mode of operation in which data stored within the non-volatile memory cells of the array are protected and must not be disturbed. If at step 574 it is determined that the memory is not in a non-disruptive mode of operation, at step 576 the first instruction is executed in the normal mode of operation. After executing the first command in the normal operating mode at step 576, the memory may continue normal operation based on the received commands.

If at step 574 it is determined that the memory is in non-destructive mode, at step 578 the data corresponding to the first instruction is not expected to be non-volatile with respect to data storage in a cache or other storage location on the memory. is accessed from Such data access can include reading and writing to storage locations, where a series of such write/read operations ranges over timing parameters to determine preferred settings for particular signals. It can be performed to sweep. Thus, while the memory is in a non-destructive mode, instructions associated with data accesses that cause data to be modified in non-volatile memory cells are executed using other storage on the memory if the memory is in a normal operating mode, so that non- Volatile storage becomes undisturbed. For example, read and write operations associated with calibrating data strobes or other timing parameters within a DDR interface can be performed using an on-memory cache instead of the memory array itself, so that stored non- A timing configuration for the memory device is established without corrupting volatile data.

At step 580, the memory is switched from a non-destructive mode to a normal operating mode. This transition may be in response to information received by the memory device, or may be based on an internal determination that a calibration procedure or other operation that benefits from a non-destructive mode has been completed. In one example, the memory includes a register that stores a value indicating whether the memory is in non-destructive mode. When the memory receives a command or signal that modifies a value in a register, this change in value may cause the memory to transition from a non-destructive mode to a normal operating mode.

In some embodiments, flags or status bits that track whether there is an open row for a particular bank are disabled during non-destructive mode. That is, storage used to store flags or status bits may be protected from modification, just as non-volatile memory cells are prevented from being overwritten in non-destructive mode. In these embodiments, because flags or status bits are cleared when exiting non-destructive mode, an incorrect indication of an open row may corrupt non-volatile data after the memory switches to normal operating mode. There is no fear of triggering a possible delay post-write operation.

In other embodiments, flags or status bits that can be set to indicate open pages of memory during execution of instructions when the memory is in a non-destructive mode may be set prior to responding to data access commands in a normal operating mode. Cleared at 582. In some embodiments, flags or status bits are cleared before entering normal operating mode, while in other embodiments, flags or status bits are cleared after entering normal operating mode.

As shown in steps 584 and 586, clearing the status bits involves detecting a change in the value indicating whether the memory is in non-destructive mode and then clearing the status bits based on the detected change. can be based on As noted above, a change in a value on memory may correspond to a change in a value in a mode register, where a change in value indicates a transition from a non-destructive mode to a normal operating mode for the memory. These registers may be modified, for example, by a mode register set command issued by the memory controller. Circuitry on memory may detect a change in value in a register and then clear flags or status bits in response.

In other embodiments, the memory clears status bits in response to a command received by the memory. In some cases, the command is a refresh, self-refresh, reset, or pre-charge command received before the memory exits non-destructive mode. As such, if such instructions potentially cause write-after-delay to occur, but the memory is still in non-destructive mode, the non-volatile data will be protected. In other embodiments, a command to specifically clear flags or status bits is received by the memory device, where no write-delay post-write is driven by this command to clear the status bits, so the command is non-delayed. -received before or after the transition from the disruptive mode to the normal operating mode. After an unintended delay, when the memory device enters normal operating mode and clears flags or status bits, it may overwrite data in non-volatile storage with garbage data from one of the cache structures left over from calibration operations. -Normal operation can proceed without worrying about the recording operation.

10 presents a flow diagram of a method for controlling a memory, which may be performed, for example, by a memory controller or other external object directing operations of the memory. At step 680, a mode change signal is provided to the memory to cause the memory to enter a non-destructive mode of operation that prevents data stored within the non-volatile memory array from being overwritten. In some embodiments, the mode change signal corresponds to a mode register write that stores on memory a value that selects a non-destructive mode. In other embodiments, a dedicated signal or sequence of signal transitions is used to provide the mode change signal. In still other embodiments, the memory defaults to a non-destructive mode of operation when power is turned on, so there is no need to provide a mode change signal to the memory.

At step 682, while the memory device is in the non-destructive mode, a plurality of calibration commands are issued to the memory device. In some examples, calibration commands are read and write commands associated with calibrating one or more signals used for communication between a memory controller and memory. For example, the calibration commands may follow a series of write and read commands using slightly different timing for the data strobe (e.g., DQS) signal to determine the optimal timing for that signal. From the point of view of the memory controller, calibration commands may not be different from the commands used during normal operation (activate, read, write, pre-charge, etc...), but from the point of view of the memory, the commands are non-volatile on the memory. It is implemented in a way that does not disturb the memory array. As noted above, the memory preferably includes additional storage, such as one or more caches or volatile memory blocks, to support read and write operations during calibration or testing without the need to disturb the non-volatile array.

At step 684, after issuing the plurality of calibration commands to the memory, the memory controller causes the memory to exit non-destructive mode and clears any flags or status bits indicating that there are open pages on the memory. It provides a signal to the memory that makes it happen. By clearing the flags or status bits, the memory controller will ensure that a calibration or testing procedure performed while the memory is in non-destructive mode does not result in unintentional write-back operations that corrupt non-volatile data. can As described above, in response to the memory controller issuing a register access command to the memory at step 686 and providing values to storage in registers on the memory device at step 688, the memory switches to a normal operating mode and You can clear flags or status bits. When stored on the memory, the value causes the memory to switch from a non-destructive mode to a normal operating mode. In other embodiments, the flags or status bits are cleared by issuing a reset, self-refresh, refresh, store, or pre-charge command to the memory before the memory transitions from a non-destructive mode to a normal operating mode. After issuing such a command, a mode change command may be provided to the memory at step 692, where the mode change command causes the memory to transition to a normal state after flags or status bits are cleared, and such flags or status bits are cleared. Status bits are used to indicate one or more open pages. In yet other embodiments, the memory controller signals the memory to change to a normal operating mode based on completion of calibration or testing operations or waits for the memory to automatically switch from a non-destructive mode to a normal operating mode, then delays Sends a command or signal to the memory instructing it to clear any flags or status bits corresponding to open pages prior to starting operations in a normal operating mode where write-back operations are used.

8 shows a circuit diagram associated with a portion of a memory device that includes the use of delay-post-write operations. A timing diagram below the schematic helps illustrate the functioning of the circuit. At startup, the OPEN signal 992 is low, thus indicating that no pages in the bank are open and thus the next activation is not waiting for post-write. When the /ACTIVATE signal 990 is first asserted low on edge 961, the ACTIVATE TIMING signal 993 is shown to transition from high to low on edge 966, which is used in the activation operation. represents the generation of a number of timing signals that are In the embodiment of FIG. 8 , these signals are signal transitions directly caused by a high-to-low transition of /ACTIVATE signal 990 and are generated by activation timing circuits block 951 .

When /ACTIVATE signal 990 returns high on edge 972 in the timing diagram, OPEN signal 992, the output of flip-flop 955, goes high. OPEN signal 992 is used to determine that a page is open and post-write to that page should be triggered upon receipt of a subsequent enable assertion. When OPEN signal 992 is high, so /ACTIVATE signal 990 deasserts high on edge 973, ACTIVATE TIMING signals 993, UPDATE TIMING signals 994, and WRITEBACK TIMING signals (995) Everyone goes from low to high. This occurs based on logic gates 952, 953, 956, 957, and 959, preparing those sets of timing signals for subsequent assertions when the next enable signal assertion occurs. Signals are prepared for assertion because it is known that the next activation will result in activation of the new page, parity/multiple update of the previous page, and post-write of the previous page.

When the next assertion of /ACTIVATE 990 occurs at edge 962, that assertion triggers the assertion of respective ACTIVATE TIMING signals 993, UPDATE TIMING signals 994, and WRITEBACK TIMING signals 995. do. Accordingly, timing signals for activating a new page are generated by activation timing circuits block 951 (edges 967), and timing signals for updating parity and majority information about a page that has been opened before are updated at the update timing. The signals generated by the circuits block 958 (edges 968) and used to post-write the previously opened page after update and activation are complete (WRITEBACK TIMING signals 995) are backwritten. Generated by timing circuits block 954 (edges 970). Upon deassertion of /ACTIVATE 990 at edge 973, each of the timing signal groups of signals is deasserted in preparation for the next activation. OPEN signal 992 remains high.

When RESET signal 991 is pulled high on edge 963, this indicates that any data stored in volatile memory should be written back to the array. In other embodiments, receipt of a refresh command or a STORE command may also trigger this post-write. The assertion of RESET resets flip-flop 955 and causes OPEN signal 992 to go low on edge 965. The transition of the OPEN signal 992 propagates through the circuit and causes the UPDATE TIMING signals 994 to assert (edges 969) and the WRITEBACK TIMING signals 995 to assert (edges ( 971)). Consequently, the timing signals cause the previously opened page to be updated (parity calculation and majority determination) and written back to the memory array.

By delaying the post-write of open pages of data to the bank until the subsequent activation operation is complete, the delay associated with writing data back into the array can be hidden, thereby improving the access timing associated with the device. This is because the memory does not have to wait for a post-write to occur before activating the next page, so that read/write operations to the newly opened page can occur while the post-write operation is performed in the background. there is. This concurrent performance of reads/writes and post-write of data to the array provides significant timing gain. Including the new operation code to support data post-write without requiring another activation operation helps ensure that data does not remain in non-volatile storage when a power-down occurs. In some instances, multiple pages of data can be written back into the array based on a single post-write indication, and the data post-write can be staggered to reduce peak power consumption.

Although exemplary embodiments have been provided above, it should be appreciated that many variations exist. Moreover, although described using spin-torque MRAM devices that include specific example arrangements of memory cells, these teachings are applicable to other memory devices having different structures to which the same concepts may be applied. Examples of such memory devices include other resistive memories and DRAMs. Such memories will benefit in terms of improved random access time, reduced power consumption, and increased data retention time.

The particular embodiments disclosed above are illustrative only and should not be taken as limiting, as the embodiments may be modified and realized in different but equivalent ways, which will be apparent to those skilled in the art having the benefit of the teachings herein. because it can Accordingly, the foregoing description is not intended to limit this disclosure to the particular form described, but on the contrary suggests that such alternatives, modifications, and equivalents may be included within the spirit and scope of the present invention as defined by the appended claims. Although intended to be encompassing, those skilled in the art will appreciate that various changes, substitutions, and changes may be made in their broad form without departing from the spirit and scope of the invention.

415: cache
470: status bits
450: control circuit
455 delay circuit

Claims (20)

As a memory
an array of non-volatile memory cells;
a register that stores a value, the value determining that the memory is in one of a normal mode and a non-destructive mode;
a status bit indicating whether a page in the array of non-volatile memory cells is open; and
a control circuit coupled to the array of non-volatile memory cells and the register, the control circuit comprising:
prevent write operations to the array of non-volatile memory cells when the memory is in the non-destructive mode;
receive an indication that the memory is transitioning from the non-destructive mode to the normal mode;
and in response to the indication that the memory is transitioning from the non-destructive mode to the normal mode, clearing the status bit, the indication being a change in the value of the register. According to claim 1,
wherein the memory further comprises mode change detection circuitry coupled to the register and the control circuitry, the mode change detection circuitry providing the indication that the memory is transitioning from the non-destructive mode to the normal mode. According to claim 1,
wherein the status bit is cleared regardless of whether a page in the array of non-volatile memory cells is closed. delete According to claim 1,
wherein the register is a mode register. According to claim 1,
Wherein the register defaults to a value corresponding to the non-destructive mode. According to claim 6,
wherein the memory automatically exits the non-destructive mode upon completion of a calibration procedure. According to claim 1,
a first cache coupled to the array and the control circuitry; and
a second cache coupled to the array and the control circuit;
The control circuit is:
In response to the first activation command corresponding to the first page:
pass first page data to the first cache at a first location in the array, the first page data corresponding to the first page;
set the status bit to indicate that there is an open page;
transfer the first page data from the first cache to the second cache;
After delivering the first page data to the second cache, in response to a second activation command:
pass second page data to the first cache at a second location in the array;
and transfer the first page data from the second cache to the first location in the array. According to claim 1,
When the memory is in the non-destructive mode, the control circuitry is configured to: and prevent write operations to the array of non-volatile memory cells. A method for operation of a memory comprising a non-volatile memory array and a first cache, comprising:
receiving a first command to access data in the memory;
In response to receiving the first command:
determining that the memory is in a non-destructive mode, wherein in the non-destructive mode, data stored in the non-volatile memory array is undisturbed;
accessing data in the first cache;
after accessing the data in the first cache, switching the memory from the non-destructive mode to a normal mode; and
in response to a change in the value stored in the register, the change indicating that the memory transitions from the non-destructive mode to the normal mode, and clearing status bits indicating open pages in the memory. , a method for the operation of memory. According to claim 10,
wherein a change in the value stored in the register is provided by mode change detection circuitry. According to claim 10,
wherein the status bits are cleared regardless of whether or not a page within the memory is closed. According to claim 10,
wherein the memory automatically exits the non-destructive mode upon completion of a calibration procedure. delete According to claim 10,
After switching the memory from the non-destructive mode to the normal mode:
receiving a first activation command and a first address corresponding to a first page in the memory;
In response to the first activation command:
retrieving first page data corresponding to the first page from the array of memory cells based on the first address;
storing the first page data in the first cache;
setting at least one of the status bits to indicate that there is a page open;
transferring the first page data from the first cache to a second cache in the memory;
after receiving the first activation command, receiving a second activation command and a second address corresponding to a second page in the memory;
In response to the second activation command:
retrieving second page data corresponding to the second page from the array of memory cells based on the second address;
storing the second page data in the first cache; and
and writing the first page data from the second cache to the array of memory cells at a location corresponding to the first address. As a method for controlling memory,
issuing a plurality of calibration commands to the memory, the plurality of calibration commands corresponding to a calibration sequence that is executed while the memory is in a non-destructive mode; ; and
After issuing the plurality of calibration commands, providing at least one signal to the memory, wherein providing the at least one signal to the memory comprises:
issuing a register access command to the memory; and
providing the memory with a value for storage in the register, wherein when storing in the register, the value causes the memory to transition from the non-destructive mode to a normal mode;
In response to the value stored in the register, the memory:
switch from the non-destructive mode to the normal mode;
A method for controlling a memory comprising clearing status bits on the memory indicating open pages in the memory. delete 17. The method of claim 16,
wherein the status bits are cleared regardless of whether a page in the memory is closed. 17. The method of claim 16,
wherein the memory automatically exits the non-destructive mode upon completion of a calibration procedure. 17. The method of claim 16,
before issuing the plurality of calibration commands to the memory, further comprising providing a mode change signal to the memory;
In response to the mode change signal, the memory enters the non-destructive mode.

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