CN100452239C - Semiconductor memory - Google Patents

Semiconductor memory Download PDF

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CN100452239C
CN100452239C CN 03824440 CN03824440A CN100452239C CN 100452239 C CN100452239 C CN 100452239C CN 03824440 CN03824440 CN 03824440 CN 03824440 A CN03824440 A CN 03824440A CN 100452239 C CN100452239 C CN 100452239C
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memory
mode
data
operation
signal
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CN1689113A (en
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松崎康郎
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富士通微电子株式会社
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045Read-write mode select circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622Partial refresh of memory arrays
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/406Refreshing of dynamic cells
    • G11C2211/4067Refresh in standby or low power modes

Abstract

多个标志被形成以对应于各自的存储器单元组,每个存储器单元组由多个易失性存储器单元组成。 A plurality of markers are formed to correspond to the respective memory cell groups, each composed of a plurality of memory cells composed of volatile memory cells. 每个标志指示存储器单元以第二存储器模式存储数据。 Each flag indicates the second memory cell stores data in the memory model. 在将模式从第一存储器模式改变到第二存储器模式的改变操作中,响应于对相应的存储器单元组的第一次访问,每个标志被复位,其中在第一存储器模式中由每个存储器单元独立地保持数据,而在第二存储器模式中,每个存储器单元组中的存储器单元保持相同数据。 In the memory mode is changed from the first mode to the second mode change operation in the memory, in response to a respective first access memory cells, each flag is reset, wherein the first memory in each memory by the mode unit is independently hold data, and in the second memory mode, each memory cell group of the memory cell remains the same data. 为此,在每个存储器单元组中,只有第一次访问是以第二存储器模式进行的。 For this purpose, in each memory cell group, only the first access mode is a second memory. 在上述改变操作中,通过以与标志一致的模式访问存储器单元,使得即使在改变操作期间,管理半导体存储器的系统也能够自由地访问存储器单元。 In the change operation, by accessing the memory cells identical to the flag pattern, so that even during the changing operation, the semiconductor memory management system is also able to freely access the memory cells. 结果,可以基本消除改变时间。 As a result, it can change the time basically eliminated.

Description

半导体存储器 The semiconductor memory

技术领域 FIELD

本发明涉及需要刷新操作来保持被写入存储器单元的数据的半导体存储器。 The present invention relates to a semiconductor memory requires refresh operations to retain data written in the memory unit.

背景技术. Background technique.

诸如蜂窝电话之类的手持终端需要的存储器容量逐年增加。 Such as cellular telephones, handheld terminal requires memory capacity increases year by year. 在这种情 In this case

况下,动态RAM (下文中称为DRAM)己经开始代替传统的静态RAM (下文中称为SRAM)被用作手持终端的工作存储器。 Under conditions, dynamic RAM (hereinafter referred to as DRAM) have begun to replace conventional static RAM (hereinafter referred to as SRAM) is used as a work memory of the handheld terminal. 由于DRAM的构成存储器单元的元件数量比SRAM少,所以其芯片尺寸可以做得比SRAM 小,并且其芯片成本可以比SRAM低。 Since the number of elements constituting the memory cell of the DRAM is less than SRAM, so that the chip size can be made smaller than the SRAM, and it may be lower than the cost of chip SRAM.

同时,安装在蜂窝电话上的半导体存储器的功耗必须低,以便允许长的电池持续时间。 Meanwhile, power consumption of a semiconductor memory mounted on a cellular phone must be low, in order to allow long duration battery. 与SRAM不同,DRAM需要周期性的刷新操作,以便保持被写入其存储器单元中的数据。 Unlike SRAM, a DRAM requires periodic refresh operations to maintain data is written in its memory cells. 因此,使用DRAM作为其工作存储器的手持终端即使当其未被使用时,仅为了保持数据也会消耗功率,使得电池被消耗。 Thus, a DRAM as a work memory of the handheld terminal even when it is not used, the data will be held only for the electric power consumption, so that the battery is consumed.

为了降低待机状态中(低功耗模式中)DRAM的功耗,已经开发了局部刷新技术和双单元技术。 To reduce power consumption in the standby state (low power mode) of a DRAM, partial refresh techniques have been developed and bi-cell technology. 日本未审査专利申请公开No. 2000-298982公开了局部刷新技术。 Japanese Unexamined Patent Application Publication No. 2000-298982 discloses a partial refresh technology. 日本未审查专利申请公开No. 2001-143463公开了双单元技术。 Japanese Unexamined Patent Application Publication No. 2001-143463 discloses a double-cell technology.

局部刷新技术限定在待机状态中要保持数据的存储器单元,从而减少要被刷新的存储器单元的数量。 The partial refresh technique defined in the standby state to the memory cell holding the data, thereby reducing the number of memory cells to be refreshed is. 要被刷新的存储器单元的数量减少会减少刷新操作的次数,使得可以降低待机功耗。 The number of memory cells to be refreshed reduction will reduce the number of refresh operation, making it possible to reduce standby power consumption.

在双单元技术中,分别被连接到互补位线上的两个存储器单元(存储器单元对)存储互补数据,使得存储器单元对所保持的电荷量加倍u由于两个存储器单元分别保持"H"数据和"L"数据,所以刷新周期是由"H"数据和"L"数据的数据保持时间中的较长一个来确定的。 In the two-cell technology, the two are connected to complementary bit lines of the memory cells (memory unit) stores complementary data, the memory unit such that the amount of charge held u doubled since two memory cells are held "H" data and "L" data, the refresh period is a long time determined by the data held "H" data and the "L" data. 这意味着最坏数据保持时间不是一个存储器单元的特性,而是两个存储器单元的特性的总和。 This means that the worst characteristic data holding time is not a memory cell, but the sum of the characteristics of the two memory cells. 另一方面,单个存储器单元中的刷新周期是由"H"数插和"L"数据的数据保持时间中的较短一个来确定的。 On the other hand, a single memory cell in a refresh cycle number is inserted from the "H" and "L" a short data in the data holding time is determined. 因此,双单元技术使用两个存储器单元来保持数据,使得即使这些存储器单元中的一个具有小泄漏路径时,另一个存储器单元也可以对此进行补偿。 Thus, the double cell technology using two memory cells to hold data, so that even if one of these memory cells having a small leak path, other memory cells may compensate for this. 下面是与本发明相关的传统技术参考文献。 The following is a conventional art references related to the present invention. 专利文献: Patent Document:

(1) 日本未审查专利申请公开No. 2000-298982 (1) Japanese Unexamined Patent Application Publication No. 2000-298982

(2) 日本未审査专利申请公开No. 2001-143463 (2) Japanese Unexamined Patent Application Publication No. 2001-143463

发明内容 SUMMARY

本发明的一个目的是降低具有易失性存储器单元的半导体存储器中用于保持数据的功耗。 An object of the present invention is to reduce volatile semiconductor memory having a memory cell for holding data of the power consumption.

本发明的另一个目的是实现从用于保存数据的操作模式到用于访问数据的模式的快速改变。 Another object of the present invention is to achieve a rapid change from the operating mode for storing data for access to the data mode.

根据本发明的半导体存储器的一个方面,多个存储器单元组中的每个组由分别与预定数量的字线连接的多个易失性存储器单元组成。 According to one aspect of the semiconductor memory of the present invention, a plurality of memory cells each composed of a plurality of volatile memory cells are connected to a predetermined number of word lines of the composition. 控制电路执行第一存储器模式和第二存储器模式的操作,第一存储器模式是其中每个存储器单元独立地保持数据的模式,第二存储器模式是其中每个存储器 The control circuit performs a first operation mode and a second memory storage mode, the first mode is a memory wherein each memory cell, independently of the data holding mode, the second mode is a memory wherein each memory

单元组中的存储器单元保持相同数据的模式。 The cell group of memory cells holding the same data model. 第二存储器模式是其中结合了所述局部技术和双单元技术的模式,并且在该模式中,第一存储器模式中所保持的数据被多个存储器单元部分地保持。 Second storage mode is a mode wherein a combination of the local and dual cell technology, and in this mode, the first mode of the memory data held by a plurality of memory cells holding part. 因此,第二存储器模式中的存储器单元的数据保持时间比第一存储器模式的长。 Thus, the second data storage mode of the memory cell retention time is longer than a first storage mode. 结果,存储器单元 As a result, the memory cell

的刷新频率可以被大大降低,从而可以降低功耗。 The refresh rate can be greatly reduced, thereby reducing power consumption.

被形成以分别对应于各个存储器单元组的多个标志中每个标志作为置位状态指示存储器单元以第二存储器模式保持数据。 It formed to correspond to the respective plurality of flag memory cells of each token in the second memory holding data mode as the set state indicates a memory cell. 在将全部存储器单元的状态从第二存储器模式改变到第一存储器模式的改变操作中,标志复位电路响应于对相应的存储器单元组的第一次访问,将标志复位。 In the state of all memory cells of the memory is changed from the second mode to the first memory mode change operation, the flag reset circuit in response to the first visit to the respective memory cell groups, the flag is reset. 这保证了对每个存储器单元组的第一次访问是在第二存储器模式中执行的。 This ensures that the first visit to each of the memory cells of the memory are performed in the second mode.

在第二存储器模式中,多个存储器单元存储相同的数据,使得刷新周期被加长,相比于第一存储器模式,这可能降低每个存储器单元的存储量(例如,电荷量)。 In a second mode memory, a plurality of memory cells store the same data, so that the refresh cycle is lengthened, compared to the first memory mode, which may reduce the storage capacity of each memory cell (e.g., charge amount). 因此,存在如下风险:在改变操作中,如果在第一存储器模式中执行第一次访问,数据可能会丢失。 Therefore, there is a risk: changing operation, if performed in the first mode, the first memory access, data may be lost. 在第二存储器模式中执行第一次访问可以防止被访问的存储器单元中的数据丢失。 Performing a first access to data memory cells can be prevented from being accessed in the memory is lost in the second mode.

对作为在第二存储器模式中的访问单位的每个存储器单元组形成标志。 Flag for each memory cell is formed as a group in the second mode memory access unit. 这使得可以对每个被访问的存储器单元判断存储器单元是在哪个模式中保持数据的。 This makes it possible to keep the data in which mode each memory cell of the memory cell being accessed is determined. 换句话说,这允许在改变操作期间同时存在以第二存储器模式保持数据的存储器单元和以第一存储器模式保持数据的存储器单元。 In other words, this allows the presence of data in the second memory holding pattern memory unit and a memory unit holding data in the first memory during a mode changing operation simultaneously. 如果在改变操作期间以与标志一致的模式访问存储器单元,则即使在改变操作期间,管理半导体存储器的系统也被允许自由地访问存储器单元。 If during access memory cells identical to the flag changing mode during operation, even if the change operation, the semiconductor memory management system is also allowed to freely access a memory cell. 结果,可以消除实际的改变时间。 As a result, the actual change time can be eliminated.

根据本发明的半导体存储器的另一种模式,标志置位电路在改变操作 According to another mode of the semiconductor memory of the present invention, the flag setting circuit changing operation

之前将全部所述标志置位。 Before the full flag. 这保证了全部存储器单元组的存储器单元从第二存储器模式转移到第一存储器模式。 This ensures that all of the memory cells of the memory cells transferred from the second memory mode to the first mode memory.

根据本发明的半导体存储器的另一种模式,当存储器单元被访问时, 标志检测电路检测相应的标志是否被置位。 According to another mode of the semiconductor memory of the present invention, when the memory cell is accessed, the corresponding flag is a flag detecting circuit is set. 控制电路根据标志检测电路的检测结果,执行第一存储器模式和第二存储器模式中的一种的操作。 The control circuit based on the detection result of the mark detection circuit performs one of the first memory and the second memory mode operation modes. 由标志检测电路检测标志的状态有助于控制电路的操作,使得可以简化其电路。 A mark detection circuit detects the state flag helps to control operation of the circuit, so that the circuit can be simplified.

根据本发明的半导体存储器的另一种模式,当第一次访问是写操作时,控制电路从被选择的存储器单元组的全部存储器单元读取数据,以将所读取的数据写回被选择存储器单元组的全部存储器单元。 According to another mode of the semiconductor memory of the present invention, when the first access is a write operation, the control circuit reads data from the memory cells of all the memory cell group is selected, the read data is written back to the selected all memory cells of the memory cells. 即,在第二存储器模式中所保持的数据被再次以第二存储器模式写回多个存储器单元。 That is, in the second mode, the memory data is held in the plurality of memory cells written back again in the second memory mode. 由于数据的回写,数据被牢靠地写入存储器单元。 Since the write-back data, the data is written to the memory cell reliably. 此后,数据被写入到被指定为写目标的存储器单元。 Thereafter, data is written to is specified as the write target memory cell. 即,数据被以第一存储器模式写入指定的存储器单元。 That is, data is written to the memory cell in the first memory specified mode. 没有被指定为写目标的存储器单元组中的存储器单元保持原始数据。 Is not designated as a write target memory cells of the memory cell remains in the original data. 因此,即使当给出了对在第二存储器模式中保持数据的存储器单元 Thus, even when a given memory cell data is held in the second memory mode

之一的写指令时,也可以将新的写数据保持在预定的存储器单元中,而没有原始数据的任何丢失。 When one of the write command, may be the new write data is held in a predetermined memory cell, the original data without any loss. 此后,以第一存储器模式的刷新周期执行刷新擦作,使得即使当以第一存储器模式执行对其的下一访问时,数据也可以从存储器单元中的任何一个中读出。 Thereafter, the first memory refresh cycle to perform a refresh mode for wiping, such that even when performing a next access to its memory in a first mode, data can be read from any memory cell in a. 结果,即使在改变操作期间,当执行写 As a result, even during changing operation, when a write

操作时,系统也不需要等待。 In operation, the system does not need to wait.

根据本发明的半导体存储器的另一种模式,读出放大器经由位线与存储器单元连接。 According to another mode of the semiconductor memory of the present invention, the sense amplifier via bit lines connected to the memory cell. 在从存储器单元读取数据、将数据写回存储器单元以及向存储器单元写入数据的时候,控制电路保持读出放大器激活。 When reading data from the memory cell, the write data and write data back to the memory cells of the memory cell, the control circuit holds the activation of the sense amplifier. 因此,可以 Therefore,

降低读出放大器的激活频率,以縮短写操作所需的时间。 Reducing the frequency of reading activation of the amplifier, to shorten the time required for the write operation.

根据本发明的半导体存储器的另一种模式,在写操作中,字控制电路在读出放大器激活的时候使得字线不被选择,该字线被连接到存储器单元组中除了被指定为写目标的存储器单元之外的存储器单元。 According to another mode of the semiconductor memory of the present invention, in a write operation, the word control circuit when the sense amplifier is activated so that the word line is not selected, the word line is connected to the memory cell group is specified as the write target addition memory cells other than the memory cell. 写数据没有被发送到与不被选择的字线连接的存储器单元。 The write data is not sent to the memory cells connected to the selected word line is not of. 因此,利用简单的控制,可以在读出放大器激活的时候,执行第二存储器模式中的数据回写操作,以及第一存储器模式中的数据写入操作。 Thus, with a simple control, when the sense amplifier can be activated, a second data memory performs a write operation mode, a first memory and a data write operation mode back.

根据本发明的半导体存储器的另一种模式,当第一次访问是读操作时,控制电路从存储器单元组的全部存储器单元读取数据,以将所读取的数据输出到半导体存储器的外部部分,并且将所读取的数据写回存储器单元。 The outer portion of another mode of the semiconductor memory of the present invention, when the first access is a read operation, the control circuit reads data from all the memory cells of memory cells, the read data is output to the semiconductor memory , and the read data is written back into memory cells. 即,在第二存储器模式中所保持的数据被以第二存储器模式再次写回多个存储器单元。 That is, in the second memory mode data is held in the second memory write-back mode, a plurality of memory cells again. 因此,即使在改变操作期间,当执行读操作时,系统也不需要等待。 Thus, even during the changing operation, when the read operation is performed, the system does not need to wait.

根据本发明的半导体存储器的另一种模式,当第一次访问是刷新操作时,控制电路从被选择的存储器单元组中的全部所述存储器单元读取数据,以将所读取的数据写回存储器单元。 According to another mode of the semiconductor memory of the present invention, when the refresh operation is first accessed, the control circuit reads data from the memory cell selected cell group in all of the memory, the read data written back to the memory cells. 即,在第二存储器模式中所保持的数据被以第二存储器模式再次写回多个存储器单元。 That is, in the second memory mode data is held in the second memory write-back mode, a plurality of memory cells again. 由于标志响应于第一次访问而被复位,所以存储器单元组中的每个存储器单元此后操作在第—存储器模式中。 Since the flag in response to the first visit is reset, the memory cell groups of each memory cell after the first operation - the memory mode. 由于写回数据的刷新操作,数据被牢靠地写入进行了刷新操作的每个存储器单元,并且随后的刷新操作以第一存储器模式的刷新周期执行。 Refresh operation since the write back data, the data is written securely performed each memory cell refresh operation, and the refresh operation performed subsequent to the first memory refresh cycle mode. 因此,即使当每个存储器单元此后以第一存储器模式被访问时,也可以安全地读取或刷新数据。 Therefore, even when each memory cell in the first memory mode after being accessed, may be safely read or refresh the data.

根据本发明的半导体存储器的另一种模式,半导体存储器具有:正常操作模式,其中半导体存储器根据外部提供的访问命令以及内部生成'的刷 According to another mode of the semiconductor memory of the present invention, a semiconductor memory having: a normal operating mode, wherein a semiconductor memory, and internally generated 'brushes according to an externally supplied access command

新命令进行操作;和数据保持模式,其中半导体存储器仅根据刷新命令进 The new operation command; and a data retention mode in which only the semiconductor memory according to the refresh command into

行操作。 Line operations. 在正常操作模式期间,数据以第一存储器模式进行存储,在数据保持模式期间,数据以第二存储器模式进行存储。 During normal operation mode, data is stored in a first memory mode, during the data hold mode, data is stored in the second memory mode. 即使当第一存储器模式中的存储器单元和第二存储器模式中的存储器单元同时存在时,应用了本发明的系统也能够在从数据保持模式转移到正常操作模式之后立即访问半导体存储器。 Even when the first memory unit and the memory mode, the second memory mode memory cells exist, the system to which the present invention can also be accessed from the semiconductor memory immediately after the data holding mode to the normal operation mode. g卩,系统可以高速操作。 g Jie, the system can operate at high speed.

根据本发明的半导体存储器的另一种模式,存储器单元组的存储器单元包括局部存储器单元,所述局部存储器单元存储在第二存储器模式期间被保持的数据。 According to another mode of the semiconductor memory of the present invention, the memory cell group of memory cells includes a local memory unit, the data unit is stored in local memory during the second mode is held in the memory. 在从正常操作模式转移到数据保持模式之后,每次生成刷新命令时,控制电路就执行公共刷新操作,该公共刷新操作读取局部存储器单元中所存储的数据,以将所读取的数据写入存储器单元组的全部存储器单元,直到全部存储器单元组的状态转移到第二存储器模式。 After the transfer of data from the normal operation mode to the hold mode, each time a refresh command is generated, the control circuit executes a refresh operation common, the common refresh operation to read data stored in the local memory unit to write the read data all memory cells in the memory cell group until the status of all memory cells is transferred to the second memory mode. 通过公共刷新操作,以第一存储器模式存储在局部存储器单元中的数据可以以第二存储器模式被存储在存储器单元组的存储器单元中。 By common refresh operation mode to the first memory data stored in the local memory cells in the second memory mode may be stored in memory cells of the memory cell group. 每次执行刷新操作时,第一存储器模式中的存储器单元的状态就被转变为第二存储器模式, 这使得能够有效地从正常操作模式改变到数据保持模式。 Each time the refresh operation is performed, a first state of the memory cell to the memory mode is converted into the second memory mode, which makes it possible to effectively change the normal operation mode to the data hold mode.

根据本发明的半导体存储器的另一种模式,与单条字线连接的单个存储器单元以第一存储器模式保持一位数据。 According to another mode of the semiconductor memory of the present invention, a single memory cell connected to the single word line in a first memory holding a data mode. 存储器单元组的全部存储器单元以第二存储器模式保持一位数据。 All memory cells of memory cells of the second memory holding a data mode. 这使得可以通过选择单条字线或者多条字线,容易地访问第一存储器模式或第二存储器模式中的存储器单元。 This makes it possible by selecting a single word line or multiple word lines to easily access the first memory or the second mode, memory mode memory cells.

附图说明 BRIEF DESCRIPTION

图1是示出了本发明的半导体存储器的第一实施例的框图。 FIG. 1 is a block diagram showing a first embodiment of a semiconductor memory of the present invention.

图2是示出了图l所示的操作模式控制电路的细节的框图。 FIG 2 is a block diagram showing details of the mode of operation of the control circuit shown in Figure l. 图3是示出了图2所示的操作模式控制电路的操作的时序图。 3 is a diagram illustrating the mode of operation shown in the timing chart of operation of the control circuit. 图4是示出了图1所示的刷新定时器的细节的框图。 FIG 4 is a block diagram showing the details of the refresh timer shown in FIG.

图5是示出了第一实施例中的刷新定时器和刷新命令发生器的操作的时序图。 FIG 5 is a diagram showing a first embodiment of the refresh timer and a refresh timing diagram illustrating operation of the command generator.

图6是示出了图1所示的刷新地址计数器的细节的框图。 FIG 6 is a block diagram showing the details of the refresh address counter shown in FIG.

图7是示出了图6所示的刷新地址计数器的复位电路的操作的时序图。 FIG 7 is a timing chart illustrating the operation of the refresh address counter reset circuit 6 shown in FIG.

图8是示出了图6所示的刷新地址计数器的操作的说明图。 FIG 8 is an explanatory view illustrating the operation of the refresh address counter shown in FIG. 6.

图9是示出了图1所示的存储器核心的基本部分的细节的框图。 FIG 9 is a block diagram showing details of the essential part of a memory core shown in FIG.

图10是示出了图9所示的1/4字译码器的细节的电路图。 FIG 10 is a circuit diagram showing details of the quarter word decoder shown in Fig.

图11是示出了图9所示的读出放大器和预充电电路的细节的电路图。 FIG 11 is a circuit diagram illustrating the details of the read amplifier and precharge circuit 9 shown in FIG.

图12是示出了图1所示的读出放大器控制电路和预充电控制电路的操作的时序图。 FIG 12 is a diagram showing a read timing chart shown in FIG. 1 and FIG amplifier control circuit operation of the precharge control circuit.

图13是示出了在图1中示出的标志电路和标志检测电路的细节以及 13 is a diagram illustrating a detail of FIG. 1 shown in the circuit and a flag mark detection circuit and

字译码器的基本部分的细节的电路图。 Circuit diagram showing the details of the essential part of the word decoder.

图14是示出了局部刷新操作后的正常操作模式中的标志电路和标志 14 is a diagram illustrating a circuit and a flag Flag normal operating mode after a partial refresh operation

检测电路的操作的时序图。 Timing diagram illustrating operation of the detection circuit.

图15是示出了局部刷新操作后的正常操作模式中的标志电路和标志 FIG 15 is a diagram showing flags flag circuit and a normal operation mode after the refresh operation in the local

检测电路的另一操作的时序图。 Timing chart showing another operation of the detection circuit.

图16是示出了局部刷新操作后的正常操作模式中的标志电路和标志 FIG 16 is a flag and flag circuit normal operation mode after the partial refresh operation is shown in

检测电路的另一操作的时序图。 Timing chart showing another operation of the detection circuit.

图17是示出了局部刷新操作后的正常操作模式中的标志电路和标志 FIG 17 is a circuit diagram illustrating a flag and a normal operation mode flag after the partial refresh operation

检测电路的另一操作的时序图。 Timing chart showing another operation of the detection circuit.

图18是示出了图l所示的标志复位电路的细节的电路图。 FIG 18 is a circuit diagram showing details of the flag reset circuit shown in Figure l.

图19是示出了图18所示的标志复位电路的操作的时序图。 FIG 19 is a timing chart illustrating the operation flag is reset circuit 18 shown in FIG.

图20是示出了第一实施例中在正常操作模式期间的操作的时序图。 FIG 20 is a timing chart illustrating operation of the embodiment during the normal operation mode of the first embodiment.

图21是示出了第一实施例中在正常操作模式期间的操作的时序图。 FIG 21 is a timing chart illustrating operation of the embodiment during the normal operation mode of the first embodiment.

图22是示出了第一实施例中在局部刷新模式期间的操作的时序图。 FIG 22 is a timing chart illustrating operation of the embodiment during the partial refresh mode of the first embodiment.

图23是示出了在第一实施例中的当操作模式再次从正常操作模式改 FIG 23 is a diagram showing a first embodiment when the operation mode is changed from the embodiment in the normal operation mode again

变到低功耗模式时的操作的时序图。 Timing diagram illustrating operation of the time is changed to low-power mode. 图24是示出了在返回到正常操作模式之后,顺序生成刷新请求的示例的时序图。 FIG 24 is a timing diagram illustrating a return to normal operating mode after sequentially generating a refresh request is exemplary.

图25是示出了在返回到正常操作模式之后,在第一刷新请求£前提供了读命令的示例的时序图。 FIG 25 is a diagram showing after returning to the normal operation mode, a timing chart showing an example of a first read command before the refresh request £.

图26是示出了在返回到正常操作模式之后,在第一刷新请求之前提供了写命令的示例的时序图。 FIG 26 is a diagram showing after returning to the normal operation mode, a timing diagram of an example of the write command before the first refresh request.

图27是示出了外部命令周期时间EXTC与内部读周期时间IRD之间的关系的说明图。 FIG 27 is an explanatory diagram showing a relationship between the external command EXTC cycle time and the internal read cycle time IRD.

图28是示出了外部命令周期时间EXTC与内部写周期时间IWR1之 FIG 28 is a diagram showing the external command EXTC cycle time and the write cycle time of IWR1

间的关系的说明图。 Illustrating the relationship between.

图29是示出了外部命令周期时间EXTC与内部写周期时间IWR2之 FIG 29 is a diagram showing the external command EXTC cycle time and the write cycle time of IWR2

间的关系的说明图。 Illustrating the relationship between.

图30是示出了第一实施例中的伪SRAM的操作的时序图。 FIG 30 is a timing chart illustrating the operation of the pseudo SRAM of the first embodiment.

图31是示出了本发明的半导体存储器的第二实施例的框图。 FIG 31 is a block diagram illustrating a second embodiment of a semiconductor memory of the present invention.

图32是示出了图31所示的刷新定时器的细节的框图。 FIG 32 is a block diagram showing details of the refresh timer 31 shown in FIG.

图33是示出了第二实施例中的刷新定时器和刷新命令发生器的操作 FIG 33 is a diagram illustrating the operation of the second embodiment of the refresh timer and a refresh command generator

的时序图。 The timing diagram.

图34是示出了图31所示的刷新地址计数器的细节的框图。 FIG 34 is a block diagram showing details of the refresh address counter 31 shown in FIG. 图35是示出了图34所示的刷新地址计数器的操作的说明图。 FIG 35 is an explanatory view illustrating the operation of the refresh address counter 34 shown in FIG. 图36是示出了图31所示的存储器核心的基本部分的细节的框图。 FIG 36 is a block diagram showing details of the essential part of the memory core 31 shown in FIG. 图37是示出了图36所示的1/4字译码器的细节的电路图。 FIG 37 is a circuit diagram showing details of the quarter word decoder 36 shown in FIG. 图38是示出了图31所示的读出放大器控制电路和预充电控制电路的操作的时序图。 FIG 38 is a timing chart illustrating the readout amplifier shown in FIG. 31 controls the operation of the control circuit and a precharge circuit.

图39是示出了在图31中示出的标志电路和标志检测电路的细节以及字译码器的基本部分的细节的电路图。 FIG 39 is a circuit diagram illustrating details of the essential part of the details and the word decoder 31 shown in FIG circuit and a flag mark detection circuit.

图40是示出了图31所示的标志复位电路的细节的电路图。 FIG 40 is a circuit diagram showing the details of the flag reset circuit 31 shown in FIG. 图41是示出了第二实施例中的正常操作模式期间的操作的时序图。 FIG 41 is a timing chart illustrating the operation during normal operation mode of the second embodiment in FIG. 图42是示出了第二实施例中的命令刷新模式期间的操作的时序图。 FIG 42 is a timing chart illustrating the operation of the second embodiment during the refresh mode command. 图43是示出了第二实施例中的局部刷新模式期间的操作的时序图。 FIG 43 is a timing chart illustrating the operation of the second embodiment during the partial refresh mode.

具体实施方式 Detailed ways

下面将使用附图描述本发明的实施例。 The embodiments are described below using the present invention. 在附图中,由粗线示出的每条信号线表示它是由多条线组成的,粗线的信号线所连接的每个块由多个电 In the drawings, each signal line shown by a bold line indicates that it is composed of a plurality of lines, each thick line block signal line is electrically connected by a plurality of

路组成。 Roads. 以"z"结尾的每个信号代表正逻辑,以"/"开头的每个信号或者以"X"结尾的每个信号代表负逻辑。 In "z" end of each represents a positive logic signal, the signal at the beginning of each "/" to each signal representative of or "X" at the end of a negative logic. 附图中的双圆圈代表外部接线 Double circles represent in the drawings the external connection

端。 end. 信号线由与指代通过其传输的信号名称的参考符号相同的参考符号指 A signal line by the reference symbols referred to by the name of its signal transmission means of the same reference symbols

代。 generation. 在下面的描述中,信号名称有时被简写,例如"时钟信号CLK"写为"CLK信号","芯片使能信号CE"写为"CE信号"。 In the following description, signal names may be abbreviated, for example, "the CLK clock signal" is written as "the CLK signal", "the chip enable signal CE" is written as "CE signal."

图l示出了本发明的半导体存储器的第一实施例。 Figure l shows a first embodiment of the semiconductor memory of the present invention. 使用CMOS技术, 该半导体存储器被形成为具有DRAM存储器单元和SRAM接口的伪SRAM。 Using CMOS technology, the semiconductor memory is formed as a pseudo SRAM having a DRAM memory cells and SRAM interfaces. 伪SRAM不用接收任何外部刷新命令就在芯片内部周期性地执行刷新操作,以保持被写入存储器单元的数据。 Pseudo SRAM without receiving any external refresh command periodically perform a refresh operation inside the chip, to keep the data written in the memory cell. 该伪SRAM例如被用作安装在蜂窝电话上的工作存储器。 This pseudo SRAM is used as, for example, a work memory mounted on a cellular phone.

该伪SRAM具有命令译码器10、操作模式控制电路12、刷新定时器14、刷新命令发生器16、刷新地址计数器18、地址缓冲器20、数据输入/ 输出缓冲器22、多路转换器24、标志复位电路26、标志检测电路28、标志电路30 (标志置位电路)、核心控制电路32和存储器核心34。 The pseudo SRAM has a command decoder 10, an operation mode control circuit 12, a refresh timer 14, a refresh command generator 16, a refresh address counter 18, an address buffer 20, the data input / output buffer 22, multiplexer 24 , flag reset circuit 26, the mark detection circuit 28, flag circuit 30 (flag setting circuit), a core 32 and a memory core control circuit 34. 操作模式控制电路12和核心控制电路32作为执行第一和第二存储器模式中的操作的控制电路迸行操作,这些模式将在后面进行描述。 Operation mode control circuit 12 and a core control circuit 32 as a control circuit into line memory to perform operations of the first and second modes of operation, these modes will be described later.

命令译码器10经由外部接线端接收命令信号(芯片使能信号CE、写使能信号/WE和输出使能信号/OE),以译码所接收的命令,并输出读控制信号RDZ或者写控制信号WRZ。 The command decoder 10 receives a command signal via the external terminal (chip enable signal CE, a write enable signal / WE and an output enable signal / OE), for decoding the received command, and outputs a read control signal RDZ or write control signal WRZ. 此外,命令译码器IO与CE信号的下降沿同步地输出局部模式开始信号PREFS (脉冲信号),并与CE信号的上升沿同步地输出局部模式释放信号PREFR (脉冲信号)。 In addition, the falling edge of the command decoder output signals IO and CE synchronization start signal PREFS partial mode (pulse signal), and outputs the partial mode release signal PREFR (pulse signal) in synchronization with the rising edge of the CE signal.

操作模式控制电路12根据局部模式开始信号PREFS、局部模式释放信号PREFR和刷新控制信号REFZ,输出模式信号MODEl、 MODE2、 MODE3。 The operating mode control circuit 12 partial mode start signal PREFS, PREFR local mode release signal and the refresh control signal REFZ, the output signal mode MODEl, MODE2, MODE3. 刷新定时器14输出具有根据模式信号M0DE1〜3确定的振荡周期的刷新请求信号TREF。 Timer 14 outputs the refresh request signal TREF in accordance with refresh mode signal determined M0DE1~3 oscillation cycle. 当在读控制信号RDZ或者写控制信号WRZ之前接收到刷新请求信号 When the read control signal RDZ before the write control signal WRZ or a refresh request signal is received

TREF时,刷新命令发生器16与刷新请求信号TREF同步地输出刷新命令信号REFZ。 TREF, the refresh command generator 16 outputs the refresh request signal in synchronization with the refresh command TREF signal REFZ. 当在读控制信号RDZ或者写控制信号WRZ之后接收到刷新请求信号TREF时,刷新命令发生器16输出跟随在响应于RDZ信号而执行的读操作之后或者响应于WRZ信号而执行的写操作之后的刷新控制信号REFZ。 Refresh after after when after the read control signal RDZ or write control signal WRZ receiving the refresh request signal TREF, refresh command 16 output of the generator to follow in response to a read operation to the RDZ signal is performed or in response to a write operation to a WRZ signal performed control signal REFZ. 这意味着刷新命令发生器16操作为仲裁器,其确定读操作/写操作与刷新操作的优先顺序。 This means that the refresh command generator 16 operating as an arbiter to determine the read / write operation priorities and the refresh operation.

刷新地址计数器18与刷新控制信号REFZ同步地更新刷新地址信号REFAD (R5〜0)。 Refresh address counter 18 updates the refresh control signal REFZ refresh address signal REFAD (R5~0) synchronization. 更新刷新地址信号REFAD的规范根据模式信号MODE2〜3而改变。 Updating the refresh address signal REFAD specification vary depending on the mode signal MODE2~3. 刷新地址信号REFAD的位的数量对应于存储器核心34中所形成的字线WL的数量(该示例中是64线)。 The number of bits of the word line refresh address signal REFAD corresponding to the memory core 34 formed in the WL number (64 in this example is a line). 因此,刷新控制信号REFZ的位的数量并不限于6位,而是根据存储器核心34中所形成的字线WL的数量而设定。 Thus, the number of bits of the refresh control signal REFZ is not limited to six, but the word line is set according to the memory core 34 formed in the number of WL.

地址缓冲器20经由地址接线端接收地址信号AD,以将所接收的信号输出为行地址信号RAD (高位(high-order)地址)和列地址信号CAD (低位(low-order)地址)。 Address buffer 20 receives an address signal AD through an address terminal, the output signal of the received signal as a row address RAD (high (high-order) address) and column address signals CAD (low (low-order) address). 这意味着该伪SRAM是同时接收高位地址和低位地址的地址非多路转换型存储器。 This means that the pseudo-SRAM is an address simultaneously receives the high address and low address non-multiplexed type memory.

数据输入/输出缓冲器22经由公共数据总线CDB接收读数据,以将所接收的数据输出到数据接线端DQ,并经由数据接线端DQ接收写数据, 以将所接收的数据输出到公共数据总线CDB。 The data input / output buffer 22 receives read data through a common data bus CDB, the received data is output to the DQ terminals of the data, and receives write data via the DQ data terminal, the received data output to the common data bus CDB. 数据接线端DQ的位的数量例如是16位。 The number of bits of the data terminal DQ is 16 bits, for example.

多路转换器24当刷新控制信号REFZ处于高电平时,将刷新地址信号REFAD输出为行地址信号RAD2,而当刷新控制信号REFZ处于低电平时,将行地址信号RAD输出为行地址信号RAD2。 Multiplexer 24 when the refresh control signal REFZ is at high level, the refresh address signal REFAD output the RAD2 row address signal, when the refresh control signal REFZ is at low level, the output of the row address signal RAD as the row address signal RAD2.

标志复位电路26当接收到标志检测信号FDTC时,根据行地址信号RAD2的最低位X0,输出标志复位信号FRAX或FRBX。 When the flag is reset circuit 26 receives the detection signal FDTC flag, in accordance with the least significant bit X0 of the row address signal RAD2, the output flag reset signal FRAX or FRBX. 标志电路30与译码信号XDX同步地输出其所保存的一对标志的值,分别作为标志输出信号S1AZ、 S1BX。 Flag circuit 30 and outputs the decoded signal in synchronization XDX a flag value of one of its stored, respectively as a flag output signal S1AZ, S1BX. 标志电路30与局部模式释放信号PREFR的脉冲同步地对标志置位,而与标志复位信号FRAX、 FRBX的脉冲同步地对标志复位。 Flag circuit 30 with the local pulse mode release signal PREFR the flag is set, and the flag reset signal FRAX, FRBX synchronization reset pulse in synchronization flag. 标志检测电路2S当接收标志输出信号S1AX、 S1BX时,输出标志检 When the mark detection circuit receives the flag output signal 2S S1AX, S1BX, the output detection flag

测信号FDTC。 Sensing signal FDTC.

核心控制电路32具有寄存器36、定时控制电路38、读出放大器控制电路40和预充电控制电路42。 The core control circuit 32 has a register 36, a timing control circuit 38, the sense amplifier control circuit 40 and the precharge control circuit 42. 当刷新命令发生器16先于读控制信号RDZ或写控制信号WRZ输出刷新控制信号REFZ时,寄存器36临时保持读控制信号RDZ或者写控制信号WRZ。 When the refresh command generator 16 prior to the read control signal RDZ or write control signal WRZ outputs the refresh control signal REFZ, the register 36 temporarily holds the read control signal RDZ or write control signal WRZ. 定时控制电路38当接收RDZ信号、WRZ信号和REFZ信号中的一个信号时,输出行激活信号RASZ。 The timing control circuit 38 when a signal received signals RDZ, WRZ, and REFZ signal is the signal output line activation signal RASZ. 读出放大器控制电路40与RASZ信号同步地输出读出放大器激活信号PSA、 NSA,用于激活读出放大器SA。 The sense amplifier control circuit 40 outputs a sense amplifier activation signals PSA, NSA, for activating the sense amplifier SA RASZ in synchronization with the signal. 当存储器核心34未进行操作时, 预充电控制电路与RASZ信号同步地输出预充电信号PREZ。 When the memory core 34 is not operated, the precharge control circuit outputs a signal RASZ in synchronization with the precharge signal PREZ. 读出放大器控制电路40和预充电控制电路42的操作定时根据刷新地址信号REFAD 的最低位XO的值和模式信号M0DE2而改变。 The sense amplifier control circuit 40 and precharge control operation of the timing circuit 42 is changed according to the value of the least significant bit and the mode signal XO M0DE2 of the refresh address signal REFAD.

存储器核心34具有读出放大器SA、预充电电路PRE、存储器单元阵歹IJALY、字译码器WDEC、列译码器CDEC、读出缓冲器SB和写放大器WA。 The memory core 34 has a sense amplifier SA, the precharge circuit PRE, the memory cell array bad IJALY, the word decoder WDEC, a column decoder CDEC, a sense buffer SB, and a write amplifier WA. 读出放大器SA根据读出放大器激活信号PSA、 NSA而操作。 Sense amplifier SA operates in accordance with the sense amplifier activation signals PSA, NSA. 预充电电路PRE根据预充电信号PREZ而操作。 The precharge circuit PRE operates in accordance with the precharge signal PREZ. 存储器单元阵列ALY具有多个易失性存储器单元MC (动态存储器单元;下文中也称为COO、 C10 等),以及连接到存储器单元MC上的多个字线WL和多个位线BL。 ALY memory cell array having a plurality of volatile memory cells MC (dynamic memory cells; hereinafter also referred to as COO, C10, etc.), and memory cells MC connected to the plurality of word lines WL and a plurality of bit lines BL. 与典型DRAM的存储器单元相同的每个存储器单元MC具有用于将数据作为电荷进行保持的电容器,以及设置在该电容器与位线BL之间的传输晶体管。 Typical DRAM memory cells MC the same as each memory cell having a capacitor for holding data as a charge and a transfer transistor disposed between the capacitor and the bit line BL. 传输晶体管的栅极连接到字线WL。 Gate of the transfer transistor is connected to the word line WL.

字译码器WDEC根据行地址信号RAD2、模式信号MODE3和标志检测信号FDTC,选择字线WL中的一条或两条,以将所选择的字线WL的电压提高到预定的高电压。 The word decoder WDEC the RAD2 row address signal, a mode signal and a flag detection signal MODE3 FDTC, select one or two of the word lines WL, the voltage of the word line WL is increased to the selected predetermined high voltage. 与字线WL的选择同步地,字译码器WDEC 输出与每个所选择的字线WL相对应的译码信号XDX。 Selection of the word lines WL in synchronization with the word decoder WDEC outputs each of the word line WL corresponding to the selected decoded signal XDX.

根据列地址信号CAD、列译码器CDEC输出列线信号(后面在图4 中描述的CLZ),用于接通分别连接位线BL和数据总线DB的列开关中的一个(后面在图4中描述的SCW)。 The column address signal CAD, the column decoder CDEC outputs a column line signal (CLZ described later in FIG. 4), for turning on column switches respectively connected to the bit line BL and data bus DB in a (later in FIG. 4 SCW) is described. 读出缓冲器SB放大数据总线DB 上的读数据的信号大小,以将其输出到公共数据总线CDB。 Buffer size read signal SB amplifies the read data on the data bus DB to output it to the common data bus CDB. 写放大器WA 放大公共数据总线CDB上的写数据的信号大小,以将其输出到数据总线DB。 Write amplifier WA amplifies the write data size of the signal on the common data bus CDB, to output it to the data bus DB.

图2示出了图1所示的操作模式控制电路12的细节。 Figure 2 shows a mode of operation shown in FIG. 12 of the control circuit details. 操作模式控制电路'12具有计数器12a和模式信号发生器12b。 '12 operation mode control circuit includes a counter 12a and a pattern signal generator 12b. 计数器Ua与刷新控制信号REFZ的上升沿同步地执行计数操作,以在第64个计数操作时输出计数器信号CNT64。 Counter and the rising edge of the refresh control signal REFZ Ua performing a counting operation in synchronization, to output a counter signal CNT64 at the 64th count operation. 计数器12a响应于复位信号RESET而被复位。 Counter 12a in response to the reset signal RESET is reset. 当模式信号M0DE1或者模式信号MODE3是高电平时,输出复位信号RESET。 When the mode signal or a mode signal MODE3 M0DE1 is high, it outputs a reset signal RESET.

顺带提及,计数的次数"64"对应于存储器核心34中所形成的字线WL的数量。 Incidentally, the counted number of times "64" corresponds to the number of word lines in the memory core 34 is formed in the WL. 在该实施例中,为了更容易理解说明,字线WL的数量假定为64,但是实际形成的字线WL的数量可以例如是2048。 In this embodiment, for easier understanding of the explanation, the number of word lines WL is assumed to be 64, but the actual word line WL is formed, for example, the number may be 2048. 在该情况中, 计数器48a在第2048个计数操作时输出计数器信号。 In this case, the counter 48a of the output signal when the counter 2048 count operation.

模式信号发生器12b根据局部模式开始信号PREFS、局部模式释放信号PREFR和计数器信号CNT64,输出模式信号MODE1〜3。 The pattern signal generator 12b partial mode start signal PREFS, partial mode release signal and the counter signal PREFR CNT64, the output signal mode MODE1~3.

图3示出了图2所示的操作模式控制电路12的操作。 FIG 3 shows the operation mode of the control operation shown in FIG. 2 circuit 12.

本实施例的伪SRAM当CE信号处于高电平时,在正常操作模式中, 而当CE信号处于低电平时,在数据保持模式(低功耗模式)中。 Pseudo SRAM of this embodiment when the CE signal is at a high level in the normal operation mode, when the CE signal is at the low level, the data holding mode (low power mode). 在数据保持模式开始时,执行公共刷新操作(公共刷新模式),并且在公共刷新操作之后执行局部刷新操作(局部刷新模式)。 When the data holding mode is started, the refresh operation performed common (common refresh mode), and performs a partial refresh operation (partial refresh mode) after the common refresh operation.

正常操作模式期间的刷新操作是依照读出放大器SA的操作,对每个位线BL的一个存储器单元MC执行的(单单元操作)。 Refresh operation during normal operation mode in accordance with operation of the readout amplifier SA, (single unit operation) performed on each bit line BL of a memory cell MC. 数据保持模式期间的刷新操作是依照读出放大器SA的操作,对每个位线BL的两个存储器单元MC执行的(双单元操作)。 Data holding mode during refresh operation is in accordance with the readout operation amplifier SA, (two unit operations) performed on each bit line BL, two memory cell MC. 换句话说,在正常操作模式中, 一次刷新操作中选择一条字线WL,而在数据保持模式中, 一次刷新操作中选择两条字线。 In other words, in the normal operation mode, a refresh operation, a selected word line WL, and the data holding mode, selecting two word lines in a refresh operation. 数据保持模式是所谓的局部刷新技术和双单元技术的结合。 Data hold mode is a combination of a so-called two-unit and the partial refresh art technology. 因此,相比于现有技术,数据保持模式期间的功耗被大大降低了。 Thus, compared to the prior art, power consumption during the data retaining mode is greatly reduced.

伪SRAM当模式信号MODE1处于高电平时,识别出正常操作模式, 当模式信号MODE2处于高电平时,识别出公共刷新模式(数据保持模式),而当模式信号MODE3处于高电平时,识别出局部刷新模式(数据 When the pseudo-SRAM at a high level when the mode signal MODE1 recognizes that normal operating mode, when the mode signal MODE2 is at a high level, the common refresh mode identified (data holding mode), when the MODE3 signal is at a high level mode, partial identification refresh mode (data

保持模式)。 Hold mode).

在数据保持模式之前的正常操作模式中,除了特殊情况之外,存储器 In the normal operation mode before the data holding mode, except in special cases, the memory

单元中的数据以第一存储器模式进行保持。 Data unit is held in the first memory mode. 特殊情况是这样的情况:'操作模式在从数据保持模式返回到正常操作模式之后立即转移到数据保持模式,如后面描述的图23所示。 A special case is a case: after the transfer 'from the data holding mode of operation mode returns to the normal operation mode to the data holding mode Now, FIG. 23 as described later.

在公共刷新模式中,存储器单元中的数据以第一存储器模式或者第二存储器模式进行保持。 In the common refresh mode, the memory cell data is held in the first memory or the second mode, memory mode. 更具体地说,在公共刷新模式中,每次生成刷新请求时,存储器单元的状态顺序地从第一存储器模式转移到第二存储器模式。 More specifically, when the common refresh mode, the refresh request is generated every time the state of the memory cell is sequentially transferred from the first memory to the second memory mode mode.

在局部刷新模式中,存储器单元中的数据被保持在第二存储器模式中。 In partial refresh mode, the data storage unit is held in the second memory mode. 在局部刷新模式之后的正常操作模式中,存储器单元中的数据以第二存储器模式中或第一存储器模式进行保持。 In the normal operation mode after the partial refresh mode, the memory cell data in a second memory holding a first mode or in memory mode. 具体地说,在局部刷新模式之后的正常操作模式中,每次访问(外部访问命令或者刷新命令)时,存储器单元的状态顺序地从第二存储器模式转移到第一存储器模式。 More specifically, when the normal operation mode after the partial refresh mode, each access (external access command or the refresh command), the state of the memory cell is sequentially transferred from the second memory mode to the first mode memory.

当在正常操作模式期间接收局部模式设定信号PREFS时,操作模式控制电路12将模式信号M0DE1、 MODE2分别改变到低电平和高电平, 以将操作模式从正常操作模式转移到公共刷新模式(图3 (a))。 When receiving the local mode setting signal PREFS during a normal operating mode, the operating mode control circuit 12 sets the mode signal M0DE1, MODE2 are changed to the low level and high level to the operation mode from the normal operation mode to the common refresh mode ( FIG. 3 (a)). 与模式信号MODE1的低电平同步地去活复位信号RESET。 The mode signal MODE1 and low deactivation synchronization reset signal RESET.

响应于复位信号RESET的低电平,计数器12a从复位状态释放,以开始与刷新控制信号REFZ同步的计数操作(图3 (b))。 In response to the reset signal RESET is low level, the counter 12a is released from the reset state to start the counting operation of the refresh control signal REFZ in synchronization (FIG. 3 (b)). 响应于刷新控制信号REFZ,执行刷新操作。 In response to the refresh control signal REFZ, perform a refresh operation. 在公共刷新模式中,由于需要选择存储器核心34的全部字线WL,所以刷新控制信号REFZ被输出64次。 In the common refresh mode, the memory core because of the need to select all the word lines WL 34, so refresh control signal REFZ is outputted 64 times. 用于生成刷新命令信号REFZ的刷新命令发生器18和刷新定时器14的操作将在后面描述的图35中进行描述。 FIG REFZ signal for generating a refresh command generator 18 of the refresh command and the refresh operation of the timer 14 will be described later in 35 will be described.

计数器12a与第64个计数操作同步地输出计数器信号CNT64 (图3 (c))。 12a and the second counter 64 outputs the count operation of the counter synchronization signal CNT64 (FIG. 3 (c)). 操作模式控制电路12与计数器信号CNT64同步地将模式信号MODE2和模式信号MODE3分别改变到低电平和高电平(图3 (d))。 Operation mode signal control circuit 12 and the counter CNT64 mode signal and the mode signal MODE2 synchronization MODE3 were changed to the low level and high level (FIG. 3 (d)). 然后,操作模式从公共刷新模式转移到局部刷新模式。 Then, the operation mode shifts from the common refresh mode to the partial refresh mode. 与模式信号MODE3向高电平的改变同步地激活复位信号RESET (图3 (e))。 The mode changes to the high level signal MODE3 is activated in synchronization with the reset signal RESET (FIG. 3 (e)). 当接收复位信号RESET的高电平时,计数器12a被复位。 When receiving the high level reset signal RESET, the counter 12a is reset. 在模式信号MODE3 处于高电平的时段期间,顺序执行局部刷新操作。 During MODE3 mode signal at a high level period, the partial refresh operations performed sequentially.

响应于经由外部接线端提供的CE信号向高电平的改变,输出肩部模式释放信号PREFR (图3 (f))。 In response to the high level to change the CE signal supplied via external terminals, the output signal mode release shoulder PREFR (FIG. 3 (f)). 当在局部刷新模式期间接收局部模式释放信号PREFR时,操作模式控制电路12将模式信号MODE3、 MODE1分别改变到低电平和高电平,并相应地将操作模式转移到正常操作模式(图3 (g))。 Upon receiving a local mode release signal PREFR during the partial refresh mode, the operating mode control circuit 12 sets the mode signal MODE3, the MODE1 changed to low and high levels, respectively, and accordingly the operation mode shifts to the normal operation mode (FIG. 3 ( g)).

图4示出了图l所示的刷新定时器14的细节。 Figure 4 shows a detail of the refresh timer shown in FIG. L 14.

刷新定时器14具有振荡器14a,分频器14b、 Mc、 14d以及多路转换器14e,其中振荡器14a生成振荡信号OSC0,分频器14b、 14c、 14d对OSC0信号进行分频,以分别生成振荡信号OSCl、 OSC2、 OSC3,多路转换器14e根据模式信号MODE1〜3,选择振荡信号OSCl、 OSC2、 OSC3 中的一个,以将其作为刷新请求信号TREF输出。 Refresh timer 14 has an oscillator 14a, divider 14b, Mc, 14d and 14e multiplexer, wherein the oscillator generates an oscillation signal OSC0 14a, divider 14b, 14c, 14d of OSC0 signal frequency, respectively generates an oscillation signal OSCl, OSC2, OSC3, multiplexer 14e according to the mode signal MODE1~3, select the oscillation signal OSCl, OSC2, OSC3 a in order to be used as outputs the refresh request signal TREF. 分频器14b、 14c、 14d 将OSC0信号的频率分别转换为八分之一、十六分之一和三十二分之一。 A frequency divider 14b, 14c, 14d OSC0 frequency signals are converted to, one eighth, one sixteenth, and one thirty second. 图5示出了刷新定时器14和刷新命令发生器16的操作。 Figure 5 illustrates the operation of the refresh timer 14 and a refresh command generator 16. 当模式信号M0DE1、 MODE2或MODE3处于高电平时,刷新定时器14分别输出振荡信号OSCl、 OSC2或OSC3作为刷新请求信号TREF。 When the mode signal M0DE1, MODE2 MODE3 or at a high level, the refresh timer 14 outputs an oscillation signal OSCl, OSC2 or OSC3 as the refresh request signal TREF. 当模式信号M0DE1或MODE3处于高电平时,刷新命令发生器16将刷新请求信号TREF输出为刷新控制信号REFZ。 When the mode signal MODE3 M0DE1 or at a high level, the refresh command generator 16 outputs the refresh request signal TREF refresh control signal REFZ. 当模式信号MODE2处于高电平时,刷新命令发生器16与刷新请求信号TREF同步地输出刷新控制信号REFZ两次。 When the mode signal MODE2 is at the high level, the refresh command generator 16 outputs the refresh request signal TREF refresh control signal REFZ in synchronization twice.

图6示出了图1所示的刷新地址计数器18的细节。 FIG 6 shows details of the refresh address counter 18 shown in FIG.

刷新地址计数器18具有复位电路18a,计数器18b、 18c以及控制计数器18b、 18c的逻辑门。 Refresh address counter 18, the counter 18b, 18c and a control counter 18b, 18c having a reset logic gate circuit 18a. 复位电路18a具有与刷新控制信号REFZ的下降沿同步地生成正脉冲的脉冲发生器、与脉冲发生器的输出信号同步地锁存模式信号MODE2的D触发器,以及检测模式信号MODE2的上升沿的NAND门。 Reset circuit 18a generates a positive pulse having a pulse generator in synchronization with the falling edge of the refresh control signal REFZ, the latches in synchronism with the rising edge of the output signal of the pulse generator mode signal MODE2 D flip-flop, and the detecting mode signal MODE2 NAND gate.

计数器18b与刷新控制信号REFZ同步地执行计数操作,以生成刷新地址信号REFAD的最低位R0。 Counter 18b and performs refresh signal REFZ in synchronization with the counting operation, to generate a refresh address signal REFAD lowest bits R0. 计数器18b当模式信号MODE3处于高电 Counter 18b when the mode signal is at a high MODE3

平时与模式信号MODE2的上升沿同步地被复位。 Usually the rising edge of the mode signal MODE2 synchronization is reset.

当模式信号MODE3处于高电平时,计数器18c与刷新控制信号REFZ同步地执行计数操作,以更新刷新地址信号REFAD的位R5〜i。 When the mode signal MODE3 at a high level, the counter 18c and the refresh control signal REFZ performs a counting operation in synchronization to update the refresh address signal REFAD is R5~i bit. 当模式信号MODE1或MODE2处于高电平时(除去模式信号MODE2的上升沿之后的预定时段之外),计数器18c与从计数器18b输出的地址信号R0同步地执行计数操作,以更新位R5〜1 。 When the mode signal MODE1 or MODE2 is at high level (outside of the predetermined period of time after the rising edge of the mode signal MODE2 removed), the counter 18c R0 address signal outputted from the counter 18b performs counting operation in synchronization to update the bit R5~1.

图7示出了图6所示的复位电路18a的操作。 FIG 7 illustrates an operation of the reset circuit 18a shown in Fig.

脉冲发生器与刷新控制信号REFZ的下降沿同步地输出脉冲信号到节点ND1 (图7 (a) ) 。 And the falling edge of the refresh control signal REFZ in synchronization with a pulse generator output pulse signal to the node ND1 (FIG. 7 (a)). D触发器与节点ND1处的脉冲信号同步地锁存模式信号MODE2,以输出模式信号MODE2的反逻辑到节点ND2 (图7 D flip-flop in synchronization with the latch pulse signal at the node ND1 mode signal MODE2, a reverse logic output mode signal MODE2 to node ND2 is (FIG. 7

(b))。 (B)). 相应地,在模式信号MODE2改变到高电平之后,节点ND2与第一个刷新控制信号REFZ同步地改变到低电平(图7 (c))。 Accordingly, after the mode signal MODE2 changes to the high level, the node ND2 of the first refresh control signal REFZ changes to low level (FIG. 7 (c)) in synchronism. 然后,模式信号MODE2和节点ND2的逻辑电平的与逻辑被输出到节点ND3 (图7 Then, the logic level of the mode signal MODE2 and the logic of the node ND2 to the node ND3 is output (FIG. 7

(d))。 (D)). 在节点ND3的高电平时段期间,即在模式信号MODE2改变到高电平之后的第一次刷新操作的时段期间,图6所示的计数器18b被复位。 During the first period after the refresh operation during a period of high level of the node ND3, i.e., changes in the mode signal MODE2 to a high level, the counter shown in FIG. 6 18b is reset.

图8示出了图6所示的刷新地址计数器18的操作。 Figure 8 illustrates the operation of the refresh address counter 18 shown in FIG. 6.

当模式信号MODE1或MODE2处于高电平时,即在正常操作模式和公共刷新模式期间,刷新地址计数器18与刷新控制信号REFZ同步地将刷新地址的6个位R5〜0顺序地加起来。 When the mode signal MODE1 or MODE2 at a high level, i.e., during the normal operation mode, refresh mode and the common refresh address counter 18 with 6 bits R5~0 refresh control signal REFZ sequentially in synchronization with the refresh address add up. 此外,当模式信号MODE3处于高电平时,即在局部刷新模式期间,刷新地址计数器18与刷新控制信号REFZ同步地将刷新地址的5个位R5〜1顺序地加起来。 Further, when the MODE3 signal is at a high level mode, i.e., during partial refresh mode, the refresh address counter 18 and the refresh control signal REFZ in synchronization with the refresh R5~1 5 bits of the address are sequentially added together. 此时,刷新地址信号RO被固定到低电平。 At this time, the refresh address signal RO is fixed to the low level.

图9示出了图1所示的存储器核心34的基本部分的细节。 Figure 9 shows a detail of an essential part shown in FIG. 34 of the memory core.

存储器核心34的字译码器WDEC具有1/4字译码器44和多个分别与主字线MW (MW0, MW1,...)相对应的子字译码器46a。 The memory core 34 of the word decoder WDEC has a quarter-word decoder 44, respectively, and a plurality of main word line MW (MW0, MW1, ...) corresponding to the sub-word decoders 46a.

当模式信号MODE3和标志检测信号FDTC处于低电平时,1/4字译码器44根据行地址信号RAD2的两个低位XI、 X0及其相反位/Xl、 /X0, 输出译码信号Xll、 XIO、 XOl、 X00中的一个。 When the mode signal and a flag detection signal MODE3 FDTC at a low level, 1/4 word decoder 44 in accordance with the lower two row address signal RAD2 of XI, X0 and the opposite bit / Xl, / X0, the output decoded signal XI1, XIO, XOl, X00 one. 当模式信号MODE3和标志检测信号FDTC中的一个处于高电平时,1/4字译码器44根据行地址信号RAD2的一个低位X1及其相反位/X1,输出两个译码信号Xll、 X10或者XOl、 XOO。 When a MODE3 signal is at high level and the mode flag detection signal of FDTC, 1/4 word decoder 44 in accordance with a row address signal RAD2 lower bit X1 and opposite bits / X1, it outputs two decode signals Xll, X10 or XOl, XOO. 1/4字译码器44操作为执行后面将描述的第一和第二存储 44 1/4 word decoder operation will be described later to perform the first and second storage

器模式的操作的控制电路。 The control circuit of the operation mode.

当主字线MW (MW0, MW1,...)处于高电平时,各个子字译码器46a被激活,以根据译码信号Xll、 XIO、 XOl、 XOO,从子字线SW (SW0P, SW1, SW2P, SW3,...)中进行选择。 When the main word line MW (MW0, MW1, ...) at a high level, each of the sub-word decoders 46a is activated in accordance with the decoded signal Xll, XIO, XOl, XOO, from the sub-word line SW (SW0P, SW1 , SW2P, SW3, ...) carried out the selection. 根据行地址信号RAD2 的高位,主字线MW被未示出的预译码器选择。 The upper row address signal RAD2, the selected main word line MW is not shown predecoder. 然后,连接到所选择的子字线SW上的存储器单元MC被访问。 Then, connected to the selected sub-word line SW memory cell MC is accessed. 因而,在本实施例中,图l所示的每条字线WL由主字线和子字线SW构成。 Accordingly, in the present embodiment, each of the word line WL Figure l shown comprises a main word line and sub-word line SW.

连接到相邻的两条子字线(例如,SW0P、 SW1)上的存储器单元构成了各个局部区域PA (存储器单元组;每个粗虚线框)。 The memory cells connected to two adjacent sub-word lines (e.g., SW0P, SW1) constituting a respective local area PA (memory cells; each coarse dashed box). 在局部区域PA 中,与位线BL (BLO, BL1, ...) 、 /BL (/BL0, /BL1,…)连接的存储器单元被连接到彼此不同的子字线SW上。 In the local area PA, the bit line BL (BLO, BL1, ...), / BL (/ BL0, / BL1, ...) connected to the memory cells are connected to each other in different sub-word line SW.

以"P"结尾的子字线SW代表局部字线。 "P" or the end of the sub-word line SW representative of the local word lines. 在数据保持模式期间,与局部字线SWP连接的存储器单元(例如,局部存储器单元COO, COl, ..., C0m)中所写入的数据被保持。 During the data holding mode, the memory cells connected to local word lines SWP (e.g., local memory cells COO, COl, ..., C0m) written data is maintained. 没有以"P"结尾的子字线SW 代表公共字线。 No sub-word line SW "P" representing the end of the common word line. 在数据保持模式期间,与公共字线SW连接的存储器单元MC (例如,公共存储器单元CIO, Cll,…,Clm)中的数据不被保持。 During the data holding mode, the memory cells MC connected to a common word line SW (e.g., the common memory unit CIO, Cll, ..., Clm) data is not held.

局部字线SWP和常规子字线SW交替布置。 SWP local word line and a conventional sub-word line SW alternately arranged. S卩,字线SWP、 SW彼此相邻布置。 S Jie, word lines SWP, SW are arranged adjacent to each other. 如后面将描述的,在数据保持模式期间,字线SWP、 SW被同时选择,使得两个存储器单元被同时访问(双单元操作)。 As will be described later, during a data holding mode, the word line SWP, SW are simultaneously selected, so that two memory cells are accessed simultaneously (two unit operations). 因此,这些字线SWP、 SW彼此相邻的布置避免了字译码器WDEC中的线路布图的复杂化。 Thus, the SWP word lines, disposed adjacent to each other to avoid the complexity SW word decoder WDEC of the layout of the circuit. 具体地说,这种布置便于设计子字译码器46a的线路布图。 Specifically, this arrangement facilitates design of the sub-word decoder circuit layout of Figure 46a.

在本实施例中,存储器核心34中所形成的存储单元MC中的一半是局部存储器单元。 In the present embodiment, half of the memory cell MC in the memory core 34 is formed in the local memory unit. 因此,在数据保持模式期间,保持了与伪SRAM的存储容量的一半相对应的数据。 Thus, during a data holding mode, the holding and pseudo SRAM half the storage capacity corresponding to data.

互补位线BL (BLO, BL1, ...) 、 /BL (/BL0, /BL1,…)连接到同一读出放大器SA和预充电电路PRE。 A complementary bit line BL (BLO, BL1, ...), / BL (/ BL0, / BL1, ...) are connected to the same sense amplifier SA and the precharge circuit PRE. 此外,位线BL、 /BL经由列开关 Further, the bit lines BL, / BL via the column switch

CSW连接到数据总线DB。 CSW is connected to the data bus DB. 列开关CSW由列选择信号CL (CL0, CLl,...)接通,其中列选择信号CL (CL0, CL1,...)是译码后的列地址信号CAD。 Column switch CSW by the column selection signal CL (CL0, CLl, ...) is turned, wherein the column selection signal CL (CL0, CL1, ...) is the column address signal CAD decoded. 读出放大器SA和预充电电路PRE将在后面描述的图U'中详细描述。 FIG amplifier SA and the precharge circuit PRE will be described later reads U 'is described in detail.

图10示出了图9所示的1/4字译码器44的细节。 Figure 10 shows a detail of a quarter word decoder 44 shown in Fig.

1/4字译码器44具有译码器44a和掩码电路44b,译码器44a对行地址信号X0、 XI、 /X0、 /XI译码,以生成译码信号Xll、 XIO、 XOl、 XOO,掩码电路44b当模式信号MODE3或者标志检测信号FDTC处于高电平时,对行地址信号X0、 /X0进行掩码,以输出高电平到译码器44a。 1/4 word decoder 44 has a mask circuit 44a and a decoder 44b, the decoder 44a to the row address signal X0, XI, / X0, / XI decoded to generate a decoded signal Xll, XIO, XOl, XOO, when the mask circuit 44b when the mode signal or a flag detection signal MODE3 FDTC at the high level, the row address signals X0, / X0 is masked, to output a high level to the decoder 44a.

图11示出了图9所示的读出放大器SA和预充电电路PRE的细节。 Figure 11 shows a detail of the readout amplifier SA and the precharge circuit PRE shown in Fig.

读出放大器SA具有:两个CMOS反相器,它们的输入和输出彼此连接;pMOS晶体管(pMOS开关),将CMOS反相器的pMOS晶体管的源极连接到电源线VDD;和nMOS晶体管(nMOS开关),将CMOS反相器的nMOS晶体管的源极连接到地线SS。 The sense amplifier SA has: two CMOS inverters whose inputs and outputs are connected to each other; pMOS transistor (pMOS switch), a source electrode connected to the pMOS transistor of the CMOS inverter to the VDD power supply line; and an nMOS transistor (nMOS switch), the source of the nMOS transistor of the CMOS inverter is connected to the ground line SS. CMOS反相器的输入(或者输出)分别连接到位线BL、 /BL。 CMOS inverter input (or output) are connected to bit lines BL, / BL. 当读出放大器激活信号PSA处于低电平时,pMOS开关导通,当读出放大器激活信号NSA处于高电平时,nMOS 开关导通。 When the sense amplifier activation signal PSA is at low level, the pMOS switch is turned on when the sense amplifier activation signal NSA is at high level, the nMOS switch is turned on. pMOS开关和nMOS开关的导通使得CMOS反相器被激活,并且位线BL、 /BL之间的电压差被差分放大。 ON pMOS switch and the nMOS switch is activated so that the CMOS inverter, and the voltage difference between the bit lines BL, / BL is differentially amplified.

预充电电路PRE具有将位线BL、 /BL彼此连接的nMOS晶体管,和分别将位线BL、 /BL连接到预充电电压线VPR上的nMOS晶体管。 The precharge circuit PRE with the bit lines BL, / BL connected to each other nMOS transistor, respectively, and the bit lines BL, / BL are connected to a precharge voltage line on the nMOS transistor VPR. 当预充电信号PREZ处于高电平时,nMOS晶体管导通,以将位线BL、 /BL连接到预充电电压线VPR。 When the precharge signal PREZ is at high level, the nMOS transistor is turned on to connect the bit lines BL, / BL to the precharge voltage line VPR.

图12示出了读出放大器控制电路40和预充电控制电路42的操作。 Figure 12 illustrates the operation of the sense amplifier control circuit 40 and precharge control circuit 42.

在从RASZ信号的上升沿开始的延迟时间DLY1之后,读出放大器控制电路40改变读出放大器激活信号PSA、 NSA,以激活读出放大器SA, 而不管模式信号MODE2的逻辑电平如何(图12 (a、 b))。 After a delay time from the rising edge of the start signal RASZ DLY1, the read amplifier control circuit 40 changes the sense amplifier activation signals PSA, NSA, to activate the sense amplifier SA, regardless of the logic level of the mode signal MODE2 how (FIG. 12 (a, b)). 图中的"ON" 、 "OFF"分别表示读出放大器SA.的激活和去活。 Figure "ON", "OFF" indicates a sense amplifier SA, respectively. The activation and deactivation. 与RASZ信号的上升沿同步地,预充电控制电路42将预充电信号PREZ改变到低电平, 以停止预充电操作,而不管模式信号MODE2的逻辑电平如何(图12 With a rising edge signal RASZ in synchronization with the precharge control circuit 42 changes the precharge signal PREZ to a low level, to stop the precharge operation, regardless of the logic level of the mode signal MODE2 how (FIG. 12

(C、 d))。 (C, d)).

当模式信号MODE2处于低电平时,在从RASZ信号的上升沿开始的延迟时间DLY2之后,读出放大器控制电路40改变读出放大器激活信号PSA、 NSA,以使读出放大器SA去活(图12 (e))。 When the mode signal MODE2 is at a low level, after a delay time from the rising edge of the start signal RASZ DLY2, the read amplifier control circuit 40 changes the sense amplifier activation signals PSA, NSA, so that the sense amplifier SA is deactivated (FIG. 12 (e)). 当模式信号MODE2处于低电平时,在从RASZ信号的上升沿开始的延迟时间DLY2 之后,预充电控制电路42将预充电信号PREZ改变到高电平,以开始预充电操作(图12 (f))。 When the mode signal MODE2 is at a low level, after a delay time from the rising edge of the start signal RASZ DLY2, precharge control circuit 42 changes the precharge signal PREZ to high level to start the precharge operation (in FIG. 12 (f) ).

当模式信号MODE2处于高电平时,在行地址信号X0改变到高电平之后,从RASZ信号的上升沿开始的延迟时间DLY2之后,读出放大器控制电路40改变读出放大器激活信号PSA、 NSA,以使读出放大器SA去活 When the mode signal MODE2 is at a high level, the row address signals X0 after the change to high level after the delay time from the start of the rising edge of the signal RASZ DLY2, the sense amplifier control circuit 40 changes the sense amplifier activation signals PSA, NSA, so that the sense amplifier SA to go live

(图12 (g))。 (FIG. 12 (g)). 当模式信号MODE2处于高电平时,在行地址信号XO改变到高电平之后,从RASZ信号的上升沿开始的延迟时间DLY2之后,预充电控制电路42改变预充电信号PREZ,以开始预充电操作(图12 When the mode signal MODE2 is at a high level, the row address signal changes to the high level after the XO, after a delay time from the rising edge of the start signal RASZ DLY2, precharge control circuit 42 changes the precharge signal PREZ, the precharge operation to begin (FIG. 12

(h))。 (H)).

简而言之,在公共刷新模式期间,为了将局部存储器单元C00中所保持的数据写入到局部存储器单元和相邻的公共存储器单元CIO,读出放大器SA被激活,而RASZ信号被输出两次,并且位线BL、 /BL的预充电被禁止。 Briefly, during the common refresh mode, to be written in the local memory cells C00 to a local data held in the memory cells and the memory cells adjacent to the CIO public, the sense amplifier SA is activated, and the signal is output two RASZ times, and the bit lines BL, / BL to the precharge is disabled. 更具体地说,与当行地址信号X0是偶数时所输出的刷新控制信号REFZ同步地锁存在读出放大器SA中的数据被保持,直到与行地址信号X0改变到奇数之后所输出的刷新控制信号REFZ相对应的操作。 More specifically, when the row address signal X0 and the refresh control signal REFZ is outputted even number latched read data in synchronization with the sense amplifier SA is maintained until the refresh control signal to change the row address signals X0 to the odd output after REFZ corresponding operation.

图13示出了在图l中所示的标志电路30和标志检测电路28的细节以及字译码器WDEC的基本部分的细节。 Figure 13 shows a detail of the detail of the basic portion 28 and the word decoder WDEC of flag circuit 30 and a mark detection circuit shown in Figure l.

标志电路30具有为各个主字线MW (MW0, MW1,...)提供的标志FAX (F0AX, F1AX,…)、FBX (F0BX, F1BX,…)。 FAX flag 30 has a flag circuit for each main word line MW (MW0, MW1, ...) provided (F0AX, F1AX, ...), FBX (F0BX, F1BX, ...). 换句话说,标志FAX、 FBX被形成用于每个局部区域PA。 In other words, flags FAX, FBX is formed for each local region PA.

每个标志FAX、 FBX由锁存电路构成,该锁存电路由输入和输出彼此连接的两个反相器组成。 Each flag FAX, FBX is constituted by a latch circuit, a latch circuit which inputs and outputs of two inverters connected to each other in composition. 在从数据保持模式转移到正常操作模式时,当相应的局部区域PA中的存储器单元独立地保持数据时(第一存储器模式, 单单元操作),标志FAX、 FBX被复位为高电平,而当相应的局部区域PA中的存储器单元保持公共数据时(第二存储器模式,双单元操作), When the data holding mode to the normal operation mode, when the corresponding partial area PA of the memory cells holding data independently (a first storage mode, single unit operation), flags FAX, FBX is reset to a high level, and when the corresponding partial area PA of the memory cell holding the common data (the second memory mode, two-unit operation),

标志FAX、 FBX被置位为低电平。 Flag FAX, FBX is set low.

更具体地说,标志FAX、 FBX与局部模式释放信号PREFR的脉冲同步地被置位为低电平。 More specifically, the FAX flag, the local pulse FBX PREFR mode release signal is set to low in synchronism. 这意味着如后面将描述的,在从数据保持模式返回到正常操作模式时,全部标志FAX、 FBX被置位了。 This means that as will be described later, when the data from the hold mode returns to the normal operation mode, all flags FAX, FBX is set up. 换句话说,在将全部存储器单元的状态从第二存储器模式改变到第一存储器模式的改变操作之前,全部标志FAX、 FBX被置位了。 In other words, before the state of all memory cells of the memory is changed from the second mode to the first storage mode changing operation, all the flags FAX, FBX is set up. 被置位的标志FAX、 FBX指示相应的局部区域PA中的存储器单元的单单元操作被禁止。 Flag is set to FAX, FBX indicate corresponding partial area PA of the memory cells in a single unit operation is prohibited. 相应地,在与标志FAX、 FBX相对应的局部区域PA中只允许双单元操作。 Accordingly, with the flag FAX, FBX corresponding partial area PA only two-unit operation. 这样,标志电路30操作为标志置位电路。 Thus, the circuit 30 operates as a symbol flag set circuit.

标志FAX、 FBX分别与标志复位信号FRAX、 FRBX同步地被复位到高电平。 Flag FAX, FBX respectively flag reset signal FRAX, FRBX synchronization is reset to the high level. 即,如后面将描述的,在将全部存储器单元的状态从第二存储器模式改变到第一存储器模式的改变操作中,对相应的局部区域PA的第一次访问期间,标志FAX、 FBX被复位。 That is, as will be described later, in the state of all memory cells of the memory is changed from the second mode to the first mode change operation in the memory, during the first visit of the corresponding partial area PA, flags FAX, FBX is reset .

当标志FAX被置位为低电平时,标志电路30与译码信号XDX (XDOX, XD1X,...)同步地将标志输出信号S1AX改变到低电平。 When the FAX flag is set low, flag circuit 30 with the decoded signal XDX (XDOX, XD1X, ...) in synchronization with the change flag S1AX output signal to a low level. 当标志FBX被置位为低电平时,标志电路30与译码信号XDX (XDOX, XD1X,...)同步地改变标志输出信号SIBX。 When the flag is set low FBX, flag circuit 30 and the decoded signal XDX (XDOX, XD1X, ...) output signal of SIBX change flag synchronization.

标志检测电路28具有锁存电路、多路转换器MUX1、延迟电路DELAY1和掩码电路MSK,其中锁存电路分别连接到标志输出信号S1AX、 S1BX,多路转换器MUX1根据行地址信号的低位XI输出标志输出信号S1AX、 S1BX中的一个信号到节点ND6。 Mark detection circuit 28 has a latch circuit, the multiplexer MUX1, the delay circuit DELAY1 and the mask circuit MSK, wherein the latch circuit are connected to the flag output signal S1AX, S1BX, multiplexer MUX1 according to the lower row address signal XI the output flag output signal s1AX, a signal to the node in S1BX ND6. 延迟电路DELAY1只将行激活信号RASZ的上升沿延迟预定的时间段。 The delay circuit DELAY1 only the row active edge of the signal RASZ is delayed by a predetermined period of time. 掩码电路M汰将由多路转换器MUX1选择的标志输出信号S1AX或者S1BX输出为标志检测信号FDTC。 Mask circuit M by eliminating the multiplexer MUX1 to select the output signal S1AX flag or flag detection output signal S1BX FDTC. 此外,掩码电路MSK具有当提供了写命令时縮短标志检测信号FDTC的激活时段的功能。 Further, when the mask circuit MSK having a functionality provided FDTC shortening flag detection signal when the activation period of the write command. 在当访问伪SRAM时检测到标志FAX或FBX 被置位了的时候,标志检测电路28输出标志检测信号FDTC。 FBX FAX flag is set or the time is detected when accessing the pseudo SRAM, the mark detection circuit 28 outputs a detection signal flag FDTC.

图14示出了局部刷新模式后的正常操作模式中标志电路30和标志检测电路28的操作。 Operation circuit 30 and the flag detection circuit 28 is a normal operation mode in FIG. 14 illustrates a partial refresh mode after the flag. 该示例示出了一种情况,其中在响应于写命令而执行的写操作中,标志电路30的标志FAOX被置位到低电平。 This example shows a case in which a write operation is performed in response to the write command, the flag of the flag FAOX circuit 30 is set to a low level. 根据与写命令相对应的地址信号,次低位的译码信号X1改变到低电平。 The address signal corresponding to the write command, the decoded signal X1 is changed to a low level times lower.

首先,与响应于写命令的写控制信号WRZ同步地输出行激活'信号RASZ (图14 (a)),并且与行地址信号RAD2相对应的译码信号XD0X 改变到低电平(图14 (b))。 First, in response to the write control signal WRZ write command in synchronization with the output row active 'the RASZ signal (FIG. 14 (A)), and changes the row address signal RAD2 XD0X decoded signal corresponding to a low level (FIG. 14 ( b)). 根据已经被复位的标志FAOX,图13所示的标志电路30输出低电平标志输出信号S1AX (图14 (c))。 The flag has been reset FAOX, flag circuit 30 outputs a low level as shown in FIG. 13 s1ax flag output signal (FIG. 14 (c)).

标志检测电路28的多路转换器MUX1输出标志输出信号S1AX到节点ND6 (图14 (d))。 Multiplexing the mark detection circuit 28 of the converter output flag output signal MUX1 to the node ND6 S1AX (FIG. 14 (d)). 标志检测电路28与标志输出信号S1AX的下降沿同步地将标志检测信号FDTC激活到高电平(图14 (e))。 Mark detection circuit 28 detects the flag signal is activated with the falling edge FDTC S1AX flag output signal to the high level in synchronization (FIG. 14 (e)).

在从RASZ信号的上升沿开始的预定时间段之后,标志检测电路28 的延迟电路DELAY1将节点ND7改变到高电平(图14 (f))。 After a predetermined time period starting from the rising edge of the RASZ signal, the delay circuit DELAY1 flag detection circuit 28 changes to the high level node ND7 (FIG. 14 (f)). 由于WRZ信号处于高电平,所以节点ND8与节点ND7的电平改变同步地改变到高电平(图14 (g))。 Since the WRZ signal is high, and the node ND8 level change synchronization node ND7 is changed to the high level (FIG. 14 (g)). 根据节点ND8的高电平,掩码电路MSK的NOR门对节点ND6的电平的电压掩码。 Node ND8 high level, the mask circuit MSK NOR gate voltage level of the node ND6 on the mask in accordance with. 相应地,即使在S1AX的激活期间,标志检测信号FDTC也被去活(图14 (h))。 Accordingly, even during the activation S1AX, FDTC flag detection signal is also deactivated (FIG. 14 (h)).

此后,节点ND8与WRZ信号的去活同步地改变到低电平(图14 (i) ) 。 Thereafter, the deactivated node ND8 WRZ signal is changed to the low level in synchronization (FIG. 14 (i)). XD0X信号、S1AX信号和节点ND6、 ND7与RASZ信号的去活同步地返回初始电平。 XD0X signal, S1AX signals and nodes ND6, ND7 and deactivated RASZ signal is returned to the initial level synchronization.

图15示出了局部刷新模式后的正常操作模式中的标志电路30和标志检测电路28的另一操作。 Another operation after the normal operation mode in FIG. 15 shows a partial refresh mode flag circuit 30 and the flag detection circuit 28. 与上述图14中的操作相同的操作的详细描述将被省略。 14 in the operation the same as described in detail in FIG operation will be omitted. 该示例示出了一种情况,其中在响应于写命令的写操作中,标志电路30的标志FAOX被复位到高电平。 This example shows a case where in response to the write command in the write operation, the flag of the flag FAOX circuit 30 is reset to a high level. 此外,根据与写命令相对应的地址信号,次低位的译码信号XI改变到低电平。 Further, the address signals corresponding to the write command, the decoded signal XI is changed to a low level times lower.

在标志FAOX被复位到高电平("H")之后,标志电路30的NOR 门维持高电平。 After FAOX flag is reset to the high level ( "H"), the flag of the NOR gate 30 maintains the high level. 相应地,标志输出信号S1AX维持高电平,而不管译码信号XDOX的激活(图15 (a))。 Accordingly, the output signal S1AX flag maintains the high level, regardless of the decoded signal activates XDOX (FIG. 15 (a)). 高电平节点ND6被高电平标志输出信号S1AX维持在高电平。 Flag is turned on by a high level node ND6 S1AX at high-level output signal. 因此,不输出标志检测信号FDTC (图15 (b))。 Accordingly, the detection signal is not output FDTC flag (FIG. 15 (b)).

图16示出了局部刷新模式后的正常操作模式中的标志电路30和标志检测电路28的另一操作。 Another operation after the normal operation mode in FIG. 16 shows a partial refresh mode flag circuit 30 and the flag detection circuit 28. 与上述图14中的操作相同的操作的详细描述将被省略。 14 in the operation the same as described in detail in FIG operation will be omitted. 该示例示出了一种情况,其中在响应于读命令的读操作中,或者 This example shows a case where the read command in response to a read operation, or

在响应于在伪SRAM中内部生成的刷新请求的刷新操作中,标志电路30 的标志FAOX被置位到低电平。 In the refresh operation responsive to the pseudo-SRAM generates an internal refresh request flag FAOX flag circuit 30 is set to a low level. 此外,通过与读命令相对应的地址信号或者刷新地址信号,次低位的译码信号XI改变到低电平。 Further, by the read address signal corresponding to the command or the refresh address signal, low secondary decoded signal changes to a low level XI.

首先,与响应于读命令的读控制信号RDZ或者响应于刷新请求的刷新控制信号REFZ同步地输出行激活信号RASZ (图16 (a)),并且写控制信号WRZ不被激活(图16 (b))。 First, the read control signal RDZ in response to the read command or in response to the refresh request the refresh control signal REFZ output line in synchronization with the activation signal the RASZ (FIG. 16 (a)), and the write control signal WRZ is not activated (FIG. 16 (b )). 相应地,节点ND8维持低电平 Accordingly, to maintain a low level node ND8

(图16 (c)),并且掩码电路MSK不起作用。 (FIG. 16 (c)), and the mask circuit MSK ineffective. 因此,在与RASZ信号的高电平时段相对应的时段中,标志检测信号FDTC保持被激活(图16 Thus, with the high level period of the RASZ signal corresponding to the period, the flag detection signal FDTC remains activated (FIG. 16

(d))。 (D)).

图n示出了局部刷新模式后的正常操作模式中的标志电路30和标志检测电路28的另一操作。 Another operation after normal operating mode is shown n FIG partial refresh mode flag circuit 30 and the flag detection circuit 28. 与上述图14和图15中的操作相同的操作的详细描述将被省略。 Operation in FIG. 14 and FIG. 15 above detailed description of the operation of the same will be omitted. 该示例示出了一种情况,其中在响应于读命令的读操作中,或者在响应于在伪SRAM中内部生成的刷新请求的刷新操作中,标志电路30的标志FAOX被复位到高电平。 This example shows a case where the read command in response to a read operation or refresh operation in response to the refresh request generated inside the pseudo SRAM, the flag of the flag FAOX circuit 30 is reset to a high level . 此外,根据与读命令相对应的地址信号或者刷新地址信号,次低位的译码信号X1改变到低电平。 Further, according to the read address signal corresponding to the command or the refresh address signal, low secondary decoded signal X1 is changed to a low level.

在标志FAOX被复位到高电平("H ")之后,标志电路30的NOR 门维持高电平。 After FAOX flag is reset to the high level ( "H"), the flag of the NOR gate 30 maintains the high level. 相应地,与图15所示的示例一样,不输出标志检测信号FDTC。 Accordingly, the example shown in FIG. 15 as a detection signal is not output flag FDTC.

图18示出了图l所示的标志复位电路26的细节。 Figure 18 shows a detail flag is reset circuit 26 shown in FIG l.

标志复位电路26具有脉冲发生器26a、延迟电路DEALY2和多路转换器MUX2。 Flag reset circuit 26 has a pulse generator 26a, and a delay circuit DEALY2 multiplexer MUX2. 脉冲发生器26a与标志检测信号FDTC的上升沿同步地生成低电平脉冲。 A rising edge pulse generator 26a and the flag detection signal for generating a low level pulse FDTC synchronization. 延迟电路DELAY2将该低电平脉冲延迟预定的时间段,以将其输出到节点ND9。 The delay circuit DELAY2 low pulse delayed by a predetermined period of time to output it to node ND9. 当译码信号X1处于低电平时,多路转换器MUX2将节点ND9处的脉冲输出为标志复位信号FRAX,而当译码信号XI处于高电平时,多路转换器MUX2将节点ND9处的脉冲输出为标志复位信号FRBXo When the decoded signal X1 at a low level, multiplexer MUX2 outputs pulses at the node ND9 flag reset signal FRAX, when the decoded signal XI at a high level, the multiplexer MUX2 pulse at node ND9 flag reset signal output FRBXo

图19示出了图18所示的标志复位电路26的操作。 FIG 19 shows an operation flag is reset circuit 26 shown in FIG. 18. 该示例示出了紧跟在局部刷新模式之后的正常操作模式。 This example shows a normal operating mode immediately after the partial refresh mode.

如图14到图17所示的那样,当标志fa1x (或fb1x)被置位时,生成标志检测信号fdtc,而当标志FA1X (或fbx)被复位时,不生成标志检测信号fdtc。 14 to 17 as shown, when flag fa1x (or fb1x) is set, the flag detection signal generating FDTC, and when the flag FA1X (or FBX) is reset, the flag detection signal is not generated fdtc. 在局部刷新操作之后,全部标志fax、 fbx与局'部模式释放信号PREFR同步地被置位到低电平。 After the partial refresh operation, all flags fax, fbx the Bureau 'portion PREFR mode release signal is asserted to a low level in synchronization. 相应地,与局部刷新操作后的第一次访问(RDZ、 WRZ、 RWEFZ)同步地输出与各个局部区域PA相对应的标志检测信号FDTC (图19 (a))。 Accordingly, the first partial refresh operation after the first visit (RDZ, WRZ, RWEFZ) FDTC output flag detection signal (FIG. 19 (a)) and the respective local area PA corresponding to the synchronization.

标志复位电路26与标志检测信号fdtc同步地输出标志复位信号FRAX或FRBX (图19 (b、 c))。 Flag is reset and the flag detection circuit 26 outputs a signal fdtc synchronization flag reset signal FRAX or FRBX (FIG. 19 (b, c)). 根据译码信号XI的电平,确定标志复位信号FRAX和FRBX中的哪一个将被输出。 The level of the decoded signal XI, which determines a flag reset signal to be output in FRAX and FRBX. 图19示出了一个示例, 其中在某个局部区域PA中,首先访问存储器单元COO,接着访问存储器单元COl。 FIG 19 shows an example in which a partial area PA, the memory unit first accesses COO, followed by accessing the memory cells COl.

注意,与译码信号XDX (XD0X, XD1X,...)相对应的标志FAX (FAOX, fa1x,...)或FBX (fb0x, fb1x,...)与标志复位信号 Note that, the decoded signal XDX (XD0X, XD1X, ...) corresponding to the flag FAX (FAOX, fa1x, ...), or FBX (fb0x, fb1x, ...) with a flag reset signal

FRAX或FRBX的脉冲同步地被复位到高电平。 FRAX or FRBX synchronization pulse is reset to the high level.

图20示出了第一实施例中的正常操作模式期间的操作。 FIG. 20 shows the operation during a normal operation mode in the first embodiment. 在正常操作期间使伪sram操作的命令cmd包括经由外部接线端提 During normal operation makes sram dummy command cmd include external terminals provide

供的访问命令(读命令、写命令)和刷新命令(来自刷新命令发生器16 For access commands (read command, write command) and a refresh command (from the refresh command generator 16

的REFZ信号)。 The REFZ signal).

例如,响应于第一命令CMD,局部存储器单元COO被访问,并且响应于下一个命令cmd,公共存储器单元c10被访问。 For example, in response to the first command to the CMD, COO local memory cell is accessed, and in response to the next command cmd, c10 common memory unit is accessed. 字线swop、 sw1 根据行地址信号rad2被独立地选择。 Word lines swop, sw1 is independently selected according to a row address signal rad2. 即,在正常操作模式中,1位数据被存储在与一条字线连接的每个存储器单元中(第一存储器模式,单单元操作)。 That is, in the normal operation mode, a data (a first storage mode, single unit operation) stored in each memory cell connected to a word line.

当命令CMD是读命令时,在位线BL、 /BL上被放大的数据经由数据总线DB被输出到外部部分。 When the command is a read command CMD, the bit line BL, on / BL is amplified data is output to the external portion via the data bus DB. 当命令CMD是写命令时,经由外部接线端提供的数据在写放大器wa和读出放大器sa中被放大,以写入存储器单元。 When the command is a write command CMD, data supplied via the external terminals at the write amplifier is amplified by the amplifier wa sa and read out to write the memory cell. 当命令CMD是刷新命令时,在读出放大器SA中被放大的数据被写回存储器单元。 When the command is a refresh command CMD, amplifier SA is amplified in the read data is written back to the memory cells.

图21示出了第一实施例中公共刷新模式(-数据保持模式,低功耗 FIG 21 shows a first embodiment, the common refresh mode (- data holding mode, Low Power

模式)期间的操作。 During operation mode). 在公共刷新模式中,禁止接受外部访问命令。 In common refresh mode, barred from receiving external access to the command. False

SRAM仅响应于内部生成的刷新命令REF而操作。 SRAM only in response to an internally generated refresh command REF operate.

在公共刷新模式中,局部存储器单元C00首先被访问,并且局部存储器单元C00中所保持的数据被读出放大器SA锁存(图21 (a))。 In the common refresh mode, the local memory is first accessed cell C00 and cell C00 in the local memory the data held in the sense amplifier SA is latched (FIG. 21 (a)). 接着,在读出放大器SA保持激活的同时,公共存储器单元C10被访问,并且读出放大器SA中锁存的数据(互补数据)被写入局部存储器单元COO 和公共存储器单元CIO (图21 (b))。 Next, the sense amplifier SA remains active while the common memory unit C10 is accessed and latched in the sense amplifier SA data (complementary data) is written into the local memory unit and the common memory unit the CIO COO (FIG. 21 (b )). 因此,局部存储器单元COO和公共存储器单元CIO保持互补数据。 Thus, the local memory unit and the common memory cells COO CIO holding complementary data. 然后,全部局部区域PA (存储器单元组)经历上述操作。 Then, the entire local area PA (memory cells) subjected to the above-described operation. 即,1位数据被存储在与两条字线SWOP、 SW1连接的存储器单元组中的多个存储器单元(例如,COO和CIO)中(第二存储 That is, the 1-bit data is stored in two word lines SWOP, SW1 is connected to memory cells in the plurality of memory cells (e.g., COO and CIO) (for the second memory stores

模式,双单元操作)。 Mode, bi-cell operation).

图22示出了第一实施例中局部刷新模式(数据保持模式,低功耗模式)期间的操作。 FIG 22 shows a first embodiment of the partial refresh mode (data holding mode, the low power consumption mode) during the operation of the embodiment. 在局部刷新模式中,与公共刷新模式中一样,禁止接受外部访问命令。 In the partial refresh mode, refresh mode as with the public, barred from receiving external access to the command. 伪SRAM仅响应于内部生成的刷新命令REF而操作。 Only in response to the pseudo-SRAM generates an internal refresh command REF to operate.

在局部刷新模式中,局部字线SWOP和公共字线SW1被同时选择, 并且局部存储器单元COO和公共存储器单元CIO中所保持的互补数据同时在读出放大器SA中被放大,以被写回存储器单元C00、 CIO (双单元操作)。 In partial refresh mode, the local word lines SWOP and the common word line SW1 are simultaneously selected, and the local memory cells COO and complementary data common memory unit CIO held in the simultaneously read out is amplified by sense amplifier SA, to be written back to memory means C00, CIO (bi-cell operation). 即,1位数据被存储在与两条字线SWOP、 SW1连接的存储器单元组中的多个存储器单元(例如,COO、 CIO)中(第二存储器模式)。 That is, 1-bit data is stored in two word lines SWOP, SW1 is connected to memory cells in the plurality of memory cells (e.g., COO, CIO) (for the second memory mode). '数据被保持在局部存储器单元coo和公共存储器单元CIO中,使得刷新周期可 'Data is held in the local memory unit and the common memory unit coo CIO so that the refresh cycle can be

以大大加长。 To significantly lengthened.

在局部刷新模式中,按照被加长的刷新周期,刚好在刷新操作之前在一个存储器单元中所保持的电荷量少于正常操作模式中的电荷量。 In partial refresh mode, the refresh cycle in accordance with lengthened, just before the refresh operation in one memory cell in the charge held in the charge amount is less than the normal operating mode. 因此, therefore,

存在这样的风险:在某段时间之前被刷新的存储器单元中的数据不能在局 There is a risk: some time before the data is refreshed memory cells not in the Council

部刷新操作后的正常操作模式中被正确读取(数据丢失)。 Normal operating mode after the refresh operation portion is correctly read (data loss). 在本发明中, 通过当在局部刷新操作后的正常操作模式中对每个存储器单元进行第一次 In the present invention, when for the first time of each memory cell in the normal operating mode after the partial refresh operation,

访问时,采取特殊的方法来防止数据丢失,如将在后面描述的图24到图26中所示的那样。 Access, to prevent take special method 26 as shown in data loss, as will be described later in FIG. 24 to FIG.

图23示出了在第一实施例中局部刷新模式后的正常操作模式中,当 FIG 23 illustrates normal operation mode after the partial refresh mode in this embodiment the first embodiment, when

CE信号在全部标志FAX、 FBX被复位之前改变到低电平,使得操作模式再次从正常操作模式转移到数据保持模式(低功耗模式)时的操作。 CE signal changes to a low level until all the flags FAX, FBX is reset, so that the operation mode is again shifted from the normal operation mode to the data holding operation mode (low power mode).

当检测到标志FAX、 FBX的置位状态时,图13所示的标志检测电路28输出标志检测信号FDTC,而不管操作模式如何。 When the FAX flag is detected, the set state of FBX, the mark detection circuit shown in FIG. 13, 28 outputs a detection signal FDTC flag, regardless of the mode of operation. 因此,即使在公共刷新模式中,也输出标志检测信号FDTC (图23 (a))。 Therefore, even when the common refresh mode, also the output signal of FDTC detection flag (FIG. 23 (a)).

标志检测信号FDTC的激活引起字译码器WDEC同时选择与局部区域PA相对应的一对子字线SW0P、 SW1 (图23 (b)),如图22中的情况一样。 FDTC activation flag detection signal causes the simultaneously selected word decoder WDEC corresponding to the partial area PA of a sub word line SW0P, SW1 (FIG. 23 (b)), in the case 22 as shown in FIG. 响应于标志检测信号FDTC,图18所示的标志复位电路输出标志复位信号FRAX,以将标志FOAX复位到高电平(图23 (c))。 In response to the detection signal FDTC flag, the flag is reset circuit outputs the reset signal FRAX flag shown in FIG. 18, to FOAX flag is reset to a high level (FIG. 23 (c)).

对于公共刷新模式中的刷新操作,在读出放大器SA被激活的同时, 子字线SW1被再次选择,并且读出放大器SA中锁存的数据被写入存储器单元C10 (图23 (d))。 To the common refresh mode in the refresh operation, the sense amplifier SA is activated at the same time, SW1 sub-word line is selected again, and the sense amplifier SA latched data is written to memory cell C10 (FIG. 23 (d)) . 该操作是冗余的,并且不是必须的。 This operation is redundant and not necessary. 但是,由于该操作没有在操作中引起任何问题,并且可以避免电路的复杂化,因此该冗余操作是允许的。 However, since this operation did not cause any problems in operation, and avoid complicating the circuit, and therefore the redundancy operation is permitted.

图24到图26示出了在从低功耗模式释放之后的正常操作模式中的操 24 to FIG. 26 shows the operation in the normal operation mode after the release from the low power mode

作。 Make. 在低功耗模式期间通过双单元操作被刷新的存储器单元对中的每个存储器单元中所保持的电荷量有时并不大到足够用于单单元操作。 During the low power mode by double the amount of charge operation unit memory cell to be refreshed for each memory cell held sometimes not large enough for a single unit operation. 因此,在 Thus, in

从低功耗模式返回到正常操作模式的时候(操作模式改变的时候),需要全部局部存储器单元实施一次双单元操作,从而补偿存储器单元电容器中所保持的电荷量的不足。 (When the operation mode is changed) is returned from low-power mode to the normal operation mode, the need for all local memory cell embodiment a double unit operation, so that the amount of charge of the compensation capacitor in a memory cell held insufficient.

在作出本发明之前,过去需要一个改变时段,用于将全部局部存储器单元实施一次双操作。 Prior to the present invention, in the past a need to change the period for the whole operation performed once bis local memory cells. 这使得在该时段中,外部系统不能访问伪SRAM。 This makes this period, the external system can access the pseudo SRAM. 在本发明中,在操作模式改变之后,标志FAX、 FBX被用于使在各个局部区域PA中要被首先访问的存储器单元实施双单元操作,从而不需要上述的改变时段。 In the present invention, after the operation mode is changed, flags FAX, FBX is memory for each local area PA unit to be accessed first embodiment of the two-cell operation, thereby eliminating the need to change the aforementioned period. 因此,在返回到正常操作模式之后,外部系统立刻能够对伪SRAM进行读访问和写访问,而不用注意双单元操作。 Thus, after the return to normal operating mode, the external system can be immediately read and write access to the pseudo SRAM, without paying attention to two-unit operation. 下面将描述其方法。 The methods will be described below.

图24示出了一个示例,其中在返回到正常操作模式之后,刷新请求REF被顺序生成。 FIG 24 shows an example in which after the return to normal operating mode, the refresh request REF is generated sequentially.

首先,图1所示的命令译码器10从伪SRAM的内部部分接收数据保持模式(低功耗模式)的释放命令PEXIT,以输出局部模式释放信号PREFR (图24 (a))。 First, as shown in FIG. 1, the command decoder 10 holds the release mode (low power mode) of the internal portion of the pseudo SRAM receives data from the command PEXIT, in the local mode release signal output PREFR (FIG. 24 (a)). 局部模式释放信号PREFR的输出引起伪SkAM 从低功耗模式返回到正常操作模式。 Partial output mode release signal causes the pseudo SkAM PREFR return from low power mode to the normal operation mode. 图13所示的标志电路30与局部模式释放信号PREFR同步地将标志FAX (FOAX, FIAX, ... ) 、 FBX (FOBX, F1BX,…)置位到低电平(图24 (b))。 Flag circuit 30 illustrated in FIG. 13 and the local mode release signal PREFR synchronization flag FAX (FOAX, FIAX, ...), FBX (FOBX, F1BX, ...) is set to a low level (FIG. 24 (b)) .

接着,在伪SRAM中内部地生成刷新命令REF (REFZ信号),并且图1所示的定时控制电路38输出RASZ信号(图24 (c))。 Next, the pseudo-SRAM generates an internal refresh command REF (REFZ signal), and the timing control circuit 138 shown in FIG RASZ output signal (FIG. 24 (c)). 此时,刷新地址计数器18正输出用于选择存储器单元COO的刷新地址信号REFAD。 At this time, the refresh address counter 18 outputs a positive refresh address signal REFAD of the selected memory cell COO. 具体地说,行地址信号的两个低位XI、 XO都处于低电平(图24 (d))。 In particular, two low row address signal XI, XO are at the low level (FIG. 24 (d)). 响应于RASZ信号,图B所示的字译码器WDEC输出与存储器单元COO相对应的主字线信号MWO和译码信号XDOX (图24 (e、 f))。 As shown in response to the RASZ signal, B of FIG word decoder WDEC outputs the corresponding memory cell COO main word line signal and the decoded signal MWO XDOX (FIG. 24 (e, f)).

标志电路30与译码信号XDOX同步地将标志FOAX、 FOBX的内容输出为标志输出信号S1AX、 S1BX (图24 (g))。 Flag circuit 30 with the decoded signal XDOX flag FOAX, FOBX content is output in synchronization flag output signal S1AX, S1BX (FIG. 24 (g)). 标志检测电路28根据行地址信号的位XI选择标志输出S1AX,以将其输出为标志检测信号FDTC S1AX mark detection circuit 28 outputs a selection marker XI according to the bit row address signal, to output a detection signal as a flag FDTC

(图24 (h))。 (FIG. 24 (h)). 当接收到标志检测信号FDTC时,图9所示的1/4字译码器44将译码信号的两个位X00、 X01改变到高电平。 When receiving the flag detection signal FDTC, 44 the decoded signal is shown in FIG. 9 1/4 word decoders two bits X00, X01 change to high level. 然后,两个子字线SWOP、 SW1被同时选择(图24 (i)),并且对存储器单元COO、 C10执行双单元刷新操作(图24 (j))。 Then, two sub-word lines SWOP, SW1 are simultaneously selected (FIG. 24 (i)), and the refresh operation (Fig. 24 (j)) of memory cells COO, C10 double execution unit. 然后,数据被写回从中读取公共数据的存储器单元COO、 CIO。 The data is then written back to the memory cell read from public data COO, CIO. 这防止了在低功耗模式期间存储器单元COO中所保持的数据的丢失。 This prevents the loss of the low power mode during a memory cell COO held in the data. 读出放大器激活信号PSA、 NSA的"ON"和 Sense amplifier activating signals PSA, NSA in the "ON" and

"OFF"分别表示读出放大器SA的激活和去活。 "OFF" represent the sense amplifier SA is activated and deactivated.

注意,刷新操作中作为存储器核心34操作时间的内部刷新周期时间IREF被设定为与正常操作模式中的内部刷新周期时间的长度相同。 Note that, the refresh operation, the refresh cycle time IREF same length is set to the normal operation mode of the internal refresh cycle time of the memory core 34 as the internal operation time.

图18所示的标志复位电路26与标志检测信号FDTC同步地输出与位XI相对应的标志复位信号FRAX (图24 (k))。 Flag reset circuit 18 shown in FIG. 26 and the output synchronization flag detection signal FDTC XI bit flag corresponding FRAX reset signal (FIG. 24 (k)). 响应于标志复位信号FRAX,图13所示的标志电路30将与译码信号XDOX相对应的标志FOAX复位到高电平(图24 (1))。 In response to the flag reset signal FRAX, flag circuit 30 shown in FIG. 13 will correspond to the decoded signal XDOX FOAX flag is reset to a high level (FIG. 24 (1)). 通过将标志FOAX复位,相应的局部区域PA中的存储器单元此后以第一存储器模式(单单元操作)被访问。 The flag is reset by FOAX, corresponding partial area PA of the memory cell is thereafter accessed to the first memory mode (single unit operation).

根据RASZ信号的去活,译码信号XDOX被去活,并且标志输出信号S1AX、 S1BX被预充电到高电平(图24 (m、 n))。 The deactivation signal RASZ, XDOX decoded signal is deactivated and the flag output signal S1AX, S1BX is precharged to a high level (FIG. 24 (m, n)). 通过标志输出'信号S1AX、 S1BX的预充电,标志检测信号FDTC被去活到低电平(图24 Flag by the output 'signal s1ax, the precharge S1BX, FDTC flag detection signal is deactivated to a low level (FIG. 24

(o))。 (O)). 根据标志检测信号FDTC的去活,主字线MW0和子字线SW0P、 SW1不被选择(图24 (p))。 The FDTC mark detection signal is deactivated, the main word line and sub-word line MW0 SW0P, SW1 is not selected (FIG. 24 (p)).

接着,生成刷新命令REF (REFZ信号)(图24 (q))。 Next, generate a refresh command REF (REFZ signal) (FIG. 24 (q)). 刷新地址计数器18己经被递增,并且正输出用于选择存储器单元C10的刷新地址信号REFAD。 Refresh address counter 18 has been incremented, and the positive outputs a refresh address signal REFAD of the selected memory cell C10. 相应地,行地址信号的位XO改变到高电平(图24 Accordingly, the XO bit row address signal changes to a high level (FIG. 24

(r))。 (R)).

与存储器单元C10相对应的标志FAOX已经通过先前的刷新操作被复位到高电平。 And the memory cell C10 FAOX corresponding flag has been reset to a high level by the previous refresh operation. 因此,当译码信号XDOX被激活时,标志电路30只将标志输出信号S1BX改变到低电平,而标志输出信号S1AX维持在高电平(图24 (s))。 Thus, when the decode signal is activated XDOX, flag circuit 30 to change the flag to a low level output signal S1BX, the flag is maintained at a high level output signal S1AX (FIG. 24 (s)). 由于与刷新地址(XI = "0")相对应的标志输出信号S1AX 处于高电平,所以不输出标志检测信号FDTC (图24 (t))。 Since the refresh address (XI = "0") corresponding to the output signal S1AX flag at a high level, the detection signal is not output FDTC flag (FIG. 24 (t)). 相应地,只有一条子字线SW1被选择,并且执行第一存储器模式中的正常刷新操作(单单元操作)。 Accordingly, only a sub-word line is selected SW1, and performs a normal refresh operation (single unit operations) in the first memory mode. 注意,在低功耗模式期间,存储器单元C10中的数据不是互补的。 Note that, during the low power mode, the data of the memory cell C10 are not complementary. 因此,对于图24中的示例,通过该刷新操作所保持的数据并不具有任何特殊的意义。 Thus, in FIG. 24 for example, held by a refresh operation of the data does not have any special meaning.

单单元刷新操作的刷新周期时间IREF被设定为与双单元刷新操作的刷新周期时间IREF的长度相同。 Single cell refresh operation IREF refreshing cycle time is set to be the same length as a double cell refresh operation of the refresh cycle time IREF. 将刷新周期时间IREF设定为长度相同使得可以简化核心控制电路32的定时控制电路38的配置。 The refreshing cycle time is set to the same length such that IREF possible to simplify the core control circuit 32 controls the timing circuit 38 configuration.

接着,生成刷新命令REF (REF信号)(图24 (ii))。 Next, generate a refresh command REF (REF signal) (FIG. 24 (ii)). 刷新地址计数器18已经被递增,并且正输出用于选择存储器单元C20的刷新地址信号REFAD。 Refresh address counter 18 has been incremented, and the positive outputs a refresh address signal REFAD of the selected memory cell C20. 相应地,行地址信号的位X1改变到高电平(图24 (v))。 Accordingly, the bit row address signal X1 is changed to a high level (FIG. 24 (v)).

标志FBOX被置位到低电平。 FBOX flag is set to a low level. 相应地,如上述的操作中一样,标志输出信号S1BX改变到低电平(图24 (w))。 Accordingly, the same operation as described above, the output signal S1BX flag changes to the low level (FIG. 24 (w)). 标志检测电路28根据行地址信号的位XI选择标志输出信号S1BX,以将其输出为标志检测信号FDTC (图24 (x))。 Mark detection circuit 28 XI S1BX output signal according to a selectable marker bit row address signal, to output a detection signal as a flag FDTC (FIG. 24 (x)). 然后,两个子字线SW2P、 SW3被同时选择,并且对存 Then, two sub-word lines SW2P, SW3 are simultaneously selected, and to deposit

储器单元C00、 C10执行双单元刷新操作(图24 (y))。 Reservoir units C00, C10 dual execution units refresh operation (FIG. 24 (y)). 此后,与标志检测信号FDTC同步地,标志复位信号FRBX被输出,并且标志FOAX被复位到高电平(图24 (zl、 z2))。 Thereafter, the synchronization flag detection signal FDTC, FRBX flag reset signal is outputted, and the flag is reset FOAX to the high level (FIG. 24 (zl, z2)).

图25示出了一个示例,其中在返回正常操作模式之后,在第一个刷新请求REF之前提供了读命令RD。 FIG 25 shows an example in which after the return to normal operating mode, a read command RD until the first refresh request REF. 由于响应于读命令RD直到在位线BL、 /BL上放大数据的操作(图25 (a)到(p))都与上述图24的操作相同,所以使用了相同的参考符号。 Since the operation in response to the read command RD until the bit line BL, / BL amplified data (FIG. 25 (a) to (p)) to the operation described above are the same as in FIG. 24, the use of the same reference symbols.

在通过双单元操作被保持在存储器单元C00、 C10中的数据在读出放大器SA中被放大之后,图1所示的列译码器CDEC对列地址信号CAD译码,并将图9所示的与存储器单元C00相对应的列选择信号CL0激活预定的一段时间(图25 (q))。 After being held in memory cell C00 by the two-cell operation, the data C10 is amplified in the sense amplifier SA, the column decoder shown in FIG. 1 CDEC decodes the column address signal CAD, and 9 shown in FIG. the memory cell C00 column select signal corresponding to a predetermined period of time CL0 activation (FIG. 25 (q)). 列选择信号CL0引起相应的列开关CSW接通,使得互补位线BL、 /BL被选择性连接到数据总线DB。 Column select signals CL0 causes a corresponding column switch CSW is turned on, so that the complementary bit lines BL, / BL is selectively connected to the data bus DB. 然后,存储器单元C00中所保持的数据在读出缓冲器SB中被放大,之后经由公共数据总线CDB从数据输入偷出端DQ被输出(图25 (r))。 Then, the memory cell C00 is held in the read data buffer SB is amplified, after which the data input from the output terminal DQ steal (FIG. 25 (r)) via a common data bus CDB.

读操作中的存储器核心34的操作时间由内部读周期时间IRD表示。 Memory core operation time read operation 34 is represented by the internal read cycle time IRD. 内部读周期时间IRD在数据保持模式和正常操作模式中具有相同的长度。 The internal read cycle time IRD held in the data mode and the normal operation mode has the same length. 此外,内部读周期时间IRD的长度与内部刷新周期时间IREF和内部写周期时间IWR1 (后面描述的图28)的长度相同,其中所述内部刷新周期时间IREF是刷新操作中存储器核心34的操作时间,内部写周期时间IWR1 是写操作中存储器核心34的操作时间。 Further, the length of the internal read cycle time IRD internal refresh cycle time and the write cycle time IREF IWR1 same length (FIG. 28 described later), wherein said internal refresh cycle time IREF is the refresh operation of the memory core operation time 34 , internal write cycle time IWR1 operation is a write operation time of the memory core 34. 内部写周期时间IWR1是用于不包括双单元操作的写操作的时间,并且在保持模式和正常操作模式两者中长度相同。 IWR1 internal write cycle time for a write operation time does not include two-unit operation, and maintaining the same length in both the normal mode and the operation mode. 用于包括双单元操作的写操作的时间由内部写周期时间IWR2 Time for two-unit operation comprises a write operation by the internal write cycle time IWR2

(后面描述的图26)表示。 (FIG. 26 described later) FIG.

在读命令RD之后,生成与存储器单元C00相对应的刷新命令REF After the read command RD, the memory cell C00 and generating the corresponding refresh command REF

(图25 (s))。 (FIG. 25 (s)). 标志F0AX已经通过与读操作相对应的双单元操作被复位到高电平。 F0AX flag has been reset to a high level by the read operation corresponding to the two-unit operation. 相应地,如图24 (q)到(t)中一样,执行第一存储器模式中的单单元操作(图25 (t))。 Accordingly, FIG. 24 (q) to (t) as in, performing a single unit operation (FIG. 25 (t)) of the first memory mode. 类似地,与存储器单元C10相对应的刷新操作也是单单元操作(图25 (u))。 Similarly, the memory cell C10 corresponds to a single unit operation is a refresh operation (Fig. 25 (u)).

图26示出了一个示例,其中在返回正常操作模式之后,在第一个刷 26 shows an example in which after the return to normal operating mode, a first brush

新请求REF之前提供了写命令WR。 It provides a write command WR until a new request REF. 换句话说,图26示出了对与置位状态中的标志FAX (F0AX, F1AX,…)、FBX (F1BX, F2BX,…)相对应的局部区域PA的写操作。 In other words, FIG. 26 shows a set state of the flag in the FAX (F0AX, F1AX, ...), FBX (F1BX, F2BX, ...) corresponding to the partial write area PA.

当标志FAX、 FBX处于置位状态中时,在内部写周期时间IWR2中执行写操作。 When the flag FAX, FBX in the set state, the write cycle time IWR2 internal write operation is performed. 在内部写周期时间IWR2中,RASZ信号的激活时段被设定得长于内部写周期时间IWR1中的激活时段(图26 (a))。 IWR2 internal write cycle time, the activation period of the RASZ signal is set to be longer than the internal write activation period (FIG. 26 (a)) of the cycle time IWR1. 依照RASZ 信号的激活时段,译码信号XDOX和标志输出信号S1AX、 S1BX的输出时段也被加长了(图26 (b、 c))。 In accordance with the activation period of the RASZ signal, and the decoded signal XDOX s1ax flag output signal, output period is also lengthened S1BX (FIG. 26 (b, c)).

如下面所示的,内部写周期时间IWR2包括一个刷新周期和一个写周期。 As shown below, the internal write cycle time IWR2 comprising a refresh cycle and a write cycle. 在刷新周期和写周期期间,读出放大器SA保持被激活。 During the refresh cycle and the write cycle, the sense amplifier SA remains activated. 这可以降低激活读出放大器的频率,并且可以使得内部写周期时间IWR2短于刷新周期时间IREF和写周期时间IWR1的和。 This can reduce the frequency to activate the sense amplifier, and the internal write cycle time can be made shorter than the refresh cycle time IWR2 IREF and IWR1 and write cycle time. 例如,内部写周期时间IWR2的长度可以是写周期时间IWR1的1.5到1.7倍。 For example, the length of the internal write cycle time IWR2 may be 1.5 to 1.7 times the write cycle time IWR1.

根据译码信号XDOX输出标志输出信号S1AX、 S1BX (图26 (d)) 以激活标志检测信号FDTC (图26 (e))的操作,以及响应于标志检测信号FDTC的激活而输出标志复位信号FRAX (图26 (f))以复位标志FAOX (图26 (g))的操作,与上述图24的操作相同。 The decoded signal output flag output signal XDOX S1AX, S1BX (FIG. 26 (d)) to activate a flag detection signal FDTC operation (FIG. 26 (e)), and a detection signal in response to the activation flag FDTC flag and outputs a reset signal FRAX (FIG. 26 (f)) to reset the flag named FAOX (FIG. 26 (g)) of the operation, the operation of FIG. 24 is the same as described above. 此外,标志检测信号FDTC的激活引起子字线SW0P、 SW1同时被激活(图26 (h)), 并且开始双单元操作(图26 (i))。 Further, the flag detection signal FDTC sub word line activation causes SW0P, SW1 are activated simultaneously (FIG. 26 (h)), and starts the operation unit bis (FIG. 26 (i)). 然后,数据被写回从其读取公共数据的存储器单元COO、 CIO。 Then, the data is written back to the data read from the common memory cell COO, CIO.

从RASZ信号的激活开始经过延迟电路DELAY1的延迟时间之后,图13所示的标志检测电路28将节点ND8改变到高电平,以去活标志检测信号FDTC,而不管标志输出信号S1AX如何(图26 (j))。 RASZ signal starts from the activation delay time after DELAY1 circuit, as shown in FIG. 13 the mark detection circuit 28 changes to the high level node ND8, flag detection signal to deactivate FDTC, regardless s1ax flag output signal (FIG. 26 (j)). 响应于标志检测信号FDTC的去活,图10所示的1/4字译码器44使得译码信号X00不被选择。 Flag detection signal in response to the deactivation FDTC 1/4 word decoder 1044 shown in FIG decoded signal such that X00 is not selected. 相应地,子字线SWOP (X0= "0")不被选择(图26 (k))。 Accordingly, the sub-word line SWOP (X0 = "0") is not selected (FIG. 26 (k)). 结果,双单元操作结束,并且只有子字线SW1 (X0= "1")被保持选择(图26 (1))。 As a result, two-unit operation is ended, and only the sub-word lines SW1 (X0 = "1") is kept selected (FIG. 26 (a)). 因此,1/4字译码器44操作为字控制电路,其在读出放大器SA的激活期间,使与未被指定为写目标的局部区域PA中的存储器单元C00连接的子字线SWOP不被选择。 Thus, 1/4 word decoder 44 operates as a digital control circuit, during which activates the sense amplifier SA, of the sub-word line and the memory cell C00 is not designated as the write destination of the partial area PA is not connected to the SWOP be chosen. 在子字线SW1被选择的时段期 In the period of the sub-word line selected SW1

间,读出放大器SA保持被激活。 Between the sense amplifier SA remains activated.

此后,写数据DT经由数据总线DB被提供到位线BL、 /BL,并且该数据只被写入与被选择的子字线SW1相连的存储器单元C10 (图26 (m))。 Thereafter, the write data DT are supplied to the bit line BL via the data bus DB, / BL, and the data is written only to memory cells connected to the selected word line sub SW1 is C10 (FIG. 26 (m)). 即,响应于写命令WR执行了写操作,并且新数据被写入被指定为写目标的存储器单元CIO。 That is, in response to the write command WR write operation is performed, and the new data is written is specified as the write target memory cell CIO. 注意,写数据DT与写命令WR同步地被提供到数据输入/ir出端DQ (图26 (n))。 Note that, the write data DT and the write command WR is supplied to the data input / ir the end of the DQ (FIG. 26 (n)) in synchronism.

因此,在存储器单元C00中所保持的数据通过双单元操作被刷新之后,数据被写入存储器单元C10,这使得可以直接从低功耗模式转移到正常操作模式,而不在存储器单元COO中引起任何数据丢失。 Thus, the memory cell C00 in the held data is refreshed after a two-unit operation, the data is written to memory cell C10, so that it can be transferred directly from the low power consumption mode to the normal operating mode, without causing any memory cell in the COO data lost. 之后,如图25 所示,顺序执行与存储器单元C00和存储器单元C10相对应的单单元刷新操作(图26 (o、 p))。 Thereafter, as shown in FIG. 25, the single sequential execution units and memory cells C00 and C10 corresponding to a memory cell refresh operation (Fig. 26 (o, p)).

图27到图29示出了在外部系统没有识别出刷新操作时,执行正常操作模式中的刷新操作的方法。 27 to 29 illustrate a method outside the system recognizes that the refresh operation is not performed in the normal operation mode of the refresh operation. 利用该方法,具有DRAM存储器核心的伪SRAM如同SRAM—样操作。 Using this method, having a DRAM memory core pseudo SRAM as SRAM- like operation.

图27示出了外部命令周期时间EXTC与内部读周期时间IRD之间的关系。 27 shows the relationship between the cycle time of the external command EXTC internal read cycle time and the IRD.

外部命令周期时间EXTC是从伪SRAM的外部部分提供的操作命令(在该示例中是读命令RD)的提供周期。 External command cycle time EXTC is supplied from the outer portion of the pseudo SRAM operation command (in this example the read command RD) of the supply period. 在本实施例中,外部命令周期时间EXTC被设定为与内部读周期时间IRD (或者写周期时间IWR1)和内部刷新周期时间IREF的和相等的一个值。 In the present embodiment, an external command EXTC cycle time is set to the internal read cycle time IRD (or write cycle time IWR1) and an internal refresh cycle time value and equal to IREF. 这保证了即使当读命令RD 以最小周期被连续地提供时,也可在内部读周期时间IRD之间插入内部刷新周期时间IREF。 This ensures that even when the read command RD to the minimum period is continuously supplied, can be inserted into the internal refresh cycle time IREF between the internal read cycle time IRD.

图28示出了外部命令周期时间EXTC与内部写周期时间IWR1之间的关系。 FIG 28 shows the relationship between the cycle time of the external command EXTC IWR1 the internal write cycle time.

由于内部写周期时间IWR1的长度等于内部读周期时间IRD的长度, 所以外部命令周期时间EXTC被设定为与内部写周期时间IWR1和内部刷新周期时间IREF的和相等的一个值。 Since the internal write cycle time IWR1 length equal to the length of the internal read cycle time IRD, the external command EXTC cycle time is set to the internal write cycle and the internal refresh IWR1 time value and a time period equal to IREF. 这保证了即使当写命令WR以最小周期被连续地提供时,也可在内部写周期时间IWR1之间插入内部刷新周期IREF。 This ensures that even when the write command WR to the minimum period is provided continuously, the cycle time can also be written in the insertion inside IWR1 between refresh cycles IREF. 图29示出了外部命令周期时间EXTC与内部写周期时间IWR2之间的关系。 FIG 29 shows the relationship between the cycle time and the internal write cycle time IWR2 external command EXTC.

外部命令周期时间EXTC被设定为比内部写周期时间IWR2和内'部刷新周期时间IREF的和小的一个值。 External command EXTC cycle time is set larger than the internal write cycle time IWR2 and the 'value of a portion of the refresh cycle time IREF and small. 如图26中所描述的,包括双单元操作的内部写周期时间IWR2大于内部写周期时间IWR1。 Depicted in FIG. 26, the operation unit includes a double internal write cycle time is greater than the internal write cycle time IWR2 IWR1. 因此,当在以最小周期连续地提供的写命令WR之间插入内部刷新周期IREF时,内部写周期IWR2被临时延迟。 Thus, when the internal refresh cycle is inserted between IREF WR minimum write cycle is continuously supplied command, the internal write cycle IWR2 is temporarily delayed. 但是,随着内部写周期IWR2被重复若干次,与写命令WR的偏离被消除了。 However, as the internal write cycle IWR2 be repeated several times, with the write command WR deviation is eliminated. 结果,即使当连续地出现包括双单元操作的内部写周期IWR2时,也可以在外部系统没有识别出刷新操作的情况下执行刷新操作。 As a result, even when the operation unit includes a double IWR2 When the internal write cycle occurs consecutively, you may not recognize the refresh operation is executed in the case where the refresh operation external system.

图30示出了第一实施例的伪SRAM的操作。 FIG 30 shows a first embodiment of the pseudo-SRAM operation. 图形下部的时序图是图形上部的时序图的延续。 FIG timing pattern is a continuation of the lower portion of the upper timing chart pattern.

在正常操作模式中,响应于刷新控制信号REFZ选择一个子字线SW (单单元操作)。 In the normal operation mode, the refresh control signal REFZ in response to a selected sub word line SW (single unit operation). 当CE信号改变到低电平以将正常操作模式改变到公共刷新模式时,为了首先选择局部字线SWP,图33所示的刷新地址计数器18的复位电路54a与模式信号MODE2的上升沿同步地将用于生成行地址信号RAD2的最低位X0的计数器54b复位。 When the CE signal changes to the low level to the normal operation mode is changed to the common refresh mode, select the first local word lines for the SWP, the rising edge of the reset circuit 54a and the mode signal MODE2 33 shown in FIG refresh address counter 18 in synchronization X0 is the least significant bit for generating the row address signal RAD2 counter 54b is reset.

在全部局部字线SWP被选择之后,操作模式从公共刷新模式转移到局部刷新模式。 After all the local word lines SWP is selected, the operation mode shifts from the common refresh mode to the partial refresh mode. 在局部刷新模式中,执行基于单刷新控制信号REFZ而选择两个相邻子字线SW的双单元操作(刷新操作)。 In partial refresh mode, the refresh is performed based on a single control signal REFZ selects two adjacent sub-word line SW of the operation unit bis (refresh operation).

当CE信号在局部刷新模式期间改变到高电平时,操作模式直接转移到正常操作模式。 When the CE signal changes to the high level during the partial refresh mode, the operation mode shifts to the normal operation mode directly. 在改变到正常操作模式之后,根据标志FAX、 FBX执行双单元操作或者单单元操作。 After changing to the normal operation mode according to the flag FAX, FBX operation unit performs a double or a single unit operation.

在上述这个实施例中,在数据保持模式期间,数据被保持在第二存储器模式中的多个存储器单元中,其中第二存储器模式是所谓的局部技术与双单元技术的结合,使得相比于第一存储器模式,可以使得数据保持时间 In this embodiment the above-described embodiment, during a data holding mode, the plurality of memory cell data is held in the second memory mode in which the second memory is a combination of so-called local mode and dual-cell technology techniques, such as compared to a first storage mode, such that the data retention time

更长。 Longer. 结果,可以大大降低存储器单元的刷新频率,得到数据保持模式期间的功耗的很大降低。 As a result, the refresh rate can greatly reduce the memory cells, greatly reducing the power consumption during the data retaining mode.

为每个局部区域PA都形成了用于指示存储器单元的存储器模式的标 Each local area PA is formed for a standard memory mode indicate that the memory unit

志FAX、 FBX,并且第一次访问需要在第二存储器模式中在每个局都区域PA中执行。 Chi FAX, FBX, and the first visit need to be performed in each local area PA are in the second memory mode. 这可以防止所访问的存储器单元中的数据丢失。 This prevents the data accessed memory cell is lost.

为每个局部区域PA都形成了用于指示存储器单元的存储器模式的标志FAX、 FBX,并且在从数据保持模式改变到正常操作模式的时候,根据标志FAX、 FBX访问存储器单元。 Each local area PA is formed FAX flag to indicate that the memory cells of the memory mode of the FBX, and when the data holding mode to the normal operation mode, according to the FAX flag, the FBX access memory cells. 这允许管理伪SRAM的系统即使在改变操作的期间也能自由地访问任何存储器单元。 This system allows the management of the pseudo SRAM can freely access any memory cell even during a change operation. 改变所需的实际时间变为零。 Change the actual time required to zero. 结果,在从数据保持模式返回到正常操作模式之后,管理伪SRAM的系统立即能够访问伪SRAM。 As a result, after the return from the data holding mode to the normal operating mode, the management system of the pseudo SRAM can be accessed immediately pseudo SRAM. 这使得例如当伪SRAM被用作蜂窝电话的工作存储器时,可以立即从待机状态返回到操作模式。 This makes for example, when the pseudo-SRAM is used as a work memory of the cellular telephone can immediately return from the standby state to the operation mode.

刚好在将操作从数据保持模式改变到正常操作模式之前,标志电路30 将全部标志FAX、 FBX置位。 Just prior to the operation from the data holding mode to the normal operation mode, all flags flag circuit 30 FAX, FBX set. 这使得可以保证全部局部区域PA的存储器单元的存储器模式被从第二存储器模式改变到第一存储器模式。 This makes it possible to ensure that all partial pattern memory area PA of the memory cell is changed from the second mode to the first memory storage mode.

标志FAX、 FBX的状态由标志检测电路28检测,使得可以容易地控制字译码器WDEC的1/4字译码器44的操作,这可以简化电路。 Flag FAX, FBX state detected by the mark detection circuit 28, making it possible to easily control the word decoder WDEC 1/4 word decoder 44 is operated, this circuit can be simplified.

当返回到正常操作模式后的第一次访问是写操作时,在通过双单元操作执行刷新操作之后,通过单单元操作写入数据。 When the first visit to return to normal operating mode after a write operation, after the refresh operation is performed by a two-unit operation, data is written by a single unit operation. 这可以保证未被执行数据写入的局部区域PA中的存储器单元中的数据被保持,并且数据被写入预定的存储器单元。 This ensures that the data is not performed in the partial area PA of the data write memory cell is maintained and data is written to a predetermined memory cell. 在返回到正常操作模式之后候,外部系统能够立即执行对伪SRAM的写操作。 After returning to normal operating mode candidate, the external system can perform the write operation of the pseudo SRAM immediately. 即,使能了系统的高速操作。 That is, high speed operation is enabled system.

当刚好在返回到正常操作模式之后的第一次访问是写操作时,读出放大器SA保持被激活,并且执行双单元刷新操作和单单元写操作。 When the first just after the return to normal operating mode once access is a write operation, the sense amplifier SA is kept activated, and the refresh operation and the single double unit cell write operation. 这可以降低读出放大器SA的激活频率,以縮短内部写周期时间IWR2。 This can reduce the frequency of activating the sense amplifier SA to shorten the internal write cycle time IWR2.

在返回到正常操作模式后的第一次写操作中,与未被指定为写目标的存储器单元连接的字线不被选择,而读出放大器SA保持激活。 In the return to normal operating mode after a write operation, the word line is not designated as a write target memory cell is connected is not selected, the sense amplifier SA remains active. 因此,利 Therefore, Lee

用简单的控制,可以执行双单元操作(在第二存储器模式中写回数据的操作)和单单元操作(在第一存储器模式中写数据的操作),而读出放大器 With a simple control unit may perform operations bis (write back the data in the second memory mode) and a single unit operation (data write operation of the memory in the first mode), while the sense amplifier

SA保持激活。 SA remains active.

当返回到正常操作模式后的第一次访问是读操作时,通过双单元操作执行刷新操作,并且被放大的读数据被输出到数据输入/输出端DQ。 When the first access is a read operation returns to the normal operating mode, the operation performed by the two-cell refresh operation, the read data is amplified and outputted to the data input / output terminal DQ. 这允许外部系统在返回到正常操作模式之后立即执行从伪SRAM的读操作。 This allows the external system to perform a read operation from the pseudo SRAM immediately after the return to normal operating mode. 即,使能了系统的高速操作。 That is, high speed operation is enabled system.

当返回到正常操作模式后的第一次访问是刷新操作时,通过双单'元操作执行刷新操作。 When the first access is a refresh operation is returned to the normal operating mode by a single dual 'Element operation refresh operation is performed. 由于写回数据的刷新操作,数据被牢靠地写入已经被访问以进行刷新操作的存储器单元。 Refresh operation since the write back data, the data is written has been securely accessed for the refresh operation of the memory cell. 因此,即使当对每个存储器单元执行单单元操作(第一存储器模式中的访问)时,数据也可以安全地被读取或者刷新。 Accordingly, even when (a first memory access mode) performing a single unit operation for each memory cell, data can be safely read or refreshed.

在从正常操作模式转移到数据保持模式时,每次生成刷新命令就执行读取存储在局部存储器单元中的数据和将所读取的数据写入局部区域PA 中的全部存储器单元的公共刷新操作,直到局部区域PA进入第二存储器模式状态中。 When transferring data from the normal operation mode to the hold mode, a refresh command is generated every time data and the read data is written to all memory cells in a local area PA in the local memory unit performing a refresh operation reads the stored common until a partial memory area PA enters a second mode state. 由于公共刷新操作,在第一存储器模式中存储在局部存储器单元中的数据可以以第二存储器模式存储在存储器单元组的存储器单元中。 Since the common refresh operation, the data stored in the local memory cells in the first memory in a second mode, memory mode may be stored in the memory cells of the memory cell group. 每次执行刷新操作时,第一存储器模式中的存储器单元就转变为第二存储器模式中的存储器单元,使得能够从正常操作模式有效地转移到数据保持模式。 Each time the refresh operation is performed, the first memory mode is transformed into the memory cells in the second memory mode memory cells, enabling efficient transfer of data from the normal operation mode to the hold mode.

图31示出了本发明的半导体存储器的第二实施例。 FIG 31 shows a second embodiment of the semiconductor memory of the present invention. 相同的参考标号或者符号被用于指明与第一实施例中所描述的元件相同的元件,并且将省略对它们的详细描述。 The same elements as the same reference numerals or symbols are used to designate the first embodiment as described, and the detailed description thereof will be omitted.

在本实施例中,代替第一实施例的刷新定时器14、刷新命令发生器16、刷新地址计数器18、标志复位电路26、标志检测电路28、标志电路30、核心控制电路32和存储器核心34,形成了刷新定时器14A、刷新命令发生器16A、刷新地址计数器18A、标志复位电路26A、标志检测电路28A、标志电路30A、核心控制电路32A和存储器核心34A。 In the present embodiment, in place of the refresh timer 14 of the first embodiment, the refresh command generator 16, a refresh address counter 18, a flag reset circuit 26, the mark detection circuit 28, flag circuit 30, a core control circuit 32 and the memory core 34 forming a refresh timer 14A, the refresh command generator. 16A, the refresh address counter. 18A, flag reset circuit 26A, the mark detection circuit 28A, flag circuit. 30A, a memory core control circuit 32A and core 34A. 核心控制电路32A的读出放大器控制电路40A和预充电控制电路42A接收从多路转换器24输出的行地址信号RAD的两个低位XI、 X0。 The core control circuit 32A of the read amplifier control circuit 40A and a precharge control circuit 42A receives the row address signal RAD two low output 24 of multiplexer XI, X0. 其他配置基本上与第一实施例的相同。 Other configuration is basically the same as the first embodiment.

图32示出了图31所示的刷新定时器14A的细节。 FIG 32 illustrates details of the refresh timer 31 shown in FIG. 14A.

刷新定时器14的分频器14b、 14c、 14f将OSC0信号的频率分别转换为八分之一、十六分之一和六十四分之一。 Refresh timer 14 of the divider 14b, 14c, 14f OSC0 frequency signals are converted to one-eighth, one-sixteenth and sixty fourth.

图33示出了刷新定时器14A和刷新命令发生器16A的操作。 FIG 33 illustrates operation of the refresh timer and a refresh command generator 14A to 16A. 当模式信号MODEl、 MODE2或MODE3处于高电平时,刷新定时器14A分别输出振荡信号OSCl、 OSC2或OSC3作为刷新请求信号TRfiF。 When the mode signal MODEl, MODE2 MODE3 or at a high level, the refresh timer 14A outputs an oscillation signal OSCl, OSC2 or OSC3 as the refresh request signal TRfiF. 当模式信号MODE1或MODE3处于高电平时,刷新命令发生器16A将刷新请求信号TREF输出为刷新控制信号REFZ。 When the mode signal MODE3 MODE1 or at a high level, the refresh command generator 16A outputs the refresh request signal TREF refresh control signal REFZ. 当模式信号MODE2处于高电平时,刷新命令发生器16A与刷新请求信号TREF同步地输出刷新控制信号REFZ四次。 When the mode signal MODE2 is at the high level, the refresh command generator 16A and outputs the refresh request signal TREF refresh control signal REFZ in synchronization four times.

图34示出了图31所示的刷新地址计数器18A的细节。 34 shows a detail of the refresh address counter 31 shown in FIG. 18A. 刷新地址计数器18A具有复位电路18a,计数器18d、 18e以及控制计数器18d、 18e的逻辑门。 18A refresh address counter having a reset circuit 18a, the counter 18d, 18e, and controls the counter 18d, 18e of the logic gate. 计数器18d与刷新控制信号REFZ同步地执行计数操作,并生成刷新地址信号REFAD的两个低位Rl、 R0。 Counters 18d and performs refresh control signal REFZ in synchronization with the counting operation, and generates a refresh address signal REFAD two low Rl, R0. 当模式信号MODE3处于高电平时,计数器18d与模式信号MODE2的上升沿同步地被复位。 When the mode signal MODE3 is high, the rising edge of the counter 18d is reset the mode signal MODE2 synchronization.

当模式信号MODE3处于高电平时,计数器18e与刷新控制信号REFZ同步地执行计数操作,并更新刷新地址信号REFAD的四个高位R5〜2。 When the mode signal MODE3 at a high level, the counter 18e and the refresh control signal REFZ performs a counting operation in synchronization, and update four upper R5~2 the refresh address signal REFAD. 当模式信号MODE1或MODE2处于高电平时(除去模式信号MODE2的上升沿之后的预定时段之外),计数器18e与从计数器18d输出的地址信号R1同步地执行计数操作。 When the mode signal MODE1 or MODE2 is at high level (outside of the predetermined period of time after the rising edge of the mode signal MODE2 removed), the counter 18e performs the counting operation in synchronism with the address signal from the output of the R1 counter 18d.

图35示出了图34所示的刷新地址计数器18A的操作。 FIG 35 shows an operation of the refresh address counter 34 shown in FIG. 18A. 当模式信号MODE1或MODE2处于高电平时,刷新地址计数器18A 与刷新控制信号REFZ同步地将刷新地址信号的6个位R5〜0顺序地加起来。 When the mode signal MODE1 or MODE2 is at high level, the refresh address counter 18A and the refresh control signal REFZ sequentially R5~0 6 bits of the refresh address signal in synchronism together. 此外,当模式信号MODE3处于高电平时,刷新地址计数器18A与刷新控制信号REFZ同步地将刷新地址信号的4个位R5〜2顺序地加起来。 Further, when the mode signal MODE3 at a high level, the refresh address counter 18A and the refresh control signal REFZ sequentially R5~2 4 bits of the refresh address signal in synchronism together. 此时,刷新地址信号R1、 RO被固定到低电平。 At this time, the refresh address signals R1, RO is fixed to the low level.

图36示出了图31所示的存储器核心34A的基本部分的细节。 Figure 36 shows a detail of the basic portion of the memory core 31 shown in FIG. 34A. 存储器核心34A的字译码器WDEC具有1/4字译码器44和多个分别与主字线MW (MW0, MW1,...)相对应的子字译码器46a。 The memory core 34A has a word decoder WDEC 1/4 word decoder 44, respectively, and a plurality of main word line MW (MW0, MW1, ...) corresponding to the sub-word decoders 46a. 当模式信号MODE3处于低电平时,1/4字译码器44A根据行地址信号RAD2的两个低位X1、 X0及其相反位/X1、 /X0,输出译码信号Xll、 XIO、 XOl、 X00中 When the mode signal MODE3 at a low level, 1/4 word decoder 44A according to a row address signal RAD2 two low X1, X0 and the opposite bit / X1, / X0, the output decoded signals Xll, XIO, XOl, X00 in

的一个。 one of. 当模式信号MODE3处于高电平时,1/4字译码器44A将全部译码信号Xll、 XIO、 XOl、 X00设定为高电平。 When the mode signal MODE3 is at a high level, 1/4 word decoder 44A decodes the signal all Xll, XIO, XOl, X00 is set to the high level.

在本实施例中,与四条相邻的子字线(例如,SW0P、 SW1、 SW2、 SW3)相连的存储器单元(COO、 C10、 C20、 C30)构成每个局部区域PA。 In the present embodiment, the memory cell (COO, C10, C20, C30) of four adjacent sub-word lines (e.g., SW0P, SW1, SW2, SW3) connected to constitute each local area PA. 例如,子字线SWOP是与局部存储器单元C00相连的局部字线,其中在数据保持模式期间,局部存储器单元C00的数据被保持,子字线SW1、 SW2、 SW3是与公共存储器单元C10、 C20、 C30相连的公共字线,其中在数据保持模式期间,公共存储器单元C10、 C20、 C30的数据不被保持。 For example, the sub-word line SWOP is the local word lines and local memory cell C00 is connected, wherein during the data holding mode, the local memory cell C00 of data is held, the sub-word lines SW1, SW2, SW3 is common memory cells C10, C20 during C30 connected to a common word line, wherein the data holding mode, the common memory cells C10, C20, C30 data is not held.

局部存储器单元C00和公共存储器单元C20连接到位线BLO,公共存储器单元CIO、 C30连接到位线/BL0。 Local memory cells C00 and C20 common memory cells connected to bit lines BLO, the common memory unit CIO, C30 connected to bit line / BL0. 局部字线SWOP和公共字线SW1、 SW2、 SW3在数据保持模式期间彼此同步地被选择,使得四个存储器单元被同时访问(第二存储器模式,四单元操作)。 SWOP local word lines and a common word line SW1, SW2, SW3 are selected during the data holding mode in synchronization with each other, so that four memory cells are accessed simultaneously (a second storage mode, the four-cell operation). 然后,在正常操作模式期间在局部存储器单元C00中保持的数据在数据保持模式期间被四个存储器单元COO、 CIO、 C20、 C30保持。 Then held in the local memory cell C00 during normal operation mode data in the data holding mode is held during the four memory cells COO, CIO, C20, C30.

在本实施例中,在存储器核心34A中形成的存储器单元MC中的四分之一是局部存储器单元。 In the present embodiment, a quarter of the memory cell MC in the memory core 34A is formed in the partial memory cells. 即,在数据保持模式期间,保持了与伪SRAM的存储器容量的四分之一相对应的数据。 That is, the data holding mode during the holding data corresponding to a quarter of the memory capacity of the pseudo SRAM.

图37示出了图36所示的1/4字译码器44A的细节。 37 shows a detail of a quarter word decoder shown in FIG. 36 44A.

1/4字译码器44A具有译码器44a和掩码电路44c,译码器44a对行地址信号X0、 XI、 /X0、 /XI译码,以生成译码信号Xll、 XIO、 XOl、 XOO,掩码电路44当模式信号MODE3或者标志检测信号FDTC处于高电平时,对行地址信号X0、 /X0、 XI、 /XI进行掩码,以输出高电平到译码器44a。 1/4 word decoder having a decoder 44A and the mask circuit 44c 44a, 44a of the row address decoder signals X0, XI, / X0, / XI decoded to generate a decoded signal Xll, XIO, XOl, XOO, when the mask circuit 44 when the mode signal or a flag detection signal MODE3 FDTC at the high level, the row address signals X0, / X0, XI, / XI masked, to output a high level to the decoder 44a.

图38示出了图31所示的读出放大器控制电路40A和预充电控制电路42A的操作。 FIG. 38 shows the read amplifier shown in FIG. 31, and a control circuit 40A controls the operation of the precharge circuit 42A. 当模式信号MODE2处于低电平时的操作以及当模式信号MODE2改变到高电平时的操作与第一实施例中的操作(图12)相同。 When the same operations (Fig. 12) operation and the operation when the mode signal MODE2 mode signal MODE2 when changing at a low level to a high level in the first embodiment.

当模式信号MODE2处于高电平时,在行地址信号XI、 X0两者都改变到高电平之后,从RASZ信号的上升沿开始的延迟时间DLY2之后,读 When the mode signal MODE2 then at a high level, both the row address signal XI, X0 changed to the high level after the delay time from the rising edge of the start signal RASZ DLY2, read

出放大器控制电路40A改变读出放大器激活信号PSA、 NSA,并使读出放大器SA去活(图38 (a))。 Amplifier control circuit 40A changes the sense amplifier activation signals PSA, NSA, and the sense amplifier SA is deactivated (FIG. 38 (a)). 当模式信号M0DE2处于高电平时,在行地址信号X1、 XO两者都改变到高电平之后,从RASZ信号的上升沿开始的延迟时间DLY2之后,预充电控制电路42A将预充电信号PREZ改变到高电平,并开始预充电操作(图38 (b))。 After M0DE2 When the mode signal at a high level, both the row address signals X1, XO changed to the high level after the delay time from the rising edge of the start signal RASZ DLY2, precharge control circuit 42A changes the precharge signal PREZ to the high level, and starts the precharge operation (in FIG. 38 (b)).

因此,在公共刷新模式期间,读出放大器SA保持激活,并且位线BL、 /BL的预充电被禁止,而RASZ信号被输出四次,以便将局部存储器单元C00中所保持的数据写入局部存储器单元和相邻的公共存储器单元CIO、 C20、 C30。 Thus, during a common refresh mode, the sense amplifier SA remains activated, and the bit lines BL, / BL to the precharge is disabled, the RASZ signal is output four times, so that the local memory cell C00 is written in the data held locally memory cells and memory cells adjacent common CIO, C20, C30.

图39示出了在图31中所示的标志电路30A和标志检测电路28A的细节以及字译码器WDEC的基本部分的细节。 And FIG. 39 shows the details of the flag circuit 30A, and the mark detection circuit shown in FIG. 31 28A details essential part of the word decoder WDEC. 字译码器WDEC与第一实施例的字译码器WDEC (图13)相同。 (FIG. 13) the same word decoder WDEC word decoder WDEC of the first embodiment.

为每个主字线MW (MWO, MW1,.,.)形成标志电路30A。 Flag circuit 30A is formed for each of the main word line MW (MWO, MW1,.,.). 每个标志电路30A具有与第一实施例的标志电路30相同的标志FAX (FOAX, F1AX,...)。 Each circuit 30A has the same sign flag circuit 30 of the first embodiment of the flag FAX (FOAX, F1AX, ...). 标志FAX的功能与第一实施例的相同。 Flag FAX function is the same as the first embodiment. 具体地说,各个标志FAX与局部模式释放信号PREFR的脉冲同步地被置位到低电平,并且与标志复位信号同步地被复位到高电平。 Specifically, each of the local FAX mode flag release PREFR pulse signal being set to a low level in synchronization, and the flag is reset to a high level reset signal in synchronization. 标志FAX的状态与译码信号XDX (XDOX, XD1X,,..)同步地被输出为标志输出信号S1AX。 And decoding the status flag of the FAX signal XDX (XDOX, XD1X ,, ..) flag is outputted as an output signal in synchronization S1AX.

标志检测电路28A具有与标志输出信号线S1AX相连的锁存电路、延迟电路DELAY1以及掩码电路MSK。 Mark detection circuit with the latch circuit 28A having a flag output signal line connected to S1AX, a delay circuit DELAY1, and the mask circuit MSK. 掩码电路MSK将标志输出信号S1AX输出为标志检测信号FDTC,并具有当提供了写命令时縮短标志检测信号FDTC的激活时段的功能。 Mask circuit MSK outputs the flag as a flag output signal S1AX FDTC detection signal, and a detection signal with a shortened FDTC flag when the write command is provided to activate functions period.

标志电路30A和标志检测电路28A的操作与第一实施例中响应于标志FOAX的操作相同,因此,对它们的描述将被省略。 Operation flag circuits 30A and 28A to the mark detection circuit responsive to the first embodiment, the same operation flag FOAX, therefore, description thereof will be omitted.

图40示出了图31所示的标志复位电路26A的细节。 FIG 40 shows a detail flag is reset circuit 31 shown in FIG. 26A.

标志复位电路26A具有缓冲器电路26b,以代替第一实施例中的标志复位电路26的多路转换器MUX2 (图18)。 Flag is reset circuit 26A includes a buffer circuit 26b, in place of the multiplexer in the embodiment of the reset circuit 26 MUX2 are flag (FIG. 18) of the first embodiment. 其他配置与标志复位电路26 的相同。 The other configuration flag is reset circuit 26. 在从标志检测信号FDTC的上升沿开始的预定时段之后,标志复位电路26A输出标志复位信号FRAX。 After a predetermined period starting from the rising edge detection signal FDTC flag, the flag is reset flag circuit 26A outputs the reset signal FRAX. 图41示出了第二实施例中在正常操作模式期间的操作。 FIG 41 shows a second embodiment of the operation during the normal operation mode. 在正常操作模式期间,类似于第一实施例(图20),根据行地址信号RAD2,字线SW0P、 SW1、 SW3、 SW4被独立地选择。 During normal operation mode, similar to the first embodiment (FIG. 20), according to the RAD2 row address signal, the word line SW0P, SW1, SW3, SW4 are independently selected. 然后,响应于外部读命令或写命令,执行读操作或写操作。 Then, in response to an external read command or write command, a read or write operation. 响应于伪SRAM中内部生成的刷新命令,执行刷新操作。 In response to a refresh command generated inside the pseudo SRAM, performs a refresh operation.

图42示出了第二实施例中在公共刷新模式期间的操作。 FIG 42 shows a second embodiment during the operation of the common refresh mode. 在公共刷新模式中,局部存储器单元C00中所保持的数据首先被锁存在读出放大器SA中(图42 (a))。 In the common refresh mode, the memory cells C00 local data held in the first sense amplifier SA in the presence (FIG. 42 (a)) lock. 接着,在读出放大器SA保持激活的时候,公共存储器单元CIO、 C20、 C30被顺序地访问,并且读出放大器SA中锁存的数据(互补数据)被写入这些存储器单元CIO、 C20、 C30 (图42 (b、 c、 d))。 Next, remains active in the sense amplifier SA, when the common memory unit CIO, C20, C30 are sequentially accessed and latched in the sense amplifier SA data (complementary data) is written into the memory cells CIO, C20, C30 (FIG. 42 (b, c, d)). 所以,互补数据被保持在局部存储器单元COO和公共存储器单元CIO、 C20、 C30中。 Therefore, complementary data is held in the local memory unit and the common memory cell COO CIO, C20, C30 in. 对全部局部区域PA执行上述操作。 Do this for the entire local area PA. 图43示出了第二实施例中在局部刷新模式期间的操作。 FIG 43 shows a second embodiment, the operation during the partial refresh mode. 在局部刷新模式中,局部字线SWOP和公共字线SW1、 SW2、 SW3 同时被选择,并且局部存储器单元COO和公共存储器单元CIO、 C20、 C30 中所保持的互补数据同时被读出放大器SA放大,并被写回存储器单元COO、 CIO、 C20、 C30 (四单元操作)。 In partial refresh mode, the local word lines SWOP and the common word line SW1, SW2, SW3 are simultaneously selected, and the local memory cells COO and the common memory unit CIO, C20, complementary data C30 are held simultaneously sense amplifier SA amplifies and is written back to memory cells COO, CIO, C20, C30 (four unit operations). 互补数据被保持在局部存储器单元COO和公共存储器单元CIO、 C20、 C30中,使得相比于第一实施例, 刷新周期可以进一步被加长。 Complementary data is held in the local memory unit and the common memory cell COO CIO, C20, C30 in comparison to that of the first embodiment, the refresh cycle can be further lengthened.

上述这个实施例也可以提供与前述第一实施例相同的效果。 The same effect as the above-described embodiments this embodiment may also be provided with the aforementioned first embodiment. 此外,在该实施例中,单个局部存储器单元COO中所保持的数据在数据保持模式期间被保持在局部存储器单元COO和公共存储器单元CIO、 C20、 C30中, 使得可保持数据的保持时间能够被进一步加长。 Further, in this embodiment, a single local memory cell COO held in the data holding period mode is held in the local memory cells COO and the common memory unit CIO, C20, C30 in the data, so that the retention time can hold data can be further extended. 这可以进一步地降低刷新操作的频率,使得数据保持模式期间的功耗可以被大大降低。 This may further reduce the frequency of the refresh operation, so that power consumption during the data holding mode can be significantly reduced.

前述实施例己经描述了将本发明应用于伪SRAM的示例,但是本发明并不限于这样的实施例。 The foregoing embodiments have described examples applied to a pseudo SRAM of the present invention, but the present invention is not limited to such embodiments. 例如,本发明可以应用于具有自刷新功能的DRAM。 For example, the present invention may be applied to a DRAM with self-refresh function.

前述实施例已经描述了CE信号、/WE信号和/OE信号被用作命令信号的示例。 The foregoing embodiment has described a CE signal, / WE signal and the / OE signal is used as an example of the command signal. 但是,本发明并不限于这样的实施例。 However, the present invention is not limited to such embodiments. 例如,在DRM中,行 For example, in DRM, OK

地址选通信号/RAS和列地址选通信号/CAS可以被用作命令信号。 Address strobe signal / RAS and column address strobe signal / CAS signal may be used as a command.

前述实施例已经描述了当芯片使能信号CE处于低电平时操作模式被设定到数据保持模式(低功耗模式)的示例。 Embodiments have been described in the foregoing embodiments when the chip enable signal CE is at a low level when the operation mode is set to the sample data holding mode (low power mode). 本发明并不限于这样的实施例。 The present invention is not limited to such embodiments. 例如,如下的设计也是可以接受的:经由外部接线端接收两个芯片使能信号/CEl、 CE2,当/CEl处于低电平而CE2处于高电平时,正常读操作和写操作是可执行的,而当CE2信号处于低电平时,操作模式被设定到数据保持模式。 For example, the following design is also acceptable that: two receiving a chip enable signal / CEl, CE2 via an external terminal, when / CEl CE2 at a low level and the high level, normal read and write operations are executable , when the CE2 signal at the low level, the operation mode is set to the data holding mode.

本发明并不限于上述实施例,可以作出各种修改而不脱离本发明的精神和范围。 The present invention is not limited to the above embodiments, various modifications may be made without departing from the spirit and scope of the invention. 可以对部分或者全部部件作出任意改进。 Modifications may be made to any part or all of the components.

实用性 Practicality

根据本发明的半导体存储器,在将存储器单元的状态从第二存储器模式改变到第一存储器模式的改变操作中,第二存储器模式中的第一次访问的执行可以防止所访问的存储器单元中的数据丢失。 The semiconductor memory according to the present invention, in the state of the memory cell to change from the second mode to the first memory storage mode change operation, a second mode memory access of the first memory cell can be prevented from being accessed in data lost.

标志的使用允许在改变操作期间,以第二存储器模式保持数据的存储器单元与以第一存储器模式保持数据的存储器单元同时存在。 Allowed to use the logo changes during operation, the second memory holding data in a pattern memory unit to the first memory holding data mode memory cells exist. 当从第二存 When the second memory

储器模式转移到第一存储器模式时,通过以与标志相符合的模式访问存储器单元,即使在改变操作期间,管理半导体存储器的系统也被允许自由地访问存储器单元。 When the mode is transferred to the first reservoir memory mode, the memory access unit and the marker pattern consistent, even during the change operation, the semiconductor memory management systems also allowed to freely access a memory cell. 结果,可以消除实际的改变时间。 As a result, the actual change time can be eliminated.

根据本发明的半导体存储器,标志置位电路在改变操作之前将全部标志置位。 The semiconductor memory according to the present invention, the flag setting circuit changing operation before all flag. 这保证了全部存储器单元组的存储器单元都从第二存储器模式转移到第一存储器模式。 This ensures that all memory cells of the memory cell groups of the memory are transferred from the second mode to the first mode memory.

根据本发明的半导体存储器,当第一次访问是写操作时,以第二存储器模式保持的数据被以第二存储器模式再次写回多个存储器单元。 The semiconductor memory according to the present invention, when the first access is a write operation, the second memory holding data pattern in the second memory is a write-back mode, a plurality of memory cells again. 此后, 数据被写入被指定为写目标的存储器单元。 Thereafter, the data is written in the memory cell is specified as the write target. 因此,即使当给出了对以第二存储器模式保持数据的存储器单元中的一个存储器单元的写指令时,也可以在预定的存储器单元中保持新的写数据,而没有任何原始数据的丢失。 Thus, even when a write instruction is given to the memory cells in the second memory holding data mode when a memory cell can be maintained in the new write data in a predetermined memory cell, without any loss of original data. 结果,即使在改变操作期间,当执行写操作时,系统也不需要等待。 As a result, even during changing operation, when a write operation is performed, the system does not need to wait.

根据本发明的半导体存储器,在数据从存储器单元被读取、被写回存 The semiconductor memory according to the present invention, the data is read from the memory means is written back to memory

储器单元或者写入存储器单元的时候,读出放大器保持激活。 The reservoir unit or when written to the memory cells, sense amplifiers remain active. 因此,可以降低激活读出放大器的频率,以縮短写操作所需的时间。 Thus, it is possible to reduce the frequency to activate the sense amplifier, in order to shorten the time required for the write operation.

根据本发明的半导体存储器,写数据不被传送到与未被选择的字线相连的存储器单元。 The semiconductor memory according to the present invention, the write data is not transmitted to the unselected memory cells connected to the word line. 因此,利用简单的控制,可以在读出放大器被激活的同时,执行第二存储器模式的数据写回操作和第一存储器模式的数据写入操作。 Accordingly, with simple control, the sense amplifier may be activated simultaneously, performing a second data storage mode and a write-back operation mode data of the first memory write operation.

根据本发明的半导体存储器,当第一次访问是读操作时,即使在改变操作期间,系统在执行读操作时也不需要等待。 The semiconductor memory according to the present invention, when the first access is a read operation, even during the changing operation, when the system performs the read operation does not need to wait.

根据本发明的半导体存储器,当第一次访问是刷新操作时,以第二存储器模式保持的数据被以第二存储器模式再次写回多个存储器单元。 The semiconductor memory according to the present invention, when the refresh operation is first accessed, a second memory holding a data pattern in the second memory is a write-back mode, a plurality of memory cells again. 因此,即使当每个存储器单元此后以第一存储器模式被访问时,也可以无误地读取或刷新数据。 Therefore, even when each memory cell in the first memory mode after being accessed, may be correctly read or refresh the data.

根据本发明的半导体存储器,即使当第一次存储器模式的存储器单元和第二存储器模式的存储器单元同时存在时,系统也可以在从数据保持模式转移到正常操作模式之后立即访问半导体存储器。 The semiconductor memory immediately after the access to the semiconductor memory of the present invention, even when the first memory unit and a second mode memory storage mode memory cells exist, the system may be shifted to the normal operation mode from the data hold mode.

根据本发明的半导体存储器,通过公共刷新操作,每次执行刷新操作时,第一存储器模式中的存储器单元的状态就被转变到第二存储器模式, 这使得能够从正常操作模式有效地改变到数据保持模式。 According to the semiconductor memory of the present invention, the common refresh operation, each refresh operation is performed, a first state of the memory cell to the memory mode is shifted to the second memory mode, which makes it possible to effectively change the normal operation mode to the data from the hold mode.

根据本发明的半导体存储器,通过选择单条字线或者多条字线,可以容易地访问第一存储器模式或者第二存储器模式中的存储器单元。 The semiconductor memory according to the present invention, by selecting a single word line or multiple word lines can be easily access the first memory or the second mode, memory mode memory cells.

Claims (11)

1. 一种半导体存储器,包括: 多个易失性存储器单元; 分别与所述存储器单元连接的多条字线;多个存储器单元组,'每个存储器单元组由分别与预定数量的所述字线连接的所述存储器单元组成;控制电路,所述控制电路执行第一存储器模式和第二存储器模式的操作,所述第一存储器模式是其中每个所述存储器单元独立地保持数据的模式,所述第二存储器模式是其中每个所述存储器单元组中的存储器单元保持相同数据的模式;多个标志,所述标志被形成以分别对应于所述存储器单元组,并且作为置位状态指示所述存储器单元以所述第二存储器模式存储数据;和标志复位电路,所述标志复位电路在将全部所述存储器单元的状态从所述第二存储器模式改变到所述第一存储器模式的改变操作中,响应于对所述存储器单元组中的相应存储器单元组的第一次 1. A semiconductor memory, comprising: a plurality of volatile memory cells; a plurality of word lines respectively connected to the memory cells; a plurality of memory cells, "each memory cell of the group consisting of said predetermined number of respectively a word line connected to the memory units; and a control circuit, the memory control circuit performs a first operation mode and the second storage mode, the first mode is a memory wherein each of said memory cell data holding mode independently the second mode is a memory wherein each of said memory cells of the memory cell remains in the same pattern data; a plurality of markers, said markers are formed to correspond to the memory cells, and a set state indicating that the memory cells in the second pattern memory for storing data; and a flag reset circuit, the reset circuit when the flag states of all the memory cell is changed from the second mode to the first memory storage mode changing operation in response to a respective one of the first group of memory cells in the memory cell groups 问,复位每个所述标士心o Q, each of said reset Sum subscript o
2. 根据权利要求1所述的半导体存储器,还包括标志置位电路,所述标志置位电路在所述改变操作之前将全部所述标志置k。 2. The semiconductor memory according to claim 1, further comprising a flag circuit is set, the flag is set before the circuit changing operation all the flag k.
3. 根据权利要求1所述的半导体存储器,还包括标志检测电路,当所述存储器单元被访问时,所述标志检测电路检测相应的标志是否被置位,其中所述控制电路根据所述标志检测电路的检测结果,执行第一存储器模式和第二存储器模式之一的操作。 3. The semiconductor memory according to claim 1, further comprising a mark detection circuit, when the memory cell is accessed, whether the corresponding flag of the flag detection circuit for detecting the position, wherein the control circuit according to the flag the detection result of the detection circuit, performs a first memory operation mode and the second mode memory.
4. 根据权利要求1所述的半导体存储器,其中当所述第一次访问是写操作时,所述控制电路从存储器单元组的全部所述存储器单元读取数据,以将所读取的数据写回全部所述存储器单元, 并且将数据写入所述存储器单元中被指定为写目标的一个存储器单元。 4. The semiconductor memory according to claim 1, wherein when the first access is a write operation, the control circuit reads data from all the memory cells of the memory cell, the read data write back all of the memory cells and writing data to a memory cell of said memory cell is designated as a write target.
5. 根据权利要求4所述的半导体存储器,还包括: 与所述存储器单元连接的位线;和与所述位线连接的读出放大器,其中在从所述存储器单元读取数据、将数据写回所述存储器单元以及向所述存储器单元写入数据的同时,所述控制电路保持所述读出放大器激活。 The semiconductor memory according to claim 4, further comprising: a bit line connected to the memory cells; and a read bit line connected to the sense amplifier, wherein read data from the memory unit, the data the write-back memory means and simultaneously writing data to the memory unit, the control circuit holds the sense amplifier activation.
6. 根据权利要求5所述的半导体存储器,还包括字控制电路,所述字控制电路在所述读出放大器激活的时候使得字线不被选择,所述字线被连接到存储器单元组中除了被指定为写目标的存储器单元之外的存储器单元。 6. The semiconductor memory according to claim 5, further comprising a control circuit of the word, the word control circuit when the sense amplifier is not activated so that the selected word line, said word line is connected to the memory cell group in addition to being designated as a write target memory cell of the memory cell.
7. 根据权利要求1所述的半导体存储器,其中当所述第一次访问是读操作时,所述控制电路从存储器单元组的全部所述存储器单元读取数据,以将所读取的数据输出到所述半导体存储器的外部部分,并且将所读取的数据写回所述存储器单元。 7. The semiconductor memory according to claim 1, wherein when the first access is a read operation, the control circuit reads data from all the memory cells of the memory cell, the read data output to an external portion of the semiconductor memory, and the read data is written back to the memory cell.
8. 根据权利要求1所述的半导体存储器,其中当所述第一次访问是刷新操作时,所述控制电路从存储器单元组的全部所述存储器单元读取数据,以将所读取的数据写回所述存储器单元。 8. The semiconductor memory according to claim 1, wherein when the refresh operation is first accessed, the control circuit reads data from all the memory cells of the memory cell, the read data write back to the memory cell.
9. 根据权利要求1所述的半导体存储器,还包括: 正常操作模式,其中所述半导体存储器根据外部提供的访问命令以及内部生成的刷新命令进行操作;和数据保持模式,其中所述半导体存储器仅根据所述刷新命令进行操作,其中在所述正常操作模式期间,数据以第一存储器模式进行存储,而在所述数据保持模式期间,数据以第二存储器模式进行存储,并且在从所述数据保持模式到所述正常操作模式的改变操作中,所述第一存储器模式中的存储器单元和所述第二存储器模式中的存储器单元同时存在。 9. The semiconductor memory according to claim 1, further comprising: a normal operating mode, wherein said semiconductor memory operates in accordance with an externally supplied access command and a refresh command is internally generated; and a data hold mode, wherein said semiconductor memory only the operation of the refresh command, wherein during said normal operation mode, data is stored in a first memory mode, and during the data holding mode, data is stored in the second memory mode, and the data from the changing the operating mode to the normal holding operation mode, the first memory mode memory cell and said second memory mode memory cells exist.
10. 根据权利要求9所述的半导体存储器,其中:存储器单元组的所述存储器单元包括局部存储器单元,所述局部存储器单元存储在第二存储器模式期间被保持的数据;并且在从所述正常操作模式转移到所述数据保持模式之后,每次生成刷新命令时,所述控制电路就执行公共刷新操作,所述公共刷新操作读取所述局部存储器单元中所存储的数据以将所读取的数据写入存储器单元组的全部所述存储器单元,直到全部所述存储器单元组的状态转移到第二存储器模式。 10. The semiconductor memory according to claim 9, wherein: the group of memory cells of memory cells includes a local memory unit, the data held in said local memory unit is stored in the memory during the second mode; and from the normal after the operation mode shifts to the data hold mode, each time a refresh command is generated, the control circuit executes a refresh operation common, the common refresh data read operation of the local memory unit stored in the read all of the data written to the memory cells of the memory cell groups, a state until all of the memory cells is transferred to the second memory mode.
11.根据权利要求1所述的半导体存储器,其中:与单条字线连接的单个存储器单元以第一存储器模式保持一位数据;并且存储器单元组的全部所述存储器单元以第二存储器模式保持数据。 11. The semiconductor memory according to claim 1, wherein: a single memory cell connected to the single word line in a first memory holding a data pattern; and all memory cells of the memory cells in the second memory holding data mode .
CN 03824440 2002-04-25 2003-04-24 Semiconductor memory CN100452239C (en)

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