KR102548402B1 - 병렬 프로세서 커널들의 디스패치 크기에 대한 동시 실행 인수를 결정하기 위한 시스템 및 방법 - Google Patents

병렬 프로세서 커널들의 디스패치 크기에 대한 동시 실행 인수를 결정하기 위한 시스템 및 방법 Download PDF

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KR102548402B1
KR102548402B1 KR1020177033219A KR20177033219A KR102548402B1 KR 102548402 B1 KR102548402 B1 KR 102548402B1 KR 1020177033219 A KR1020177033219 A KR 1020177033219A KR 20177033219 A KR20177033219 A KR 20177033219A KR 102548402 B1 KR102548402 B1 KR 102548402B1
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kernel
mini
kernels
workgroups
parallel processor
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KR20180011096A (ko
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라시지트 센
인드라니 파울
웨이 후앙
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어드밴스드 마이크로 디바이시즈, 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/545—Interprogram communication where tasks reside in different layers, e.g. user- and kernel-space
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3404—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for parallel or distributed programming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3433—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment for load management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/445—Program loading or initiating
    • G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4893—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues taking into account power or heat criteria
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
KR1020177033219A 2015-05-13 2016-03-22 병렬 프로세서 커널들의 디스패치 크기에 대한 동시 실행 인수를 결정하기 위한 시스템 및 방법 Active KR102548402B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/710,879 2015-05-13
US14/710,879 US9965343B2 (en) 2015-05-13 2015-05-13 System and method for determining concurrency factors for dispatch size of parallel processor kernels
PCT/US2016/023560 WO2016182636A1 (en) 2015-05-13 2016-03-22 System and method for determining concurrency factors for dispatch size of parallel processor kernels

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KR20180011096A KR20180011096A (ko) 2018-01-31
KR102548402B1 true KR102548402B1 (ko) 2023-06-27

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EP (1) EP3295300B1 (enExample)
JP (1) JP6659724B2 (enExample)
KR (1) KR102548402B1 (enExample)
CN (1) CN107580698B (enExample)
WO (1) WO2016182636A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10324730B2 (en) * 2016-03-24 2019-06-18 Mediatek, Inc. Memory shuffle engine for efficient work execution in a parallel computing system
US20180115496A1 (en) * 2016-10-21 2018-04-26 Advanced Micro Devices, Inc. Mechanisms to improve data locality for distributed gpus
US10558499B2 (en) * 2017-10-26 2020-02-11 Advanced Micro Devices, Inc. Wave creation control with dynamic resource allocation
US12405790B2 (en) * 2019-06-28 2025-09-02 Advanced Micro Devices, Inc. Compute unit sorting for reduced divergence
US11900123B2 (en) * 2019-12-13 2024-02-13 Advanced Micro Devices, Inc. Marker-based processor instruction grouping
US11809902B2 (en) * 2020-09-24 2023-11-07 Advanced Micro Devices, Inc. Fine-grained conditional dispatching
US20220334845A1 (en) * 2021-04-15 2022-10-20 Nvidia Corporation Launching code concurrently
US20240220315A1 (en) * 2022-12-30 2024-07-04 Advanced Micro Devices, Inc. Dynamic control of work scheduling

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020116357A1 (en) 1999-12-07 2002-08-22 Paulley Glenn Norman System and methodology for join enumeration in a memory-constrained environment
US20110022817A1 (en) * 2009-07-27 2011-01-27 Advanced Micro Devices, Inc. Mapping Processing Logic Having Data-Parallel Threads Across Processors
US20120291040A1 (en) * 2011-05-11 2012-11-15 Mauricio Breternitz Automatic load balancing for heterogeneous cores
US20130160016A1 (en) * 2011-12-16 2013-06-20 Advanced Micro Devices, Inc. Allocating Compute Kernels to Processors in a Heterogeneous System

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8136104B2 (en) 2006-06-20 2012-03-13 Google Inc. Systems and methods for determining compute kernels for an application in a parallel-processing computer system
US8375368B2 (en) * 2006-06-20 2013-02-12 Google Inc. Systems and methods for profiling an application running on a parallel-processing computer system
CN102023844B (zh) * 2009-09-18 2014-04-09 深圳中微电科技有限公司 并行处理器及其线程处理方法
KR101079697B1 (ko) * 2009-10-05 2011-11-03 주식회사 글로벌미디어테크 범용 그래픽 처리장치의 병렬 프로세서를 이용한 고속 영상 처리 방법
US8250404B2 (en) * 2009-12-31 2012-08-21 International Business Machines Corporation Process integrity of work items in a multiple processor system
US9092267B2 (en) * 2011-06-20 2015-07-28 Qualcomm Incorporated Memory sharing in graphics processing unit
US20120331278A1 (en) 2011-06-23 2012-12-27 Mauricio Breternitz Branch removal by data shuffling
US9823927B2 (en) * 2012-11-30 2017-11-21 Intel Corporation Range selection for data parallel programming environments
CN105027089B (zh) * 2013-03-14 2018-05-22 英特尔公司 内核功能性检查器
US9772864B2 (en) * 2013-04-16 2017-09-26 Arm Limited Methods of and apparatus for multidimensional indexing in microprocessor systems
US10297073B2 (en) * 2016-02-25 2019-05-21 Intel Corporation Method and apparatus for in-place construction of left-balanced and complete point K-D trees

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020116357A1 (en) 1999-12-07 2002-08-22 Paulley Glenn Norman System and methodology for join enumeration in a memory-constrained environment
US20110022817A1 (en) * 2009-07-27 2011-01-27 Advanced Micro Devices, Inc. Mapping Processing Logic Having Data-Parallel Threads Across Processors
US20120291040A1 (en) * 2011-05-11 2012-11-15 Mauricio Breternitz Automatic load balancing for heterogeneous cores
US20130160016A1 (en) * 2011-12-16 2013-06-20 Advanced Micro Devices, Inc. Allocating Compute Kernels to Processors in a Heterogeneous System

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US9965343B2 (en) 2018-05-08
EP3295300A1 (en) 2018-03-21
EP3295300B1 (en) 2022-03-23
EP3295300A4 (en) 2019-01-09
WO2016182636A1 (en) 2016-11-17
CN107580698A (zh) 2018-01-12
KR20180011096A (ko) 2018-01-31
CN107580698B (zh) 2019-08-23
US20160335143A1 (en) 2016-11-17
JP6659724B2 (ja) 2020-03-04
JP2018514869A (ja) 2018-06-07

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