KR102545226B1 - Memory system and data processing system including the same - Google Patents

Abstract

The data processing system includes a shared memory; a host processor configured to take ownership of the shared memory and process a first task by accessing the shared memory; a processor configured to receive and possess the ownership from the host processor and process a second task by accessing the shared memory; and a memory controller connected between the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership, wherein the memory controller stores a mailbox. and the host processor transfers or reclaims the ownership by accessing the mailbox.

Description

Memory system and data processing system including it {MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME}

The present invention relates to a data processing system, and more particularly to a data processing system including a shared memory.

The data processing system is an electronic system capable of processing data, and may include a personal computer, a laptop computer, a smart phone, a tablet computer, a digital camera, a game console, a navigation device, a virtual reality device, and a wearable device.

A data processing system may include a memory system. The memory system may be configured to store data processed by the data processing system. The memory system may operate by being embedded in the data processing system or manufactured in a detachable form and connected to the data processing system. The memory system is PCMCIA (Personal Computer Memory Card International Association) card, CF (Compact Flash) card, smart media card, memory stick, various multi-media cards (MMC, eMMC, RS-MMC, MMC-micro), SD (Secure Digital) ) card (SD, Mini-SD, Micro-SD), Universal Flash Storage (UFS) or Solid State Drive (SSD).

An embodiment of the present invention is to provide a data processing system in which a host processor and a peripheral processor can access a shared memory without colliding with each other.

A data processing system according to an embodiment of the present invention includes a shared memory; a host processor configured to take ownership of the shared memory and process a first task by accessing the shared memory; a processor configured to receive and possess the ownership from the host processor and process a second task by accessing the shared memory; and a memory controller connected between the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership, wherein the memory controller stores a mailbox. and the host processor may transfer or withdraw the ownership by accessing the mailbox.

A memory system according to an embodiment of the present invention includes a shared memory; a processor configured to receive ownership from a host processor and process a task by accessing the shared memory; and a memory controller connected between the host processor, the processor and the shared memory and configured to allow the host processor or the processor to access the shared memory according to the ownership, wherein the memory controller comprises the host processor may include a mailbox accessed to transfer the ownership to the processor.

In a data processing system according to an embodiment of the present invention, a host processor and a peripheral processor can access a shared memory without colliding with each other.

1 is a block diagram illustrating a data processing system according to an embodiment of the present invention;
2 is a diagram illustrating a situation in which a host processor or processors alternately possess ownership of a shared memory according to an embodiment of the present invention;
3 is a diagram briefly illustrating a host processor and operating procedures of the processor according to an embodiment of the present invention;
4 is a diagram for explaining the configuration of a mailbox according to an embodiment of the present invention;
5 is a block diagram showing in detail a memory controller according to an embodiment of the present invention;
6 is a diagram illustrating a method for a host processor to store work data in a shared memory according to an embodiment of the present invention;
7 is a diagram illustrating a method for a host processor to transfer ownership to a processor according to an embodiment of the present invention;
8 is a diagram illustrating a method in which a controller assigns ownership to a processor according to an embodiment of the present invention;
9 is a diagram illustrating a method for a host processor to store job information in a mailbox according to an embodiment of the present invention;
10 is a diagram illustrating a method for a processor to read job information from a mailbox according to an embodiment of the present invention;
11 is a diagram illustrating how a processor processes work data according to an embodiment of the present invention;
12 is a diagram illustrating a method for a host processor to reclaim ownership from a processor according to an embodiment of the present invention;
13 is a diagram illustrating a method for a host processor to read job result data from a shared memory according to an embodiment of the present invention;
14 is a diagram showing a method for a host processor to read job result data from a mailbox according to an embodiment of the present invention;
15 is a diagram exemplarily showing a data processing system according to an embodiment of the present invention;
16 is a diagram exemplarily showing a data processing system according to an embodiment of the present invention;
17 is a diagram exemplarily showing a data processing system according to an embodiment of the present invention;
18 is a diagram exemplarily illustrating a network system including a memory system according to an embodiment of the present invention.

Advantages and features of the present invention, and methods for achieving them, will be explained in detail through the following embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the present embodiments are provided to explain in detail enough to easily implement the technical idea of the present invention to those skilled in the art to which the present invention belongs.

In the drawings, embodiments of the present invention are not limited to the specific forms shown and are exaggerated for clarity. Although certain terms are used in this specification. This is used for the purpose of explaining the present invention, and is not used to limit the scope of the present invention described in the meaning or claims.

In this specification, the expression 'and/or' is used to mean including at least one of the elements listed before and after. In addition, the expression 'connected/coupled' is used as a meaning including being directly connected to another component or indirectly connected through another component. In this specification, the singular form also includes the plural form unless otherwise specified in the phrase. In addition, elements, steps, operations, and elements referred to as 'comprising' or 'including' used in the specification mean the presence or addition of one or more other elements, steps, operations, and elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating a data processing system 100 according to an embodiment of the present invention.

Referring to FIG. 1 , the data processing system 100 may include a host processor 110 , a processor 120 , a shared memory 130 and a memory controller 140 .

The host processor 110 may overall control the data processing system 100 . The host processor 110 may process a task by possessing ownership of the shared memory 130 and accessing the shared memory 130 . Also, the host processor 110 may transfer ownership to the processor 120 while instructing the processor 120 to process the job.

The processor 120 may process tasks instructed by the host processor 110 . The processor 120 may process a task by receiving ownership transferred from the host processor 110 and accessing the shared memory 130 while owning the ownership. That is, in the present invention, ownership may be the right for the host processor 110 and the processor 120 to exclusively access the shared memory 130 without conflicting with each other. The host processor 110 and the processor 120 may access the shared memory 130 through the memory controller 140 .

Meanwhile, the host processor 110 may check state information of the processor 120 from the memory controller 140 after transferring the ownership to the processor 120 . When the host processor 110 determines that the processor 120 has finished its work, the host processor 110 may withdraw the ownership from the processor 120 and own it again. The host processor 110 may read work result data of the processor 120 from the shared memory 130 after possessing ownership.

As described above, access to the shared memory 130 may be restricted depending on which of the host processor 110 and the processor 120 has ownership. This is possible when the memory controller 130 assigns ownership to either the host processor 110 or the processor 120 . The memory controller 130 may change a path for the shared memory 130 while assigning ownership to one of the host processor 110 and the processor 120 under the control of the host processor 110 . The host processor 110 may transmit a predetermined command to the memory controller 140 to change ownership, that is, to transfer or withdraw ownership from the processor 120 .

The host processor 110 and the processor 120 may include a central processing unit, a graphic processing unit, a microprocessor, an application processor, an accelerated processing unit, an operating system, and the like.

The shared memory 130 may be shared by the host processor 110 and the processor 120 . The shared memory 130 may be accessed through the memory controller 140 by one of the host processor 110 and the processor 120 having ownership.

The memory controller 140 may be connected between the host processor 110 , the processor 120 and the shared memory 130 . The memory controller 140 assigns ownership to either the host processor 110 or the processor 120 under the control of the host processor 110, thereby accessing the shared memory 130 of the host processor 110 or the processor 120. ) of the shared memory 130 may be allowed. When the ownership is attributed to either one of the host processor 110 and the processor 120, the memory controller 140 eventually passes the data path and command path between the host processor 110, the processor 120, and the shared memory 130. It can be implemented by selectively activating. The memory controller 140 may change ownership of ownership between the host processor 110 and the processor 120 in response to a predetermined command transmitted from the host processor 110 .

The memory controller 140 may include a mail box 145 . Host processor 110 may transfer ownership to and take back ownership from processor 120 by accessing mailbox 145 . The host processor 110 may store job information to be confirmed by the processor 120 in the mail box 145 . The host processor 110 may read state information of the processor 120 from the mailbox 145 .

Also, the processor 120 may process the job instructed by the host processor 110 by reading and checking job information from the mail box 145 .

The mail box 145 may be implemented with various memory devices such as SRAM or registers.

In summary, the memory controller 140 assigns ownership to either one of the host processor 110 and the processor 120 under the control of the host processor 110 and shares information about the shared memory 130 of only one of which has ownership. Since access is allowed, the host processor 110 and the processor 120 can process tasks using the shared memory 130 without conflict. In addition, the interface of the shared memory 130 may be applied as it is according to an existing protocol or pin arrangement.

2 is a diagram illustrating a situation in which the host processor 110 or the processor 120 alternately owns ownership of the shared memory 130 according to an embodiment of the present invention.

Referring to FIG. 2 , the host processor 110 may initially have ownership. Accordingly, during the time T1 , the host processor 110 may take ownership and access the shared memory 130 to process a task. During time T1, processor 120 cannot access shared memory 130.

At the point in time P1 , the host processor 110 may transfer ownership to the processor 120 . Accordingly, during the time T2 , the processor 120 may take ownership and access the shared memory 130 to process a task. During time T2, host processor 110 cannot access shared memory 130.

At point in time P2 , the host processor 110 may withdraw ownership from the processor 120 . Accordingly, during the time T3 , the host processor 110 may take ownership and access the shared memory 130 to process a task. During time T3, processor 120 cannot access shared memory 130.

According to an embodiment, the job of the host processor 110 processed at time T1 may include storing job data to instruct the processor 120 to process in the shared memory 130 . The work of the processor 120 processed at time T2 may include processing work data stored in the shared memory 130 according to instructions from the host processor 110 . The work of the host processor 110 processed at time T3 may include reading the work result data processed by the processor 120 from the shared memory 130 . A description of the corresponding procedure will be described in detail with reference to FIG. 3 next.

3 is a diagram briefly illustrating operating procedures of the host processor 110 and the processor 120 according to an embodiment of the present invention. When the procedure in FIG. 3 starts, ownership may be owned by the host processor 110 .

Referring to FIG. 3 , in step S11 , the host processor 110 may store work data to be processed by the processor 120 in the shared memory 130 . Since the host processor 110 has ownership, it can access the shared memory 130 . Meanwhile, the host processor 110 does not directly access the shared memory 130 , but actually accesses it through the memory controller 140 . An arrow connected from the host processor 110 to the shared memory 130 in step S11 means that the host processor 110 has ownership and uses the shared memory 130 .

In operation S12 , the host processor 110 may transmit a predetermined command to the memory controller 140 to transfer ownership to the processor 120 .

In step S13 , the memory controller 140 may assign ownership to the processor 120 in response to a command transmitted from the host processor 110 . Accordingly, the memory controller 140 may allow only the access of the processor 120 to the shared memory 130 .

In step S14 , the host processor 110 may store job information in the mail box 145 of the memory controller 140 . The task information may include information about a task to be processed by the processor 120 . For example, the work information may include a start address and an end address of an area in which work data is stored in the shared memory 130 . The job information may include a start address and an end address of an area where job result data is to be stored in the shared memory 130 .

In step S15, the processor 120 may read job information stored in the mail box 145.

In step S16 , the processor 120 may process work data stored in the shared memory 130 . The processor 120 may read and process job data from the shared memory 130 and store the processed data in the shared memory 130 as job result data. Since the processor 120 owns the ownership, it can access the shared memory 130 . Meanwhile, the processor 120 does not directly access the shared memory 130, but actually accesses it through the memory controller 140. An arrow connected from the processor 120 to the shared memory 130 in step S16 means that the processor 120 has ownership and uses the shared memory 130 .

In step S17 , the host processor 110 may repeatedly read state information of the processor 120 through the mailbox 145 of the memory controller 140 . The state information may include whether the processor 120 has finished its work. The status information may include remaining throughput of an operation being processed by the processor 120 . Step S17 may be performed in parallel with step S16. As will be discussed later, when processor 120 takes ownership, host processor 110 gains access to mailbox 145.

In operation S18 , when it is determined that the processor 120 has finished its work, the host processor 110 may transmit a predetermined command to the memory controller 140 to retrieve ownership from the processor 120 .

In step S19 , the memory controller 140 may assign ownership to the host processor 110 in response to a command transmitted from the host processor 110 . Accordingly, the memory controller 140 may allow only the host processor 110 to access the shared memory 130 .

In step S20 , the host processor 110 may read the operation result data of the processor 120 from the shared memory 130 . Since the host processor 110 has ownership, it can access the shared memory 130 . Meanwhile, the host processor 110 does not directly access the shared memory 130 , but actually accesses it through the memory controller 140 . An arrow connected from the host processor 110 to the shared memory 130 in step S11 means that the host processor 110 has ownership and uses the shared memory 130 .

4 is a diagram for explaining the configuration of a mailbox 145 according to an embodiment of the present invention. The address shown in FIG. 4 will be used as it is in the operation method described later. In addition, a method of transferring and withdrawing ownership using the mail box 145 in FIG. 4 will also be described.

Referring to FIG. 4 , an address range (ADa to ADz) used by the host processor 110 is shown. The host processor 110 may allocate a portion of the address range ADa to ADi among the address ranges ADa to ADz to the shared memory 130 . The host processor 110 may allocate a partial range (ADj to ADn) of the address range (ADa to ADz) to the mailbox 145 . A part of the address range (ADa to ADz) (ADo to ADz) may be reserved without being used.

Accordingly, the memory controller 140 determines whether the address of an access command transmitted from the host processor 110 is between the address range ADa to ADi of the shared memory 130 and the address range ADj to ADn of the mailbox 145. It is possible to determine where it is included and process the access command according to the determination result.

The mailbox 145 may include an ownership transfer area 401 , an ownership recovery area 402 , a job information area 403 , a status information area 404 , and a job result data area 405 . The ownership transfer area 401, ownership withdrawal area 402, job information area 403, status information area 404, and job result data area 405 are addresses included in the address range ADj to ADn, respectively. can respond to

The ownership transfer area 401 may be an area in which the host processor 110 read-accesses to transfer ownership to the processor 120 . The host processor 110 may transmit a read command and an address AD-TR of the area 401 to which ownership is transferred to the memory controller 140 in order to transfer ownership to the processor 120 . The memory controller 140 may assign ownership to the processor 120 by checking the read command transmitted from the host processor 110 and the address AD-TR of the region 401 before ownership. The memory controller 140 may transmit transfer confirmation data stored in the transfer-of-ownership area 401 to the host processor 110 in response to a read command for the transfer-of-ownership area 401 . The transfer confirmation data signifies that the transfer of ownership has been completed, and may be data previously agreed upon with the host processor 110 .

The ownership withdrawal area 402 may be an area in which the host processor 110 read-accesses to recover ownership from the processor 120 . The host processor 110 may transmit a read command and an address AD-RS of the ownership withdrawal area 402 to the memory controller 140 to retrieve ownership from the processor 120 . The memory controller 140 may attribute the ownership to the host processor 110 by checking the read command transmitted from the host processor 110 and the address AD-RS of the ownership recovery area 402 . The memory controller 140 may transmit redemption confirmation data stored in the ownership redemption area 402 to the host processor 110 in response to a read command for the ownership redemption area 402 . The redemption confirmation data means that the ownership redemption will be processed, and may be data promised in advance with the host processor.

The task information area 403 may be an area in which task information to be verified by the processor 120 is stored. The host processor 110 may store job information in the job information area 403 . The processor 120 may read and check job information from the job information area 403 . The work information area 403 can be accessed using an address (AD-WI).

The state information area 404 may be an area where state information of the processor 120 is stored. State information may be stored by the memory controller 140 . For example, as will be described later, the memory controller 140 can know the location where the work result data of the processor 120 is stored in the shared memory 130, and based thereon, updates the remaining throughput or state information of the operation. can do. Depending on embodiments, state information may be stored by the processor 120 . The host processor 110 can read and check status information from the status information area 404 . The status information area 404 can be accessed using an address (AD-ST).

The task result data area 405 may be an area in which task result data of a task processed by the processor 120 is stored. The processor 120 may store job result data in the job result data area 405 . The host processor 110 may read job result data from the job result data area 405 . That is, the host processor 110 may read the work result data from the shared memory 130 as described with reference to FIG. 3 or may read the work result data area 405 according to an embodiment. The job result data area 405 can be accessed using the address AD-RD.

According to an embodiment, the host processor 110 may change the ownership ownership through separately designated commands without changing ownership by accessing the mailbox 145 as described above. Separately designated commands may be for storing ownership of current ownership in a separate register (not shown) included in the memory controller 140, for example, a multi purpose register (MPR). When receiving separately designated commands from the host processor 110, the memory controller 140 may store in a separate register who the ownership belongs to and form a path to the shared memory 130 accordingly.

5 is a block diagram showing in detail the memory controller 140 according to an embodiment of the present invention.

Referring to FIG. 5 , the memory controller 140 may include a control unit 210 and an interface unit 220 .

The controller 210 may be connected to the host processor 110 through a host command path (HC). The controller 210 may be connected to the data driver 211 through the second host data path HD2 and the second memory data path MD2. The controller 210 may be connected to the command mux 212 through a processor command path (PC). The use of each pass will be detailed below. Also, the controller 210 may include a mailbox 145 . The controller 210 may control the mail box 145 .

The controller 210 may assign ownership to the processor 120 under the control of the host processor 110 . In detail, the host processor 110 may transmit the read command and the address AD-TR of the area 401 before ownership of the mailbox 145 through the host command path HC. Since the controller 210 is always connected to the host processor 110 through the host command path HC, it can receive a lead command from the host processor 110 regardless of who owns the ownership. The controller 210 may receive a read command and an address AD-TR of the region 401 before ownership through the host command path HC, and may assign ownership to the processor 120 . As will be described later, the controller 210 may assign ownership to the processor 120 by changing the data path and command path of the interface unit 220 .

After the ownership is attributed to the processor 120, the controller 210 may transmit transfer confirmation data stored in the ownership transfer area 401 to the host processor 110 as a response to the read command. Meanwhile, when the ownership belongs to the processor 120, as will be described later, since the second host data path HD2 is connected to the first host data path HD1, the controller 210 transfers the previous confirmation data to the second host data path HD1. It can be transmitted to the host processor 110 through the data path HD2 and the first host data path HD1.

Also, the controller 210 may assign ownership to the host processor 110 under the control of the host processor 110 . In detail, the host processor 110 may transmit the read command and the address AD-RS of the ownership recovery area 402 of the mailbox 145 through the host command path HC. Since the controller 210 is always connected to the host processor 110 through the host command path HC, it can receive a lead command from the host processor 110 in a state in which ownership belongs to the processor 120 . The controller 210 may receive a read command and an address (AD-RS) of the ownership recovery area 402, and may assign ownership to the host processor 110. As will be described later, the controller 210 may assign ownership to the host processor 110 by changing the data path and command path of the interface unit 220 .

Before the controller 210 attributes ownership to the host processor 110, that is, before changing the data path and the command path of the interface unit 220, the collection confirmation data stored in the ownership recovery area 402 as a response to a read command. may be transmitted to the host processor 110. Meanwhile, since the second host data path HD2 is connected to the first host data path HD1 before ownership is transferred to the host processor 110, the control unit 210 transmits recovery confirmation data to the second host data path. It can be transmitted to the host processor 110 through (HD2) and the first host data path (HD1).

Also, the controller 210 may process various accesses to the mail box 145 of the host processor 110 and the processor 120 .

First of all, the controller 210 may store job information in the job information area 403 of the mail box 145 under the control of the host processor 110 .

The controller 210 may transmit job information stored in the job information area 403 of the mail box 145 to the processor 120 under the control of the processor 120 .

The controller 210 may store state information of the processor 120 in the state information area 404 of the mailbox 145 under the control of the processor 120 . According to an embodiment, since the controller 210 directly accesses the shared memory 130 under the control of the processor 120, the remaining throughput of the processor 120 may be known, and thus the controller 210 may State information of the processor 120 may be stored in the state information area 404 regardless of the control of the processor 120 .

The controller 210 may transmit status information stored in the status information area 404 of the mailbox 145 to the host processor 110 under the control of the host processor 110 .

The controller 210 may store job result data processed by the processor 120 in the job result data area 405 of the mailbox 145 under the control of the processor 120 .

The controller 210 may transmit job result data stored in the job result data area 405 of the mail box 145 to the host processor 110 under the control of the host processor 110 .

Meanwhile, the controller 210 may interface between the processor 120 and the shared memory when ownership belongs to the processor 120 . For example, when the processor 120 is a hardware accelerator, the processor 120 does not generate a command according to the interface protocol of the shared memory 130, but the control unit 210 instead generates a command according to the instructions of the processor 120 It can be transferred to the shared memory 130. According to an embodiment, the processor 120 may generate a command according to an interface protocol of the shared memory 130, and in this case, the controller 210 transmits the command generated by the processor 120 to the shared memory 130. can In summary, when ownership is vested in the processor 120, the processor 120 may access the shared memory 130 through the controller 210. Therefore, as will be described later, when ownership is attributed to the processor 120, the controller 210 may control the interface 220 to activate a path between the controller 210 and the shared memory 130.

The control unit 210 interfaces to activate a pass between the host processor 110, the control unit 210, and the shared memory 130 according to which of the host processor 110 and the processor 120 the ownership belongs to. The unit 220 can be controlled.

Specifically, when the ownership belongs to the host processor 110, the controller 210 may control the interface unit 220 to activate a path between the host processor 110 and the shared memory 130.

When ownership is vested in the processor 120, the controller 210 deactivates the path between the host processor 110 and the shared memory 130 and activates the path between the controller 210 and the shared memory 130. It is possible to control the interface unit 220 so as to be. The processor 120 may access the shared memory 130 through the control unit 210 when possessing ownership.

Also, when the ownership belongs to the processor 120, the controller 210 may control the interface 220 to activate a path between the host processor 110 and the controller 210. Therefore, while the ownership belongs to the processor 120, the host processor 110 stores job information in the mailbox 145 of the control unit 210 and reads status information and job result data from the mailbox 145. that could be possible

The interface unit 220 may transmit data and commands by forming a path between the host processor 110 , the controller 210 and the shared memory 130 under the control of the controller 210 . Specifically, when the host processor 110 has ownership, the interface unit 220 may activate a path between the host processor 110 and the shared memory 130 under the control of the controller 210 . When the processor 120 owns the ownership, the interface unit 220 deactivates the path between the host processor 110 and the shared memory 130 under the control of the controller 210, and the controller 210 and the shared memory A path between 130 and a path between the controller 210 and the host processor 110 may be activated.

The interface unit 220 may include a data driver 211 and a command mux 212 .

The data driver 211 may be connected to the host processor 110 through the first host data path HD1. The data driver 211 may be connected to the shared memory 130 through the first memory data path MD1. The data driver 211 may be connected to the control unit 210 through a second host data path HD2 and a second memory data path MD2.

When ownership belongs to the host processor 110 , the data driver 211 may activate a data path between the host processor 110 and the shared memory 130 under the control of the control unit 210 . Specifically, the data driver 211 may activate a data path between the host processor 110 and the shared memory 130 by connecting the first host data path HD1 and the first memory data path MD1.

In addition, when ownership is vested in the processor 120, the data driver 211 deactivates the data path between the host processor 110 and the shared memory 130 under the control of the controller 210, and the host processor 110 ) and the control unit 210 may be activated, and a data path between the shared memory 130 and the control unit 210 may be activated. In detail, the data driver 211 can activate the data path between the host processor 110 and the controller 210 by connecting the first host data path HD1 and the second host data path HD2. Also, the data driver 211 can activate the data path between the shared memory 130 and the control unit 210 by connecting the first memory data path MD1 and the second memory data path MD2.

The command mux 212 may be connected to the host processor 110 through a host command path (HC). The command mux 212 may be connected to the control unit 210 through a processor command path (PC). The command mux 212 may be connected to the shared memory 130 through a memory command path (MC).

When ownership is vested in the host processor 110 , the command mux 212 may activate a command path between the host processor 110 and the shared memory 130 under the control of the controller 210 . In detail, the command mux 212 may activate a command path between the host processor 110 and the shared memory 130 by connecting the host command path HC and the memory command path MC.

In addition, when ownership is attributed to the processor 120, the command mux 212 deactivates a command path between the host processor 110 and the shared memory 130 under the control of the controller 210, and the controller 210 and a command path between the shared memory 130 may be activated. In detail, the command mux 212 may activate a command path between the controller 210 and the shared memory 130 by connecting a processor command path (PC) and a memory command path (MC).

As a result, whenever ownership is transferred and withdrawn between the host processor 110 and the processor 120, a data path and a command path may be changed between the host processor 110, the control unit 210, and the shared memory 130. there is.

6 to 13 are diagrams for explaining how the memory controller 140 interfaces among the host processor 110, the processor 120, and the shared memory 130 according to an embodiment of the present invention.

First, FIG. 6 is a diagram illustrating a method in which the host processor 110 stores work data in the shared memory 130 according to an embodiment of the present invention.

Referring to FIG. 6 , the host processor 110 may be in a state of ownership.

When the host processor 110 owns the ownership, the data driver 211 connects the first host data path HD1 and the first memory data path MD1 under the control of the control unit 210 so that the host processor 110 ) and the shared memory 130 can be activated.

When the host processor 110 owns the ownership, the command mux 212 connects the host command path (HC) and the memory command path (MC) under the control of the control unit 210 so that the host processor 110 and the shared memory You can activate the command path between (130). In FIG. 6, an active path connecting the host processor 110 and the shared memory 130 is filled in gray.

Therefore, since the host processor 110 is connected to the shared memory 130 through the interface unit 220, it can access the shared memory 130 to process a task. For example, the host processor 110 transmits a write command to the host command path (HC) and transmits the work data to the first host in order to store work data of a task to be instructed to the processor 120 in the shared memory 130. It can be transmitted through the data path HD1.

7 is a diagram illustrating a method for the host processor 110 to transfer ownership to the processor 120 according to an embodiment of the present invention.

Referring to FIG. 7 , in order to transfer ownership to the processor 120, the host processor 110 transmits a read command and an address AD-TR of an ownership transfer area 401 of the mailbox 145 to a host command path ( HC) to the control unit 210.

8 is a diagram illustrating a method in which the controller 210 assigns ownership to the processor 120 according to an embodiment of the present invention.

Referring to FIG. 8 , the controller 210 responds to the read command transmitted through the host command path (HC) and the address (AD-TR) of the transfer-of-ownership area 401 of the mailbox 145, so that the processor 120 ) can be assigned ownership. In addition, the controller 210 may control the interface unit 220 to change the data path and the command path according to the change in ownership.

Specifically, when the processor 120 owns the ownership, the data driver 211 connects the first memory data path MD1 and the second memory data path MD2 under the control of the control unit 210 to the shared memory. A data path between 130 and the control unit 210 may be activated.

Further, the data driver 211 connects the first host data path HD1 and the second host data path HD2 under the control of the control unit 210, thereby providing a data path between the host processor 110 and the control unit 210. can activate.

Also, the command mux 212 may activate a command path between the controller 210 and the shared memory 130 by connecting the processor command path (PC) and the memory command path (MC) under the control of the controller 210. there is.

As a result, in FIG. 8, the active path connecting the host processor 110 and the control unit 210 is filled in gray, and the active path connecting the shared memory 130 and the control unit 210 is filled with hatched lines. there is.

Meanwhile, since the host processor 110 and the data path are connected, the controller 210 may transmit transfer confirmation data stored in the ownership transfer area 401 to the host processor 110 in response to a lead command for ownership transfer.

9 is a diagram illustrating a method for the host processor 110 to store job information in the mail box 145 according to an embodiment of the present invention.

Referring to FIG. 9 , in order to instruct the processor 120 to work, the host processor 110 transmits the write command and the address AD-WI of the work information area 403 of the mailbox 145 to the host command path ( HC) and transmits job information to the controller 210 through the first host data path HD1 and the second host data path HD2.

The controller 210 may store job information in the job information area 403 of the mailbox 145 in response to the write command transmitted through the host command path HC. Although not shown, the controller 210 may notify the processor 120 that job information is stored in the job information area 403 .

10 is a diagram illustrating a method in which the processor 120 reads job information from the mailbox 145 according to an embodiment of the present invention.

Referring to FIG. 10 , the processor 120 may read job information stored in the job information area 403 of the mailbox 145 . The processor 120 may check the stored location of data to be processed in the shared memory 130 through the read job information.

11 is a diagram illustrating how the processor 120 processes work data according to an embodiment of the present invention.

Referring to FIG. 11 , since the processor 120 is connected to the shared memory 130 through the control unit 210 and the interface unit 220, it can process work data by accessing the shared memory 130. The processor 120 may read and process job data from the shared memory 130 and store job result data in the shared memory 130 . The processor 120 may exchange work data and work result data with the shared memory 130 through the control unit 210 and the first memory data path MD1 and the second memory data path MD2. To this end, the controller 210 may generate read commands and write commands under the control of the processor 120 and transmit them to the shared memory 130 through a processor command path (PC) and a memory command path (MC).

While the processor 120 is processing a task, the host processor 110 uses a read command and an address (AD-ST) of the status information area 404 of the mailbox 145 to check the status information of the processor 120. may be transmitted to the controller 210 through a host command path (HC).

The controller 210 may transmit status information to the host processor 110 in response to a read command for reading status information. The host processor 110 may confirm that the task of the processor 120 has been completed by checking the state information.

12 is a diagram illustrating a method in which the host processor 110 withdraws ownership from the processor 120 according to an embodiment of the present invention.

Referring to FIG. 12, the host processor 110 confirms that the task of the processor 120 has been completed by checking the status information, and then, in order to retrieve the ownership from the processor 120, the lead command and the ownership of the mailbox 145 The address AD-RS of the recovery area 402 may be transmitted to the controller 210 through the host command path HC.

The controller 210 may transmit recovery confirmation data stored in the ownership recovery area 402 to the host processor 110 in response to a read command for ownership confirmation.

13 is a diagram illustrating a method in which the host processor 110 reads job result data from the shared memory 130 according to an embodiment of the present invention.

13, the controller 210 responds to the read command transmitted through the host command path (HC) and the address (AD-RS) of the ownership recovery area 402 of the mailbox 145, the host processor ( 110) can be attributed ownership. In addition, the controller 210 may control the interface unit 220 to change the data path and the command path according to the change in ownership. As a result, the interface unit 220 can change the data path and command path as shown in FIG. 6 .

Therefore, since the host processor 110 is connected to the shared memory 130 through the interface unit 220, it can read operation result data of the processor 120 from the shared memory 130. To read job result data, the host processor 110 transmits a read command to the host command path HC and shares the job result data through the first memory data path MD1 and the first host data path HD1. It can be transmitted from the memory 130.

14 is a diagram illustrating a method in which the host processor 110 reads job result data from the mailbox 145 according to an embodiment of the present invention.

Referring to FIG. 14, unlike in FIG. 13, when the job result data is stored in the job result data area 405 of the mail box 145, the host processor 110 transfers the job result data to the mail box 145. can lead from That is, in the situation of FIG. 11, if it is confirmed that the task of the processor 120 is completed based on the status information, the host processor 110 can read the task result data from the mail box 145 without retrieving ownership. In order to read job result data, the host processor 110 sends a read command and the address AD-RD of the job result data area 405 of the mailbox 145 to the control unit 210 through a host command path (HC). can be sent to

15 is a diagram exemplarily illustrating a data processing system 1000 according to an embodiment of the present invention. Referring to FIG. 15 , the data processing system 1000 may include a host device 1100 and a memory system 1200 .

The host device 1100 may be configured in the form of a board such as a printed circuit board. The host device 1100 may include a host processor 1110 and an access terminal 1120 .

The host processor 1110 may correspond to the host processor 110 of FIG. 1 .

The connection terminal 1120 may include a socket, slot, or connector, and the memory system 1200 may be mounted on the connection terminal 1120 .

The memory system 1200 may be configured in the form of a substrate such as a printed circuit board. The memory system 1200 may be referred to as a memory module or a memory card. The memory system 2200 may include a processor 1210 , a memory device 1220 , a memory controller 1230 , and a connection terminal 1240 .

Processor 1210 may correspond to processor 120 of FIG. 1 . The memory device 1220 may correspond to the shared memory 130 of FIG. 1 . The memory controller 1230 may correspond to the memory controller 140 of FIG. 1 .

The access terminal 1240 may be connected to the access terminal 1120 of the host device 1100 . Signals such as commands, addresses, and data, and power may be transferred between the host device 1100 and the memory system 1200 through the connection terminal 1240 . The access terminal 1240 may be configured in various forms according to an interface method between the host device 1100 and the memory system 1200 . The connection terminal 1240 may be disposed on either side of the memory system 1200 .

16 is a diagram exemplarily illustrating a data processing system 2000 according to an embodiment of the present invention. Referring to FIG. 16 , a data processing system 2000 may include a host device 2100 and a memory system 2200 .

The host device 2100 may be configured in the form of a board such as a printed circuit board. The host device 2100 may include a host processor 2110 . The host processor 2110 may correspond to the host processor 110 of FIG. 1 .

The memory system 2200 may be configured in the form of a surface-mounted package. The memory system 2200 may be mounted on the host device 2100 through a solder ball 2250 .

The memory system 2200 may include a processor 2210 , a memory device 2220 and a memory controller 2230 . Processor 2210 may correspond to processor 120 of FIG. 1 . The memory device 2220 may correspond to the shared memory 130 of FIG. 1 . The memory controller 2230 may correspond to the memory controller 140 of FIG. 1 .

17 is a diagram exemplarily illustrating a data processing system 3000 according to an embodiment of the present invention. Referring to FIG. 17 , a data processing system 3000 may include a host processor 3100 , a memory system 3200 , an interposer 3300 and a semiconductor substrate 3400 .

The host processor 3100 and the memory system 3200 may be disposed on one surface of the interposer 3300 .

The interposer 3300 may electrically connect the host processor 3100 and the memory system 3200 . Signals such as commands, addresses, and data, and power may be transferred between the host processor 3100 and the memory system 3200 through the interposer 3300 . The interposer 3300 may be mounted on the semiconductor substrate 3400 .

The host processor 3100 may correspond to the host processor 110 of FIG. 1 .

The memory system 3200 may include a stacked logic semiconductor device 3210 and a memory device 3220 . The logic semiconductor device 3210 may control the operation of the memory system 3200 . The logic semiconductor device 3210 may include a processor 3211 and a memory controller 3212 . The processor 3211 may correspond to the processor 120 of FIG. 1 . The memory controller 3212 may correspond to the memory controller 140 of FIG. 1 .

The memory device 3220 may correspond to the shared memory 130 of FIG. 1 .

The memory system 3200 may include, for example, high bandwidth memory (HBM).

18 is a diagram exemplarily illustrating a network system 4000 including a data processing system 4150 according to an embodiment of the present invention. Referring to FIG. 18 , a network system 4000 may include a server system 4100 and a plurality of client systems 4410 to 4430 connected through a network 4500 .

The server system 4100 may provide data service in response to requests from the plurality of client systems 4410 to 4430 . For example, the server system 4100 may store data provided from a plurality of client systems 4410 to 4430 . As another example, the server system 4100 may provide data to a plurality of client systems 4410 to 4430.

Server system 4100 may include data processing system 4150 . The data processing system 4150 includes the data processing system 100 of FIG. 1 , the data processing system 1000 of FIG. 15 , the data processing system 2000 of FIG. 16 , and the data processing system 3000 of FIG. 17 . can

Since the person skilled in the art to which the present invention pertains may be embodied in other specific forms without changing the technical spirit or essential characteristics of the present invention, the embodiments described above are illustrative in all respects and not limiting. must be understood as The scope of the present invention is indicated by the claims to be described later rather than the detailed description above, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: data processing system
110: host processor
120: processor
130: shared memory
140: memory controller
145 Mail box

Claims (31)

shared memory;
a host processor configured to take ownership of the shared memory and process a first task by accessing the shared memory;
a processor configured to receive and possess the ownership from the host processor and process a second task by accessing the shared memory; and
A memory controller connected between the host processor, the processor and the shared memory and configured to allow access of the host processor or the processor to the shared memory according to the ownership;
The memory controller includes a mailbox,
the host processor transfers or reclaims the ownership by accessing the mailbox;
The memory controller,
a controller configured to attribute the ownership to the host processor or to the processor in response to the host processor's access to the mailbox; and
An interface unit configured to form a path between the host processor, the shared memory, and the control unit under the control of the control unit;
The control unit forms a first data path and a first command path between the shared memory and the control unit so that the ownership is attributed to the processor in response to the host processor's first access to the mailbox. and control to form a second data path between the host processor and the controller,
The control unit transfers the ownership to the host processor in response to the host processor's second access to the mailbox, so that the interface unit connects a third data path and a second command path between the host processor and the shared memory. A data processing system that controls to form. delete ◈Claim 3 was abandoned when the registration fee was paid.◈ According to claim 1,
The processor is connected to the control unit, and accesses the shared memory through the control unit when the ownership is owned. delete ◈Claim 5 was abandoned when the registration fee was paid.◈ According to claim 1,
wherein the control unit transmits previous confirmation data to the host processor through the second data path in response to the first access. delete ◈Claim 7 was abandoned when the registration fee was paid.◈ According to claim 1
wherein the control unit transmits recovery confirmation data to the host processor through the second data path in response to the second access and then attributes the ownership to the host processor. shared memory;
a host processor configured to take ownership of the shared memory and process a first task by accessing the shared memory;
a processor configured to receive and possess the ownership from the host processor and process a second task by accessing the shared memory; and
A memory controller connected between the host processor, the processor and the shared memory and configured to allow access of the host processor or the processor to the shared memory according to the ownership;
The memory controller includes a mailbox,
the host processor transfers or reclaims the ownership by accessing the mailbox;
The memory controller,
a controller configured to attribute the ownership to the host processor or to the processor in response to the host processor's access to the mailbox; and
An interface unit configured to form a path between the host processor, the shared memory, and the control unit under the control of the control unit;
The control unit forms a first data path and a first command path between the shared memory and the control unit so that the ownership is attributed to the processor in response to the host processor's first access to the mailbox. and control to form a second data path between the host processor and the controller,
After the host processor transfers the ownership to the processor, the host processor transmits job information on the second job to the control unit through the second data path;
The control unit stores the job information in the mail box under the control of the host processor. ◈Claim 9 was abandoned when the registration fee was paid.◈ According to claim 8,
The processor reads and confirms the job information from the mailbox and processes the second job. shared memory;
a host processor configured to take ownership of the shared memory and process a first task by accessing the shared memory;
a processor configured to receive and possess the ownership from the host processor and process a second task by accessing the shared memory; and
A memory controller connected between the host processor, the processor and the shared memory and configured to allow access of the host processor or the processor to the shared memory according to the ownership;
The memory controller includes a mailbox,
the host processor transfers or reclaims the ownership by accessing the mailbox;
The memory controller,
a controller configured to attribute the ownership to the host processor or to the processor in response to the host processor's access to the mailbox; and
An interface unit configured to form a path between the host processor, the shared memory, and the control unit under the control of the control unit;
The control unit forms a first data path and a first command path between the shared memory and the control unit so that the ownership is attributed to the processor in response to the host processor's first access to the mailbox. and control to form a second data path between the host processor and the controller,
The processor stores job result data of the second job in the mailbox,
wherein the host processor reads the job result data from the mailbox through the second data path. ◈Claim 11 was abandoned when the registration fee was paid.◈ According to claim 1
The host processor is simultaneously connected to the interface unit and the control unit through a host command path, and transmits an access command to the shared memory or the mailbox through the host command path. ◈Claim 12 was abandoned when the registration fee was paid.◈ According to claim 11,
the host processor allocates a first address range that does not overlap with the second address range allocated to the shared memory to the mailbox;
wherein the control unit compares an address of the access command transmitted from the host processor with the first address range and the second address range to process the access command. ◈Claim 13 was abandoned when the registration fee was paid.◈ According to claim 1,
The mailbox includes an area before ownership,
wherein the host processor transmits a read command for a region to which ownership is transferred to the memory controller in order to transfer the ownership to the processor. ◈Claim 14 was abandoned when the registration fee was paid.◈ According to claim 13
The mailbox further includes an ownership recovery area;
wherein the host processor transmits a read command for the ownership recovery area to the memory controller in order to recover the ownership from the processor. ◈Claim 15 was abandoned when the registration fee was paid.◈ According to claim 1,
The memory controller stores state information of the processor in the mailbox,
The host processor, after transferring the ownership to the processor, reads the status information from the mailbox to determine whether the processor has finished the second task, and retrieves the ownership from the processor according to the determination result. data processing system. ◈Claim 16 was abandoned when the registration fee was paid.◈ According to claim 15,
After the host processor retrieves the ownership, the data processing system reads job result data of the second job from the shared memory through the memory controller. shared memory;
a processor configured to receive ownership from a host processor and process a task by accessing the shared memory; and
A memory controller connected between the host processor, the processor and the shared memory and configured to allow access of the host processor or the processor to the shared memory according to the ownership;
the memory controller includes a mailbox accessed by the host processor to transfer the ownership to the processor;
The memory controller,
a controller configured to attribute the ownership to the host processor or to the processor in response to the host processor's access to the mailbox; and
An interface unit configured to form a path between the host processor, the shared memory, and the control unit under the control of the control unit;
The control unit forms a first data path and a first command path between the shared memory and the control unit so that the ownership is attributed to the processor in response to the host processor's first access to the mailbox. and control to form a second data path between the host processor and the controller,
The control unit transfers the ownership to the host processor in response to the host processor's second access to the mailbox, so that the interface unit connects a third data path and a second command path between the host processor and the shared memory. A data processing system that controls to form delete ◈Claim 19 was abandoned when the registration fee was paid.◈ According to claim 17,
The processor is connected to the control unit, and accesses the shared memory through the control unit when the ownership is owned. delete ◈Claim 21 was abandoned when the registration fee was paid.◈ According to claim 17,
wherein the control unit transmits previous confirmation data to the host processor through the second data path in response to the first access. delete ◈Claim 23 was abandoned when the registration fee was paid.◈ According to claim 17
wherein the control unit transmits recovery confirmation data to the host processor through the second data path in response to the second access and then attributes the ownership to the host processor. shared memory;
a processor configured to receive ownership from a host processor and process a task by accessing the shared memory; and
A memory controller connected between the host processor, the processor and the shared memory and configured to allow access of the host processor or the processor to the shared memory according to the ownership;
the memory controller includes a mailbox accessed by the host processor to transfer the ownership to the processor;
The memory controller,
a controller configured to attribute the ownership to the host processor or to the processor in response to the host processor's access to the mailbox; and
An interface unit configured to form a path between the host processor, the shared memory, and the control unit under the control of the control unit;
The control unit forms a first data path and a first command path between the shared memory and the control unit so that the ownership is attributed to the processor in response to the host processor's first access to the mailbox. and control to form a second data path between the host processor and the controller,
wherein the control unit stores job information about the job transmitted from the host processor through the second data path in the mailbox after the ownership is transferred to the processor. ◈Claim 25 was abandoned when the registration fee was paid.◈ According to claim 24,
The processor reads and confirms the job information from the mailbox and processes the job. shared memory;
a processor configured to receive ownership from a host processor and process a task by accessing the shared memory; and
A memory controller connected between the host processor, the processor and the shared memory and configured to allow access of the host processor or the processor to the shared memory according to the ownership;
the memory controller includes a mailbox accessed by the host processor to transfer the ownership to the processor;
The memory controller,
a controller configured to attribute the ownership to the host processor or to the processor in response to the host processor's access to the mailbox; and
An interface unit configured to form a path between the host processor, the shared memory, and the control unit under the control of the control unit;
The control unit forms a first data path and a first command path between the shared memory and the control unit so that the ownership is attributed to the processor in response to the host processor's first access to the mailbox. and control to form a second data path between the host processor and the controller,
wherein the processor stores the job result data of the job in the mailbox so that the host processor reads the job result data of the job through the second data path. ◈Claim 27 was abandoned when the registration fee was paid.◈ According to claim 17
wherein the interface unit and the control unit are simultaneously connected to the host processor through a host command path, and receive an access command to the shared memory or the mailbox through the host command path. ◈Claim 28 was abandoned when the registration fee was paid.◈ The method of claim 27,
The mailbox is assigned a first address range that does not overlap with a second address range allocated to the shared memory from the host processor;
wherein the control unit compares an address of the access command transmitted from the host processor with the first address range and the second address range to process the access command. ◈Claim 29 was abandoned when the registration fee was paid.◈ According to claim 17,
The mailbox includes an area before ownership,
When the memory controller receives a read command for the region before ownership from the host processor, assigns the ownership to the processor. ◈Claim 30 was abandoned when the setup registration fee was paid.◈ According to claim 29
The mailbox further includes an ownership recovery area;
The memory controller, when receiving a read command for the ownership recovery area from the host processor, assigns the ownership to the host processor. ◈Claim 31 was abandoned when the registration fee was paid.◈ According to claim 17,
The memory controller stores state information of the processor in the mailbox so that the host processor can read.

Images