KR20190110306A - Memory system and data processing system including the same - Google Patents

Abstract

The present invention relates to a memory system and a data processing system including the same to enable host and peripheral processors to access a shared memory without a collision. According to the present invention, the data processing system comprises: the shared memory; the host processor possessing an ownership for the shared memory and accessing the shared memory to process a first task; a processor possessing the ownership transferred from the host processor and accessing the shared memory to process a second task; and a memory controller connected among the host processor, the processor and the shared memory, and allowing access to the shared memory, the host processor or the processor in accordance with the ownership. The memory controller includes a mailbox and the host processor accesses the mailbox to transfer or collect the ownership.

Description

MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME}

The present invention relates to a data processing system, and more particularly to a data processing system comprising a shared memory.

The data processing system is an electronic system capable of processing data, and may include a personal computer, a laptop computer, a smartphone, a tablet computer, a digital camera, a game console, a navigation device, a virtual reality device, a wearable device, and the like.

The data processing system can include a memory system. The memory system may be configured to store data processed in the data processing system. The memory system may be operated by being embedded in a data processing system or by being manufactured in a detachable form and connected to the data processing system. Memory systems include Personal Computer Memory Card International Association (PCMCIA) cards, Compact Flash (CF) cards, smart media cards, memory sticks, various multimedia cards (MMC, eMMC, RS-MMC, MMC-micro), and Secure Digital (SD). ) Card (SD, Mini-SD, Micro-SD), UFS (Universal Flash Storage) or SSD (Solid State Drive).

An embodiment of the present invention is to provide a data processing system capable of accessing a shared memory without conflict between the host processor and the peripheral processor.

A data processing system according to an embodiment of the present invention includes a shared memory; A host processor configured to process a first task by owning ownership of the shared memory and accessing the shared memory; A processor configured to receive and own the ownership from the host processor and to process a second job by accessing the shared memory; And a memory controller coupled between the host processor, the processor and the shared memory, the memory controller configured to allow access to the shared memory of the host processor or the processor in accordance with the ownership. And the host processor can transfer or reclaim the ownership by accessing the mailbox.

Memory system according to an embodiment of the present invention is a shared memory; A processor configured to receive ownership from a host processor and process the job by accessing the shared memory; And a memory controller coupled between the host processor, the processor and the shared memory, the memory controller configured to allow access to the shared memory of the host processor or the processor in accordance with ownership; May include a mailbox that is accessed to transfer the ownership to the processor.

The data processing system according to an exemplary embodiment of the present invention may access a shared memory without colliding with the host processor and the peripheral processor.

1 is a block diagram showing a data processing system according to an embodiment of the present invention;
2 is a diagram illustrating a situation in which a host processor or a processor alternately owns ownership of a shared memory according to an embodiment of the present invention;
3 is a diagram schematically illustrating an operating procedure of a host processor and a processor according to an embodiment of the present disclosure;
4 is a view for explaining the configuration of a mailbox according to an embodiment of the present invention;
5 is a block diagram illustrating in detail a memory controller in accordance with an embodiment of the present invention;
6 is a diagram illustrating a method for storing work data in a shared memory by a host processor according to an embodiment of the present invention;
7 is a diagram illustrating a method for transferring ownership to a processor by a host processor according to an embodiment of the present invention;
8 is a diagram illustrating a method in which a control unit assigns ownership to a processor according to an embodiment of the present invention;
9 is a diagram for a method of storing, by a host processor, job information in a mailbox according to an embodiment of the present invention;
10 is a diagram illustrating a method in which a processor reads job information from a mailbox according to an embodiment of the present invention;
11 is a diagram illustrating a method of processing job data by a processor according to an embodiment of the present invention;
12 is a diagram illustrating a method in which a host processor reclaims ownership from a processor according to an embodiment of the present invention;
FIG. 13 is a diagram illustrating a method in which a host processor reads operation result data from a shared memory according to an embodiment of the present disclosure; FIG.
14 is a diagram illustrating a method in which a host processor reads job result data from a mailbox according to an embodiment of the present invention;
15 is a diagram illustrating a data processing system in accordance with an embodiment of the present invention.
16 is a diagram illustrating a data processing system in accordance with an embodiment of the present invention.
17 is a diagram illustrating a data processing system in accordance with an embodiment of the present invention.
FIG. 18 is a diagram illustrating a network system including a memory system according to an embodiment of the present disclosure.

Advantages and features of the present invention, and methods for achieving the same will be described with reference to embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. However, the present embodiments are provided to explain in detail enough to easily implement the technical idea of the present invention to those skilled in the art.

In the drawings, the embodiments of the present invention are not limited to the specific forms shown, but are exaggerated for clarity. Although specific terms are used herein. It is used for the purpose of illustrating the present invention and is not intended to limit the scope of the present invention as defined in the meaning limitations or claims.

The expression 'and / or' is used herein to mean at least one of the components listed before and after. In addition, the expression 'connected / combined' is used in the sense of including directly connected to or indirectly connected to other components. In this specification, the singular forms also include the plural unless specifically stated otherwise in the phrases. Also, as used herein, components, steps, operations, and elements referred to as 'comprising' or 'comprising' refer to the presence or addition of one or more other components, steps, operations, and elements.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating a data processing system 100 according to an embodiment of the present invention.

Referring to FIG. 1, the data processing system 100 may include a host processor 110, a processor 120, a shared memory 130, and a memory controller 140.

The host processor 110 may control the data processing system 100 as a whole. The host processor 110 may own the ownership of the shared memory 130 and process work by accessing the shared memory 130. In addition, the host processor 110 may transfer ownership to the processor 120 while instructing the processor 120 to process a job.

The processor 120 may process a task indicated by the host processor 110. The processor 120 may transfer the ownership from the host processor 110 to process the job by owning the ownership and accessing the shared memory 130. That is, in the present invention, ownership may be a right for the host processor 110 and the processor 120 to exclusively access the shared memory 130 without conflict with each other. The host processor 110 and the processor 120 may access the shared memory 130 through the memory controller 140.

The host processor 110 may transfer ownership to the processor 120 and then check the state information of the processor 120 from the memory controller 140. When it is determined that the processor 120 has finished the work, the host processor 110 may recover ownership from the processor 120 and own it again. The host processor 110 may own the ownership and read the operation result data of the processor 120 from the shared memory 130.

As described above, access to the shared memory 130 may be limited depending on who owns ownership of the host processor 110 and the processor 120. This is possible by the memory controller 130 attributing ownership to either the host processor 110 or the processor 120. The memory controller 130 may change the path to the shared memory 130 while attributing ownership to either the host processor 110 or the processor 120 under the control of the host processor 110. The host processor 110 may transmit a predetermined command to the memory controller 140 to change the ownership of the ownership, that is, transfer the ownership to the processor 120 or withdraw the ownership from the processor 120.

The host processor 110 and the processor 120 may include a central processing unit, a graphics processing unit, a microprocessor, an application processor, an accelerated processing unit, an operating system, and the like.

The shared memory 130 may be shared by the host processor 110 and the processor 120. The shared memory 130 may be accessed through the memory controller 140 by one of ownership of the host processor 110 and the processor 120.

The memory controller 140 may be connected between the host processor 110, the processor 120, and the shared memory 130. The memory controller 140 assigns ownership to either the host processor 110 or the processor 120 under the control of the host processor 110, thereby accessing the shared memory 130 of the host processor 110 or the processor 120. ) May allow access to the shared memory 130. Attributing ownership to either the host processor 110 or the processor 120 eventually results in the memory controller 140 having a data path and command path between the host processor 110, the processor 120, and the shared memory 130. It can be implemented by selectively activating. The memory controller 140 may change the ownership of ownership between the host processor 110 and the processor 120 in response to a predetermined command transmitted from the host processor 110.

The memory controller 140 may include a mail box 145. The host processor 110 can transfer ownership to and retrieve ownership from the processor 120 by accessing the mailbox 145. The host processor 110 may store job information to be checked by the processor 120 in the mailbox 145. The host processor 110 may read state information of the processor 120 from the mailbox 145.

In addition, the processor 120 may process a job instructed by the host processor 110 by reading and confirming job information from the mailbox 145.

The mail box 145 may be implemented with various memory elements such as SRAM or registers.

In summary, the memory controller 140 assigns ownership to one of the host processor 110 and the processor 120 according to the control of the host processor 110, and controls the ownership of the shared memory 130 having only one ownership. Because of allowing access, the host processor 110 and the processor 120 can process the task using the shared memory 130 without conflict. In addition, the interface of the shared memory 130 may be applied as it is according to the existing protocol or pin arrangement.

2 is a diagram illustrating a situation in which the host processor 110 or the processor 120 alternately owns ownership of the shared memory 130 according to an embodiment of the present invention.

Referring to FIG. 2, the host processor 110 may initially own ownership. Thus, during time T1, host processor 110 may own ownership and access shared memory 130 to process the job. During time T1, processor 120 may not access shared memory 130.

At the point in time P1, the host processor 110 may transfer ownership to the processor 120. Thus, during time T2, processor 120 may own ownership and access shared memory 130 to process work. During time T2, the host processor 110 may not be able to access the shared memory 130.

At the point in time P2, the host processor 110 may take ownership from the processor 120. Thus, during time T3, host processor 110 may own ownership and access shared memory 130 to process the job. During time T3, processor 120 may not access shared memory 130.

According to an embodiment, the operation of the host processor 110 processed at the time T1 may include storing, in the shared memory 130, job data to instruct the processor 120 to process. The task of the processor 120 processed at time T2 may include processing the task data stored in the shared memory 130 according to the instruction of the host processor 110. The operation of the host processor 110 processed at time T3 may include reading the operation result data processed by the processor 120 from the shared memory 130. The description of the procedure will then be described in detail with reference to FIG.

3 is a diagram schematically illustrating an operation procedure of the host processor 110 and the processor 120 according to an exemplary embodiment of the present invention. Ownership may be in a state owned by the host processor 110 when the procedure begins in FIG.

Referring to FIG. 3, in step S11, the host processor 110 may store work data to be processed by the processor 120 in the shared memory 130. Since the host processor 110 owns ownership, the host processor 110 can access the shared memory 130. The host processor 110, on the other hand, does not access the shared memory 130 directly, but rather may access it through the memory controller 140. An arrow connected from the host processor 110 to the shared memory 130 in step S11 means that the host processor 110 uses the shared memory 130 with ownership.

In operation S12, the host processor 110 may transmit a predetermined command to the memory controller 140 to transfer ownership to the processor 120.

In operation S13, the memory controller 140 may assign ownership to the processor 120 in response to a command transmitted from the host processor 110. Thus, the memory controller 140 may then only allow access of the processor 120 to the shared memory 130.

In operation S14, the host processor 110 may store job information in the mailbox 145 of the memory controller 140. The job information may include information about a job to be processed by the processor 120. For example, the job information may include a start address and a last address of an area in which job data is stored in the shared memory 130. The job information may include a start address and a last address of an area in which the job result data is to be stored in the shared memory 130.

In operation S15, the processor 120 may read job information stored in the mailbox 145.

In operation S16, the processor 120 may process work data stored in the shared memory 130. The processor 120 may read and process work data from the shared memory 130, and store the processed data in the shared memory 130 as work result data. The processor 120 owns ownership and can access the shared memory 130. In the meantime, the processor 120 does not directly access the shared memory 130, but may substantially access it through the memory controller 140. An arrow connected from the processor 120 to the shared memory 130 in step S16 means that the processor 120 has ownership and uses the shared memory 130.

In operation S17, the host processor 110 may repeatedly read the state information of the processor 120 through the mailbox 145 of the memory controller 140. The status information may include whether the processor 120 has finished the task. The state information may include the remaining throughput of the operation being processed by the processor 120. Step S17 may be performed in parallel with step S16. As will be described below, when the processor 120 owns ownership, the host processor 110 becomes able to access the mailbox 145.

In operation S18, when it is determined that the processor 120 has finished the operation, the host processor 110 may transmit a predetermined command to the memory controller 140 to recover ownership from the processor 120.

In operation S19, the memory controller 140 may assign ownership to the host processor 110 in response to a command transmitted from the host processor 110. Thus, the memory controller 140 can then only allow access of the host processor 110 to the shared memory 130.

In operation S20, the host processor 110 may read the operation result data of the processor 120 from the shared memory 130. Since the host processor 110 owns ownership, the host processor 110 can access the shared memory 130. The host processor 110, on the other hand, does not access the shared memory 130 directly, but rather may access it through the memory controller 140. An arrow connected from the host processor 110 to the shared memory 130 in step S11 means that the host processor 110 uses the shared memory 130 with ownership.

4 is a view for explaining the configuration of a mail box 145 according to an embodiment of the present invention. The address shown in Fig. 4 will be used as it is in the operation method described later. In addition, a method of transferring and retrieving ownership using the mailbox 145 in FIG. 4 will also be described.

Referring to FIG. 4, the address ranges ADa to ADz used by the host processor 110 are illustrated. The host processor 110 may allocate some ranges ADa to ADi of the address ranges ADa to ADz to the shared memory 130. The host processor 110 may assign a partial range ADj to ADn of the address ranges ADa to ADz to the mailbox 145. Some ranges ADo to ADz of the address ranges ADa to ADz may be reserved without being used.

Therefore, the memory controller 140 has an address of an access command transmitted from the host processor 110 in the address range ADa to ADi of the shared memory 130 and the address range ADj to ADn of the mailbox 145. It is determined where it is included, and the access command can be processed according to the determination result.

The mailbox 145 may include an ownership ownership area 401, an ownership recovery area 402, a job information area 403, a status information area 404, and a job result data area 405. The ownership ownership area 401, ownership recovery area 402, job information area 403, status information area 404, and job result data area 405 are the addresses included in the address range ADj to ADn, respectively. It can correspond to.

The ownership transfer area 401 may be an area where the host processor 110 leads access to transfer ownership to the processor 120. The host processor 110 may transmit a read command and an address AD-TR of the ownership transfer region 401 to the memory controller 140 to transfer ownership to the processor 120. The memory controller 140 may check ownership of the read command transmitted from the host processor 110 and the address AD-TR of the region before the ownership 401 and assign the ownership to the processor 120. The memory controller 140 may transmit the previous confirmation data stored in the ownership previous area 401 to the host processor 110 in response to the read command for the previous ownership area 401. The transfer confirmation data indicates that ownership transfer has been completed and may be data previously promised with the host processor 110.

The ownership retrieval area 402 may be an area where the host processor 110 reads access to reclaim ownership from the processor 120. The host processor 110 may transmit the read command and the address AD-RS of the ownership recovery area 402 to the memory controller 140 to recover ownership from the processor 120. The memory controller 140 may check ownership of the read command transmitted from the host processor 110 and the address AD-RS of the ownership retrieval area 402, and assign ownership to the host processor 110. The memory controller 140 may transmit the collection confirmation data stored in the ownership recovery area 402 to the host processor 110 in response to the read command for the ownership recovery area 402. The revocation confirmation data means that the ownership retrieval will be processed and may be data previously agreed with the host processor.

The job information area 403 may be an area in which job information to be checked by the processor 120 is stored. The host processor 110 may store job information in the job information area 403. The processor 120 reads and confirms job information from the job information area 403. The job information area 403 can be accessed using the address AD-WI.

The state information area 404 may be an area where state information of the processor 120 is stored. The state information may be stored by the memory controller 140. For example, as will be described later, the memory controller 140 may know a location where the work result data of the processor 120 is stored in the shared memory 130, and accordingly, update the remaining throughput or state information of the operation. can do. According to an embodiment, the state information may be stored by the processor 120. The host processor 110 may read and check state information from the state information area 404. The status information area 404 can be accessed using the address AD-ST.

The job result data area 405 may be an area in which job result data of a job processed by the processor 120 is stored. The processor 120 may store the operation result data in the operation result data area 405. The host processor 110 may read the operation result data from the operation result data area 405. That is, the host processor 110 may read the operation result data from the shared memory 130 as described with reference to FIG. 3, or may read from the operation result data area 405 according to an embodiment. The job result data area 405 can be accessed using the address AD-RD.

According to an embodiment of the present disclosure, the host processor 110 may change ownership ownership by accessing the mailbox 145 as described above, but through separate designated commands. Separately designated commands may be for storing attribution of the current ownership in a separate register (eg, multi purpose register) included in the memory controller 140. When the memory controller 140 receives the separately designated commands from the host processor 110, the memory controller 140 may store who owns the ownership in a separate register, thereby forming a path to the shared memory 130.

FIG. 5 is a detailed block diagram illustrating a memory controller 140 according to an exemplary embodiment of the inventive concept.

Referring to FIG. 5, the memory controller 140 may include a controller 210 and an interface unit 220.

The controller 210 may be connected to the host processor 110 through a host command path HC. The controller 210 may be connected to the data driver 211 through the second host data path HD2 and the second memory data path MD2. The controller 210 may be connected to the command mux 212 through a processor command path PC. The use of each pass will be described in detail below. In addition, the controller 210 may include a mailbox 145. The controller 210 may control the mailbox 145.

The controller 210 may assign ownership to the processor 120 under the control of the host processor 110. In detail, the host processor 110 may transmit the read command and the address AD-TR of the previous ownership area 401 of the mailbox 145 through the host command path HC. Since the controller 210 is always connected to the host processor 110 through the host command path HC, the controller 210 may receive a read command of the host processor 110 regardless of who owns the ownership. The controller 210 may receive the read command and the address AD-TR of the previous ownership area 401 through the host command path HC, and assign the ownership to the processor 120. The controller 210 may assign ownership to the processor 120 by changing the data path and the command path of the interface unit 220, as will be described later.

The controller 210 may assign ownership to the processor 120, and then transmit the previous confirmation data stored in the previous ownership area 401 to the host processor 110 in response to the read command. Meanwhile, when ownership is attributed to the processor 120, the second host data path HD2 is connected to the first host data path HD1 as will be described later, so that the controller 210 may transfer the previous confirmation data to the second host. The data path HD2 and the first host data path HD1 may be transmitted to the host processor 110.

In addition, the controller 210 may assign ownership to the host processor 110 under the control of the host processor 110. In detail, the host processor 110 may transmit the read command and the address AD-RS of the ownership recovery area 402 of the mailbox 145 through the host command path HC. Since the controller 210 is always connected to the host processor 110 through the host command path HC, the controller 210 may receive a read command of the host processor 110 while the ownership is attributed to the processor 120. The controller 210 may receive the read command and the address AD-RS of the ownership recovery area 402, and assign ownership to the host processor 110. The controller 210 may assign ownership to the host processor 110 by changing a data path and a command path of the interface unit 220, as will be described later.

The control unit 210 stores the number of confirmation data stored in the ownership collection area 402 as a response to the read command before assigning the ownership to the host processor 110, that is, before changing the data path and the command path of the interface unit 220. To the host processor 110. On the other hand, before the ownership is attributed to the host processor 110, since the second host data path HD2 is connected to the first host data path HD1, the control unit 210 returns the recovery confirmation data to the second host data path. The data may be transmitted to the host processor 110 through the HD2 and the first host data path HD1.

In addition, the controller 210 may process various accesses of the host processor 110 and the processor 120 to the mailbox 145.

First, the controller 210 may store job information in the job information area 403 of the mailbox 145 under the control of the host processor 110.

The controller 210 may transmit the job information stored in the job information area 403 of the mailbox 145 to the processor 120 under the control of the processor 120.

The controller 210 may store state information of the processor 120 in the state information area 404 of the mailbox 145 under the control of the processor 120. According to an embodiment, since the controller 210 directly accesses the shared memory 130 under the control of the processor 120, the controller 210 may know the remaining throughput of the task of the processor 120, and therefore, the controller 210 may The state information of the processor 120 may be stored in the state information area 404 regardless of the control of the processor 120.

The controller 210 may transmit the state information stored in the state information area 404 of the mailbox 145 to the host processor 110 under the control of the host processor 110.

The controller 210 may store the job result data processed by the processor 120 in the job result data area 405 of the mailbox 145 under the control of the processor 120.

The controller 210 may transmit the job result data stored in the job result data area 405 of the mailbox 145 to the host processor 110 under the control of the host processor 110.

Meanwhile, the controller 210 may interface between the processor 120 and the shared memory when ownership is attributed to the processor 120. For example, when the processor 120 is a hardware accelerator, the controller 210 does not generate a command according to the interface protocol of the shared memory 130, but instead generates the command according to the instruction of the processor 120. The shared memory 130 may be transferred. According to an embodiment, the processor 120 may generate a command according to the interface protocol of the shared memory 130, and in this case, the controller 210 may transfer the command generated by the processor 120 to the shared memory 130. Can be. In summary, when ownership is attributed to the processor 120, the processor 120 may access the shared memory 130 through the controller 210. Accordingly, when ownership is attributed to the processor 120 as described below, the controller 210 may control the interface unit 220 to activate a path between the controller 210 and the shared memory 130.

The controller 210 interfaces to activate a path between the host processor 110, the controller 210, and the shared memory 130, depending on which ownership belongs to the host processor 110 or the processor 120. The unit 220 may be controlled.

In detail, when ownership is attributed to the host processor 110, the controller 210 may control the interface unit 220 to activate a path between the host processor 110 and the shared memory 130.

When ownership is attributed to the processor 120, the controller 210 deactivates a path between the host processor 110 and the shared memory 130, and activates a path between the controller 210 and the shared memory 130. The interface unit 220 may be controlled so that When the processor 120 owns the ownership, the processor 120 may access the shared memory 130 through the controller 210.

In addition, when ownership is attributed to the processor 120, the controller 210 may control the interface unit 220 to activate a path between the host processor 110 and the controller 210. Accordingly, while ownership is attributed to the processor 120, the host processor 110 stores the job information in the mailbox 145 of the controller 210 and reads the status information and the job result data from the mailbox 145. It may be possible.

The interface unit 220 may form a path between the host processor 110, the controller 210, and the shared memory 130 under the control of the controller 210 to transmit data and commands. In detail, when the host processor 110 owns the ownership, the interface unit 220 may activate a path between the host processor 110 and the shared memory 130 under the control of the controller 210. When the processor 120 owns the ownership, the interface unit 220 deactivates a path between the host processor 110 and the shared memory 130 under the control of the controller 210, and controls the controller 210 and the shared memory. The path between 130 may be activated and the path between the controller 210 and the host processor 110 may be activated.

The interface unit 220 may include a data driver 211 and a command mux 212.

The data driver 211 may be connected to the host processor 110 through the first host data path HD1. The data driver 211 may be connected to the shared memory 130 through the first memory data path MD1. The data driver 211 may be connected to the controller 210 through the second host data path HD2 and the second memory data path MD2.

When ownership is attributed to the host processor 110, the data driver 211 may activate a data path between the host processor 110 and the shared memory 130 under the control of the controller 210. In detail, the data driver 211 may activate the data path between the host processor 110 and the shared memory 130 by connecting the first host data path HD1 and the first memory data path MD1.

In addition, when ownership is attributed to the processor 120, the data driver 211 deactivates the data path between the host processor 110 and the shared memory 130 under the control of the controller 210, and the host processor 110. ) And a data path between the controller 210 and the controller 210, and a data path between the shared memory 130 and the controller 210. In detail, the data driver 211 may activate the data path between the host processor 110 and the controller 210 by connecting the first host data path HD1 and the second host data path HD2. The data driver 211 may activate the data path between the shared memory 130 and the controller 210 by connecting the first memory data path MD1 and the second memory data path MD2.

The command mux 212 may be connected to the host processor 110 through a host command path HC. The command mux 212 may be connected to the controller 210 through a processor command path PC. The command mux 212 may be connected to the shared memory 130 through the memory command path MC.

When ownership is attributed to the host processor 110, the command mux 212 may activate a command path between the host processor 110 and the shared memory 130 under the control of the controller 210. In detail, the command mux 212 may activate the command path between the host processor 110 and the shared memory 130 by connecting the host command path HC and the memory command path MC.

In addition, when ownership is attributed to the processor 120, the command mux 212 deactivates a command path between the host processor 110 and the shared memory 130 under the control of the controller 210, and the controller 210. And a command path between the shared memory 130 and the shared memory 130. In detail, the command mux 212 may activate a command path between the controller 210 and the shared memory 130 by connecting the processor command path PC and the memory command path MC.

As a result, whenever the ownership is transferred and recovered between the host processor 110 and the processor 120, the data path and the command path may be changed between the host processor 110, the controller 210, and the shared memory 130. have.

6 to 13 are diagrams for describing a method in which the memory controller 140 interfaces between the host processor 110, the processor 120, and the shared memory 130 according to an embodiment of the present invention.

6 is a diagram illustrating a method in which the host processor 110 stores working data in the shared memory 130 according to an embodiment of the present invention.

Referring to FIG. 6, the host processor 110 may have ownership.

When the host processor 110 owns the ownership, the data driver 211 connects the first host data path HD1 and the first memory data path MD1 under the control of the controller 210 to control the host processor 110. ) And the shared memory 130 may be activated.

When the host processor 110 owns the ownership, the command mux 212 connects the host command path HC and the memory command path MC under the control of the controller 210 to share the memory with the host processor 110. Command paths between 130 may be activated. In FIG. 6, an active path connecting between the host processor 110 and the shared memory 130 is filled in gray.

Therefore, since the host processor 110 is connected to the shared memory 130 through the interface unit 220, the host processor 110 may access the shared memory 130 to process a job. For example, the host processor 110 transmits a write command to the host command path HC and transmits the job data to the first host to store the job data of the job to be instructed by the processor 120 in the shared memory 130. The data path HD1 can be transmitted.

7 is a diagram illustrating a method for transferring ownership to the processor 120 by the host processor 110 according to an exemplary embodiment of the present invention.

Referring to FIG. 7, the host processor 110 transfers the read command and the address AD-TR of the ownership transfer area 401 of the mailbox 145 to the host 120 in order to transfer ownership to the processor 120. HC) may be transmitted to the controller 210.

8 is a diagram illustrating a method in which the controller 210 assigns ownership to the processor 120 according to an embodiment of the present invention.

Referring to FIG. 8, the controller 210 responds to the read command transmitted through the host command path HC and the address AD-TR of the previous ownership area 401 of the mailbox 145. Ownership can be attributed to). The controller 210 may control the interface unit 220 to change the data path and the command path according to the change of ownership.

Specifically, when the processor 120 owns the ownership, the data driver 211 connects the first memory data path MD1 and the second memory data path MD2 under the control of the controller 210 to share the memory. The data path between the 130 and the controller 210 may be activated.

The data driver 211 connects the first host data path HD1 and the second host data path HD2 under the control of the control unit 210 to control the data path between the host processor 110 and the control unit 210. Can be activated.

The command mux 212 may activate the command path between the controller 210 and the shared memory 130 by connecting the processor command path PC and the memory command path MC under the control of the controller 210. have.

As a result, in FIG. 8, the active path between the host processor 110 and the controller 210 is filled in gray, and the active path between the shared memory 130 and the controller 210 is filled with hatched lines. have.

Meanwhile, since the data path is connected to the host processor 110, the controller 210 may transmit the previous confirmation data stored in the ownership ownership area 401 to the host processor 110 in response to a read command for ownership transfer.

9 is a diagram illustrating a method of storing, by the host processor 110, job information in a mailbox 145 according to an embodiment of the present invention.

Referring to FIG. 9, the host processor 110 sends a write command and an address AD-WI in the job information area 403 of the mailbox 145 to instruct a job to the processor 120. The control unit 210 may transmit the information to the control unit 210 through the HC, and transmit the job information to the control unit 210 through the first host data path HD1 and the second host data path HD2.

The controller 210 may store job information in the job information area 403 of the mailbox 145 in response to the write command transmitted through the host command path HC. Although not shown, the controller 210 may inform the processor 120 that job information is stored in the job information area 403.

10 is a diagram illustrating a method in which the processor 120 reads job information from the mailbox 145 according to an embodiment of the present invention.

Referring to FIG. 10, the processor 120 may read job information stored in the job information area 403 of the mailbox 145. The processor 120 may identify a location where data to be processed in the shared memory 130 is stored through read job information.

11 is a diagram illustrating a method in which the processor 120 processes job data according to an exemplary embodiment of the present invention.

Referring to FIG. 11, since the processor 120 is connected to the shared memory 130 through the controller 210 and the interface unit 220, the processor 120 may access the shared memory 130 to process work data. The processor 120 may read and process work data from the shared memory 130 and store the work result data in the shared memory 130. The processor 120 may exchange work data and work result data with the shared memory 130 through the controller 210, the first memory data path MD1, and the second memory data path MD2. To this end, the controller 210 may generate a read command and a write command under the control of the processor 120 and transmit the read command and the write command to the shared memory 130 through the processor command path PC and the memory command path MC.

While the processor 120 is processing the job, the host processor 110 checks the status information of the processor 120, and reads the address (AD-ST) of the status information area 404 of the mailbox 145. May be transmitted to the controller 210 through the host command path HC.

The controller 210 may transmit the status information to the host processor 110 in response to a read command for reading the status information. The host processor 110 may check the state information to confirm that the operation of the processor 120 is completed.

12 is a diagram illustrating a method in which the host processor 110 recovers ownership from the processor 120 according to an embodiment of the present invention.

Referring to FIG. 12, the host processor 110 checks the status information to confirm that the work of the processor 120 is completed, and then, in order to recover the ownership from the processor 120, the ownership of the read command and the mail box 145. The address AD-RS of the recovery area 402 may be transmitted to the controller 210 through the host command path HC.

The controller 210 may transmit the collection confirmation data stored in the ownership collection area 402 to the host processor 110 in response to the read command for confirming the ownership.

FIG. 13 is a diagram illustrating a method in which the host processor 110 reads operation result data from the shared memory 130 according to an embodiment of the present disclosure.

Referring to FIG. 13, the controller 210 responds to a read command transmitted through the host command path HC and an address AD-RS of the ownership recovery area 402 of the mailbox 145. Ownership can be attributed to 110). The controller 210 may control the interface unit 220 to change the data path and the command path according to the change of ownership. As a result, the interface unit 220 may change the data path and the command path as shown in FIG. 6.

Therefore, since the host processor 110 is connected to the shared memory 130 through the interface unit 220, the host processor 110 may read the operation result data of the processor 120 from the shared memory 130. The host processor 110 transmits a read command to the host command path HC and shares the operation result data through the first memory data path MD1 and the first host data path HD1 to read the operation result data. The memory 130 may be transmitted.

14 is a diagram illustrating a method in which the host processor 110 reads job result data from the mailbox 145 according to an embodiment of the present invention.

Referring to FIG. 14, unlike the description of FIG. 13, when the job result data is stored in the job result data area 405 of the mailbox 145, the host processor 110 sends the job result data to the mailbox 145. Can be read from That is, in the situation of FIG. 11, if it is confirmed that the operation of the processor 120 is completed based on the state information, the host processor 110 may read the operation result data from the mailbox 145 without recovering ownership. The host processor 110 controls the read command and the address AD-RD of the work result data area 405 of the mailbox 145 through the host command path HC to read the work result data. Can be sent to.

15 is a diagram illustrating a data processing system 1000 according to an embodiment of the present invention. Referring to FIG. 15, the data processing system 1000 may include a host device 1100 and a memory system 1200.

The host device 1100 may be configured in the form of a board such as a printed circuit board. The host device 1100 may include a host processor 1110 and an access terminal 1120.

The host processor 1110 may correspond to the host processor 110 of FIG. 1.

The connection terminal 1120 may include a socket, a slot, or a connector, and the memory system 1200 may be mounted to the connection terminal 1120.

The memory system 1200 may be configured in the form of a substrate such as a printed circuit board. The memory system 1200 may be called a memory module or a memory card. The memory system 2200 may include a processor 1210, a memory device 1220, a memory controller 1230, and a connection terminal 1240.

The processor 1210 may correspond to the processor 120 of FIG. 1. The memory device 1220 may correspond to the shared memory 130 of FIG. 1. The memory controller 1230 may correspond to the memory controller 140 of FIG. 1.

The connection terminal 1240 may be connected to the connection terminal 1120 of the host device 1100. Signals such as commands, addresses, data, and the like may be transferred between the host device 1100 and the memory system 1200 through the access terminal 1240. The access terminal 1240 may be configured in various forms according to the interface method between the host device 1100 and the memory system 1200. The connection terminal 1240 may be disposed on one side of the memory system 1200.

16 is a diagram illustrating a data processing system 2000 according to an embodiment of the present invention. Referring to FIG. 16, the data processing system 2000 may include a host device 2100 and a memory system 2200.

The host device 2100 may be configured in the form of a board such as a printed circuit board. The host device 2100 may include a host processor 2110. The host processor 2110 may correspond to the host processor 110 of FIG. 1.

The memory system 2200 may be configured in the form of a surface mount package. The memory system 2200 may be mounted to the host device 2100 through solder balls 2250.

The memory system 2200 may include a processor 2210, a memory device 2220, and a memory controller 2230. The processor 2210 may correspond to the processor 120 of FIG. 1. The memory device 2220 may correspond to the shared memory 130 of FIG. 1. The memory controller 2230 may correspond to the memory controller 140 of FIG. 1.

17 is a diagram illustrating a data processing system 3000 according to an exemplary embodiment of the present invention. Referring to FIG. 17, the data processing system 3000 may include a host processor 3100, a memory system 3200, an interposer 3300, and a semiconductor substrate 3400.

The host processor 3100 and the memory system 3200 may be disposed on one surface of the interposer 3300.

The interposer 3300 may electrically connect the host processor 3100 and the memory system 3200. Signals such as commands, addresses, data, and the like may be transferred between the host processor 3100 and the memory system 3200 through the interposer 3300. The interposer 3300 may be mounted on the semiconductor substrate 3400.

The host processor 3100 may correspond to the host processor 110 of FIG. 1.

The memory system 3200 may include a stacked logic semiconductor device 3210 and a memory device 3220. The logic semiconductor device 3210 may control an operation of the memory system 3200. The logic semiconductor device 3210 may include a processor 3211 and a memory controller 3212. The processor 3211 may correspond to the processor 120 of FIG. 1. The memory controller 3212 may correspond to the memory controller 140 of FIG. 1.

The memory device 3220 may correspond to the shared memory 130 of FIG. 1.

The memory system 3200 may include, for example, a high bandwidth memory (HBM).

18 is a diagram illustrating a network system 4000 including a data processing system 4150 according to an embodiment of the present invention. Referring to FIG. 18, the network system 4000 may include a server system 4100 and a plurality of client systems 4410 ˜ 4430 connected through the network 4500.

The server system 4100 may service data in response to a request of the plurality of client systems 4410 to 4430. For example, the server system 4100 may store data provided from the plurality of client systems 4410-4430. As another example, the server system 4100 may provide data to the plurality of client systems 4410-4430.

Server system 4100 may include a data processing system 4150. The data processing system 4150 may include the data processing system 100 of FIG. 1, the data processing system 1000 of FIG. 15, the data processing system 2000 of FIG. 16, and the data processing system 3000 of FIG. 17. Can be.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above are exemplary in all respects and are not intended to be limiting. It must be understood as. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

100: data processing system
110: host processor
120: processor
130: shared memory
140: memory controller
145: mail box

Claims (31)

Shared memory;
A host processor configured to process a first task by owning ownership of the shared memory and accessing the shared memory;
A processor configured to receive and own the ownership from the host processor and to process a second job by accessing the shared memory; And
A memory controller coupled between the host processor, the processor and the shared memory, the memory controller configured to allow access to the shared memory of the host processor or the processor in accordance with ownership;
The memory controller includes a mailbox,
And the host processor transfers or reclaims the ownership by accessing the mailbox. The method of claim 1,
The memory controller,
A controller configured to assign the ownership to the host processor or a processor in response to the host processor's access to the mailbox; And
An interface unit configured to form a path between the host processor, the shared memory, and the control unit under control of the control unit;
And the control unit controls the interface unit to change the path according to the change of ownership ownership. The method of claim 2,
And the processor is coupled to the controller and accesses the shared memory through the controller when owning the ownership. The method of claim 2,
The control unit forms a first data path and a first command path between the shared memory and the control unit to assign the ownership to the processor in response to the first access of the host processor to the mailbox. And form a second data path between the host processor and the controller. The method of claim 4, wherein
And the control unit transmits previous confirmation data to the host processor through the second data path in response to the first access. The method of claim 4
The control unit may include a third data path and a second command path between the host processor and the shared memory, so that the interface unit assigns the ownership to the host processor in response to a second access of the host processor to the mailbox. A data processing system that controls to form a. The method of claim 6
And the controller is further configured to transmit ownership confirmation data to the host processor through the second data path in response to the second access, and then assign the ownership to the host processor. The method of claim 4, wherein
The host processor transfers the ownership to the processor, and then transmits job information on the second job to the controller through the second data path.
The control unit stores the job information in the mailbox under the control of the host processor. The method of claim 8,
And the processor reads and confirms the job information from the mailbox and processes the second job. The method of claim 4, wherein
The processor stores the operation result data of the second task in the mailbox,
And the host processor reads the operation result data from the mailbox via the second data path. The method of claim 2
And the host processor is simultaneously connected to the interface unit and the control unit through a host command path, and transmits an access command to the shared memory or the mailbox in the host command path. The method of claim 11,
The host processor allocates a first address range to the mailbox that does not overlap with a second address range allocated to the shared memory.
And the controller is configured to process the access command by comparing an address of an access command transmitted from the host processor with the first address range and the second address range. The method of claim 1,
The mailbox includes an ownership transfer area,
And the host processor transmits a read command for the transfer ownership region to the memory controller to transfer the ownership to the processor. The method of claim 13,
The mailbox further includes an ownership recovery area,
And the host processor transmits a read command for the ownership recovery area to the memory controller to recover the ownership from the processor. The method of claim 1,
The memory controller stores state information of the processor in the mailbox;
The host processor transfers the ownership to the processor, reads the status information from the mailbox, determines whether the processor has finished the second task, and recovers the ownership from the processor according to a determination result. Data processing system. The method of claim 15,
And the host processor reclaims the ownership and reads the operation result data of the second job from the shared memory through the memory controller. Shared memory;
A processor configured to take over ownership from a host processor and process the job by accessing the shared memory; And
A memory controller coupled between the host processor, the processor and the shared memory, the memory controller configured to allow access to the shared memory of the host processor or the processor in accordance with ownership;
The memory controller includes a data box accessed by the host processor to transfer the ownership to the processor. The method of claim 17,
The memory controller,
A controller configured to assign the ownership to the host processor or a processor in response to the host processor's access to the mailbox; And
An interface unit configured to form a path between the host processor, the shared memory, and the control unit under control of the control unit;
And the control unit controls the interface unit to change the path according to the change of ownership ownership. The method of claim 18,
And the processor is coupled to the controller and accesses the shared memory through the controller when owning the ownership. The method of claim 18,
The control unit forms a first data path and a first command path between the shared memory and the control unit to assign the ownership to the processor in response to the first access of the host processor to the mailbox. And form a second data path between the host processor and the controller. The method of claim 20,
And the control unit transmits previous confirmation data to the host processor through the second data path in response to the first access. The method of claim 20
The control unit may include a third data path and a second command path between the host processor and the shared memory, so that the interface unit assigns the ownership to the host processor in response to a second access of the host processor to the mailbox. A data processing system that controls to form a. The method of claim 22,
And the controller is further configured to transmit ownership confirmation data to the host processor through the second data path in response to the second access, and then assign the ownership to the host processor. The method of claim 20,
And the control unit stores, in the mailbox, job information about the second job transmitted from the host processor through the second data path after the ownership is transferred to the processor. The method of claim 24,
And the processor reads and confirms the job information from the mailbox and processes the second job. The method of claim 20,
And the processor stores the job result data of the second job in the mailbox such that the host processor reads the job result data of the second job via the second data path. The method of claim 18
And the interface unit and the controller are simultaneously connected to the host processor through a host command path and receive an access command to the shared memory or the mailbox through the host command path. The method of claim 27,
The mailbox is allocated from the host processor with a first address range that does not overlap with a second address range allocated to the shared memory,
And the controller is configured to process the access command by comparing an address of an access command transmitted from the host processor with the first address range and the second address range. The method of claim 17,
The mailbox includes an ownership transfer area,
And when the memory controller receives a read command for the previous ownership area from the host processor, assigns the ownership to the processor. The method of claim 29
The mailbox further includes an ownership recovery area,
And when the memory controller receives a read command for the ownership recovery area from the host processor, assigns the ownership to the host processor. The method of claim 17,
And the memory controller stores state information of the processor in the mailbox for the host processor to read.

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