KR102520832B1 - Micro display device and display integrated circuit - Google Patents

Abstract

The present embodiments relate to a microdisplay device and a display integrated circuit, and more particularly, to include M*N pixel array units in which a plurality of subpixels defined by a plurality of gate lines and a plurality of data lines are arranged. It relates to a micro display device and a display integrated circuit having various sizes and resolutions, including a display panel chip and a driving circuit for driving the plurality of gate lines and the plurality of data lines.

Description

Micro display device and display integrated circuit {MICRO DISPLAY DEVICE AND DISPLAY INTEGRATED CIRCUIT}

The present invention relates to a micro display device and a display integrated circuit.

A display device includes a display panel in which a plurality of subpixels are arranged, and various driving circuits such as a source driving circuit and a gate driving circuit for driving the display panel.

In a conventional display device, in a display panel, transistors, various electrodes, and various signal wires are formed on a glass substrate, and driving circuits that can be implemented as an integrated circuit are mounted on a printed circuit, and the display panel is provided through the printed circuit. is electrically connected with

This existing structure is suitable for a large display device, but is not suitable for a small display device.

On the other hand, many various electronic devices requiring small display devices, such as virtual reality devices and augmented reality devices, are emerging. Accordingly, a micro display device manufactured in a very small size has been proposed.

In general, a micro display device is implemented in the form of a chip on a silicon substrate (silicon semiconductor substrate). Therefore, as the size of the micro display device increases, the size of the chip also increases, resulting in a decrease in yield.

On the other hand, recently, the demand for a large screen and high resolution has increased even in a micro display device. The demand for such a large screen and high resolution consequently increases the size of the chip, thereby reducing the production yield of the micro display device and increasing the manufacturing cost.

Also, whenever the size and resolution are changed, the display device has to be redesigned, which is inconvenient.

Due to this, it is not possible to provide micro display devices of various sizes and resolutions.

An object of embodiments of the present invention is to provide a micro display device and a display integrated circuit capable of displaying a large screen and high resolution image.

Another object of embodiments of the present invention is to provide a micro display device and a display integrated circuit capable of reducing manufacturing costs.

Another object of embodiments of the present invention is to provide micro display devices and display integrated circuits having various sizes and resolutions.

In one aspect, embodiments of the present invention are a display panel chip including M * N pixel array units in which a plurality of sub-pixels defined by a plurality of gate lines and a plurality of data lines are arranged and a plurality of gate lines and A micro display device including a driving circuit for driving a plurality of data lines may be provided.

In the display panel chip, M*N pixel array units may be arranged to correspond to at least one of a predetermined size or resolution.

Here, the display panel chip may be obtained by sawing a plurality of pixel array units manufactured on a silicon wafer in units of M * N groups.

The plurality of pixel array units may include a pixel array region in which a plurality of subpixels are arranged and a through region in which a plurality of through electrodes connected to a plurality of gate lines and a plurality of data lines are disposed in an outer region of the pixel array region. there is.

The driving circuit includes a plurality of gate driving circuits for driving a plurality of gate lines through a plurality of gate through electrodes connected to a plurality of gate lines among the plurality of through electrodes, and a plurality of data lines among the plurality of through electrodes. A plurality of source driving circuits for driving a plurality of data lines through the data penetration electrode may be included.

The driving circuit includes M*N driving chips including at least one gate driving circuit among a plurality of gate driving circuits and at least one source driving circuit among a plurality of source driving circuits, and the M * N driving chips are configured to display It may be disposed under the panel chip.

Each of the M*N driving chips may further include at least one controller controlling at least one gate driving circuit and at least one source driving circuit.

The driving circuit may further include an integrated controller that receives input image data, divides the received input image data into M*N divided image data for each region, and transfers the received input image data to the controller included in each of the M*N driving chips. can

The driving circuit receives input image data, divides the received input image data into M*N divided image data for each region, and includes at least one gate driving circuit for each of the M*N driving chips according to the divided image data; An integrated controller controlling at least one source driving circuit may be further included.

The micro display device may further include an active interposer disposed below the display panel chip.

In such an active interposer, a plurality of gate driving circuits and a plurality of source driving circuits are disposed, electrically connects a plurality of gate driving circuits and a plurality of gate through-electrodes, and multiple source passive circuits and a plurality of data through-electrodes. It may include a plurality of redistribution lines electrically connected to each other.

The active interposer may further include an integrated controller controlling the plurality of gate driving circuits and the plurality of source driving circuits.

The micro display device may further include a passive interposer disposed below the display panel.

Such a passive interposer includes a plurality of gate redistribution lines electrically connecting a plurality of gate through electrodes of pixel array units arranged adjacent to each other among M * N pixel array units, and a plurality of data through electrodes electrically connected to each other. may include a plurality of data redistribution lines connecting to

The driving circuit may include at least one gate driving chip including at least one gate driving circuit among a plurality of gate driving circuits and at least one source driving chip including at least one source driving circuit among a plurality of source driving circuits. can

Here, at least one gate driving chip is disposed in a first direction in which a plurality of gate lines extend from the display panel chip, and at least one source driving chip is disposed in a second direction in which a plurality of source lines extend in the display panel chip. can be placed on the side.

The passive interposer includes a gate driving redistribution line electrically connecting a plurality of gate through-electrodes of the pixel array unit disposed on the outermost side in the first direction among M * N pixel array units and at least one gate driving chip, and M * Data drive redistribution lines electrically connecting a plurality of data through electrodes of the pixel array unit disposed at the outermost side in the second direction among the N pixel array units and at least one source driving chip may be further included.

The driving circuit may further include a control chip that controls at least one gate driving chip and at least one source driving chip.

The passive interposer may further include a control redistribution line electrically connecting the at least one gate driving chip and the at least one source driving chip to the control chip.

In another aspect, embodiments of the present invention may provide a display integrated circuit including M * N pixel array units in which a plurality of sub-pixels each defined by a plurality of gate lines and a plurality of data lines are arranged. .

These M*N pixel array units may be obtained by sawing M*N pixel array units in group units corresponding to at least one of a predetermined size or resolution among a plurality of pixel array units on a silicon wafer.

According to the embodiments of the present invention as described above, it is possible to provide a micro display device and a display integrated circuit capable of displaying a large screen and high resolution image.

In addition, according to the embodiments of the present invention, it is possible to provide a micro display device and a display integrated circuit capable of reducing manufacturing costs.

In addition, according to embodiments of the present invention, micro display devices and display integrated circuits having various sizes and resolutions can be provided.

1 shows an example of an electronic device using a micro display device according to embodiments of the present invention.
2 is a schematic system configuration diagram of a micro display device according to embodiments of the present invention.
3 and 4 are pixel structures of a micro display device according to embodiments of the present invention.
4 shows an example of an electronic device using a micro display device according to embodiments.
5 is a diagram conceptually illustrating a micro display device according to embodiments of the present invention.
6 is a diagram showing a schematic structure of a micro display device according to embodiments of the present invention.
FIG. 7 is a diagram schematically showing the structure of a display panel chip (DPC) of FIG. 6 .
FIG. 8 is a diagram schematically illustrating the structure of the driving circuit chip (DCC) of FIG. 6 .
9 is a diagram showing another structure of a micro display device according to embodiments of the present invention.
10 is a diagram showing another structure of a micro display device according to embodiments of the present invention.
11 and 12 are diagrams showing another structure of the micro display device according to the exemplary embodiments of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention are described in detail below with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

Also, terms such as first, second, A, B, (a), and (b) may be used in describing the components of the present invention. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

1 shows an example of an electronic device using a micro display device according to embodiments of the present invention.

Referring to FIG. 1 , an electronic device 100 according to embodiments is an HMD-type device that is a type of wearable device that displays augmented reality or virtual reality images.

An electronic device 100 according to embodiments includes an image signal input unit 110 into which image data is input, a first display device 120L displaying a first image (eg, a left eye image) based on the image signal, and an image A case accommodating the second display device 120R displaying a second image (eg, right eye image) based on a signal, the image signal input unit 110, the first display device 120L, and the second display device 120R. (130) and the like.

The video signal input unit 110 may include a wired cable or a wireless communication module connected to a terminal (eg, smart phone, etc.) that outputs video data.

The first display device 120L and the second display device 120R are display components located at positions corresponding to the user's left and right eyes.

Each of the first display device 120L and the second display device 120R may include all or part of the micro display device 200 .

Although the video signal input unit 110 is shown as a wired line in FIG. 1, the video signal input unit 110 may be implemented as a wireless interface.

2 is a schematic system configuration diagram of a micro display device according to embodiments of the present invention.

Referring to FIG. 2 , a microdisplay device 200 according to embodiments of the present invention may have a backplane structure in which a pixel array PXL and various driving circuits are formed on a silicon substrate 210 .

The silicon substrate 210 may be p-type or n-type. In this specification, "p" means a hole (Hole), and "n" means an electron (electron).

The silicon substrate 210 may include a pixel array zone (PAZ) where the pixel array PXL is disposed and a circuit zone (CZ) where various driving circuits are disposed.

The circuit area CZ of the silicon substrate 210 may be positioned around the pixel array area PAZ of the silicon substrate 210 . For example, the circuit area CZ may be present on one side, two sides, or three sides of the pixel array area PAZ, or may exist while surrounding the periphery of the pixel array area PAZ.

The pixel array PXL includes a plurality of data lines DL and a plurality of gate lines GL and a plurality of subpixels defined by the plurality of data lines DL and the plurality of gate lines GL. fields (SP) are disposed.

As shown in FIG. 2 , on the pixel array PXL, the data lines DL may be disposed to extend in a first direction, and the gate lines GL may extend in a second direction different from the first direction. can be placed.

Also, on the pixel array PXL, in addition to the plurality of data lines DL and the plurality of gate lines GL, signal wires for supplying various signals and voltages to the plurality of subpixels SP are disposed. may be

For example, the signal wires disposed on the pixel array PXL may further include a driving voltage line for transmitting a driving voltage, and in some cases, may further include a sensing line for transmitting a reference voltage or sensing a voltage. can

Signal lines disposed on the pixel array PXL may be electrically connected to driving circuits disposed on the circuit zone CZ of the silicon substrate 210 .

Meanwhile, the driving circuits disposed on the circuit zone CZ of the silicon substrate 210 include at least one source driving circuit SDC for driving data lines and at least one gate driving circuit for driving gate lines ( GDC), and a controller CONT that controls operations of at least one source driving circuit SDC and gate driving circuit GDC.

The controller CONT controls the source driving circuit SDC and the gate driving circuit GDC by supplying various control signals DCS and GCS to the source driving circuit SDC and the gate driving circuit GDC.

The controller (CONT) starts scanning according to the timing implemented in each frame, and converts the input image data input from the outside to suit the data signal format used in the source driving circuit (SDC) to convert the converted image data (Data ), and controls data drive at an appropriate time according to the scan.

The controller CONT may be a timing controller used in a typical display technology or a control device that further performs other control functions including the timing controller.

The source driving circuit SDC drives the plurality of data lines DL by receiving the image data Data from the controller CONT and supplying data voltages to the plurality of data lines DL. Here, the source driving circuit SDC is also referred to as a data driving circuit.

The source driving circuit (SDC) may include a shift register, a latch circuit, a digital to analog converter (DAC), an output buffer, and the like.

In some cases, the source driving circuit SDC may further include an analog to digital converter (ADC).

The gate driving circuit GDC sequentially drives the plurality of gate lines GL by sequentially supplying scan signals to the plurality of gate lines GL. Here, the gate driving circuit GDC is also referred to as a scan driving circuit.

The gate driving circuit GDC may include a shift register, a level shifter, and the like.

The gate driving circuit GDC sequentially supplies scan signals of an on voltage or an off voltage to the plurality of gate lines GL under the control of the controller CONT.

When a specific gate line is opened by the gate driving circuit (GDC), the source driving circuit (SDC) converts the image data (DATA) received from the controller (CONT) into an analog type of data voltage to generate a plurality of data lines (DL). ) is supplied.

The source driving circuit SDC may be located on only one side (eg, upper side or lower side) of the pixel array PXL, and in some cases, depending on a driving method or a design method, the source driving circuit SDC may be located on both sides of the pixel array PXL (eg, upper side and lower side) may be located on both sides.

The gate driving circuit GDC may be located on only one side (eg, the left side or the right side) of the pixel array PXL. : left and right) may be located on both sides.

The type and number of circuit elements constituting each sub-pixel SP may be variously determined according to a provided function and a design method.

Meanwhile, the driving circuit disposed on the circuit zone CZ transfers various signals and voltages necessary for driving the subpixels SP arranged in the pixel array PXL to other circuits SDC1, SDC2, GDC, and CONT. A power circuit (PSC) for providing or supplying to the pixel array (PXL) may be further included.

Here, the power circuit PSC may include a power generator such as a DC-DC converter to generate and output various voltages required by the pixel array PXL from various power supply voltages supplied from the outside.

In addition, a pad part PAD having a plurality of pads may be disposed on the circuit zone CZ of the silicon substrate 210 to electrically connect other electronic components and driving circuits outside the silicon substrate 210 .

A plurality of pads of the pad unit PAD may be used for signal input/output, power supply, or communication. In FIG. 2 , the pad part PAD is illustrated as being disposed on only one side of the silicon substrate 210 , but the position of the pad part PAD may be adjusted in various ways, and may be distributed and disposed in various positions.

All or part of the micro display device 200 according to the embodiments of the present invention described above may be made in a manufacturing process of a silicon wafer.

Accordingly, all or part of the micro display device 200 according to embodiments of the present invention may be referred to as a display integrated circuit.

As described above, the micro display device 200 includes driving circuits such as a source driving circuit (SDC), a gate driving circuit (GDC), a controller (CONT), and a power circuit (PSC) as well as a pixel array (PXL) on a silicon substrate. By forming all on the 210, the size of the device can be miniaturized, and the manufacturing process can be performed easily and quickly.

3 and 4 are pixel structures of a micro display device according to embodiments of the present invention.

FIG. 3 shows a circuit structure of a subpixel SP, and FIG. 4 shows a cross-sectional structure of a pixel including red (R), green (G), and blue (B) subpixels.

Referring to FIG. 3 , each subpixel SP includes an organic light emitting diode OLED, a driving transistor DRT driving the organic light emitting diode OLED, and a first node N1 of the driving transistor DRT. and a first transistor T1 electrically connected between the data line DL and a capacitor Cst electrically connected between the first node N1 and the second node N2 of the driving transistor DRT. can be implemented.

The organic light emitting diode (OLED) may include a first electrode (eg, an anode electrode or a cathode electrode), an organic light emitting layer (OEL), and a second electrode (eg, a cathode electrode or an anode electrode).

A first electrode of the organic light emitting diode OLED may be electrically connected to the second node N2 of the driving transistor DRT. The ground voltage EVSS may be applied to the second electrode of the organic light emitting diode OLED.

Here, the base voltage EVSS may be a kind of common voltage applied to all subpixels SP.

The driving transistor DRT drives the organic light emitting diode OLED by supplying a driving current Ioled to the organic light emitting diode OLED.

The driving transistor DRT has a first node N1 , a second node N2 , and a third node N3 .

The first node N1 of the driving transistor DRT is a node corresponding to a gate node and may be electrically connected to a source node or a drain node of the first transistor T1.

The second node N2 of the driving transistor DRT may be electrically connected to the first electrode of the organic light emitting diode OLED, and may be a source node or a drain node.

The third node N3 of the driving transistor DRT is a node to which the driving voltage EVDD is applied, and may be electrically connected to the driving voltage line DVL supplying the driving voltage EVDD, and may be a drain node or a source node. can be

Here, the driving voltage EVDD may be a kind of common voltage applied to all subpixels SP.

The first transistor T1 may be turned on and off by receiving the first scan signal SCAN1 to the gate node through the gate line.

The first transistor T1 is turned on by the first scan signal SCAN1 to transfer the data voltage Vdata supplied from the data line DL to the first node N1 of the driving transistor DRT. can

Such a first transistor T1 is also referred to as a switching transistor.

The capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, so that the data voltage Vdata corresponding to the image signal voltage or the voltage corresponding thereto is stored in one frame. You can keep it for hours.

As described above, one subpixel (SP) illustrated in FIG. 3 is 2T (Transistor) 1C including two transistors (DRT) and one capacitor (Cst) to drive an organic light emitting diode (OLED). (Capacitor) structure.

The subpixel structure (2T1C structure) illustrated in FIG. 3 is only an example for convenience of description. Depending on the function, panel structure, etc., one subpixel (SP) further includes one or more transistors or one or more capacitors. may further include.

For example, the sub-pixel may further include at least one transistor connected to a sensing line in order to sense a driving transistor (DRT) or organic light emitting diode (OLED) characteristic value.

This is a configuration for improving the picture quality of a micro display device by compensating for deviations between sub-pixels.

Meanwhile, the capacitor Cst is not a parasitic capacitor (eg, Cgs or Cgd) that is an internal capacitor existing between the first node N1 and the second node N2 of the driving transistor DRT, but It may be an external capacitor intentionally designed outside the driving transistor DRT.

Each of the driving transistor DRT and the first transistor T1 may be an n-type transistor or a p-type transistor.

Also, in some cases, each of a plurality of subpixels may have the same structure, and some of the plurality of subpixels may have a different structure.

In FIG. 4 , the silicon substrate 210 may be a p-type substrate or an n-type substrate. Here, it is assumed that the silicon substrate 210 is a p-type substrate.

An insulating layer ISO is disposed on the silicon substrate 210 , and a gate electrode G, a source electrode S, and a drain electrode D are disposed in the insulating layer ISO.

Also, the driving transistor DRT is disposed on the silicon substrate 210 .

The source and drain of the driving transistor DRT may be disposed at positions corresponding to the source electrode S and the drain electrode D in the silicon substrate 210 .

The gate of the driving transistor DRT is disposed in the insulating layer ISO and is disposed at a position corresponding to the gate electrode G.

Also, the gate, source, and drain of the driving transistor DRT may be electrically connected to the gate electrode G, the source electrode S, and the drain electrode D through contact holes, respectively.

Meanwhile, the contact metal CM disposed in the insulating layer ISO may be connected to the source electrode S or the drain electrode D through a contact hole of the insulating layer ISO. Here, the contact metal CM may be the sensing line SL.

Meanwhile, the first electrode E1 of the organic light emitting diode OLED may be disposed on the insulating layer ISO. The first electrode E1 may be electrically connected to the contact metal CM through the contact hole of the insulating layer ISO. Here, the first electrode E1 may be an anode electrode of the organic light emitting diode (OLED).

An emission layer EL may be disposed on the first electrode E1, and a second electrode E2 of the organic light emitting diode OLED may be disposed on the emission layer EL. Here, the second electrode E2 may be a cathode electrode of the organic light emitting diode (OLED).

As shown in FIG. 4 , the second electrode E2 may be a common electrode formed in common with a plurality of subpixels.

The organic light emitting diode (OLED) is implemented by the first electrode E1, the light emitting layer EL, and the second electrode E2.

Meanwhile, a protective layer ICS may be disposed on the second electrode E2 , and a color filter layer CF may be disposed on the protective layer ISC. Here, the color filter layer CF is used to implement red (R), green (G), and blue (B) subpixels. A red filter, a green filter, and a blue filter may be included.

A protective cover COV may be disposed on the color filter layer CF. In this case, the protective cover COV may be attached by an adhesive layer ADH.

In FIG. 4 , as an example of a micro display device, the light emitting layer EL is configured to emit light of a single color. Further, the color filter layer CF enables the light emitted from the light emitting layer EL to express red (R), green (G), and blue (B) lights corresponding to each subpixel. In this case, the light emitting layer EL may emit white light.

However, as another example, a plurality of different light emitting layers emitting red (R), green (G), and blue (B) light are disposed corresponding to subpixels, so that each subpixel emits red (R) and green (G) light. And it may be configured to express blue (B) light. In this case, the color filter layer CF may be omitted.

In addition, although FIG. 4 shows a case in which three subpixels corresponding to red (R), green (G), and blue (B) constitute one pixel, four subpixels may constitute one pixel. For example, the four subpixels may be subpixels that emit red (R), green (G), blue (B), and white (W) lights.

In such a micro display device, an organic light emitting diode (OLED) may be formed through a deposition method after several circuit elements of a subpixel including a driving transistor (DRT) are generally formed on a silicon substrate 210 .

On the other hand, recently, a demand for a high resolution of a large screen has increased even in the micro display device 200 .

However, if the size of the micro display device 200 is increased to provide a high resolution of the large screen, the production yield is greatly reduced and the manufacturing cost is increased.

In addition, as shown in FIG. 2 , in the micro display device 200 in which the pixel array (PXL) and the driving circuit are co-located on a single silicon substrate 210, when a change in screen size and/or resolution is required, the pixel array Not only the size of the area PAZ is changed, but also the shape and size of the circuit area CZ surrounding the outer area of the pixel array area PAZ must be changed.

That is, in order to provide various sizes and resolutions, there is a problem of redesigning and manufacturing the micro display device 200 corresponding to each size and resolution.

5 is a diagram conceptually illustrating a micro display device according to embodiments of the present invention.

As described above, the demand for micro display devices having various sizes and resolutions has recently increased. However, in the general display field, the resolution required for most display devices regularly increases as shown in FIG. 6 .

In order for the display device to output a high-quality image, input image data provided to the display device and resolution of the display device must be matched.

Accordingly, resolutions required for display devices in the display field are mostly prescribed in advance and are regularly increasing.

For example, as shown in FIG. 6 , when a first pixel array PXL1 having a resolution of Full HD (1920 * 1080) is referred to as a pixel array unit PXLU, a first pixel array having a resolution of 4K UHD (3840 * 2160) The 2-pixel array PXL2 can be viewed as having four pixel array units PXLU arranged in a 2*2 matrix pattern.

In addition, the third pixel array PXL3 having a resolution of 8K UHD (7680 * 4320) can be regarded as having 16 pixel array units PXLUs arranged in a 4 * 4 matrix pattern.

As an example, FIG. 5 shows a case where the pixel array units PXLUs are arranged in 2*2 and 4*4 matrix patterns, but the pixel array units PXLUs may be arranged in various patterns and numbers.

Accordingly, the pixel arrays PXL2 and PXL3 having various resolutions and sizes may be configured by arranging a plurality of pixel array units PXLU adjacent to each other.

That is, if the micro display device can arrange a plurality of pixel array units (PXLUs) adjacent to each other, images of various resolutions and sizes can be provided.

However, in the micro display device 200 of FIG. 2 , a circuit area CZ in which a driving circuit is disposed exists outside the pixel array area PAZ in which the pixel array PXL is disposed.

Accordingly, the micro display device 200 of FIG. 2 cannot structurally arrange a plurality of pixel arrays PXL adjacently. That is, the pixel array PXL shown in FIG. 2 cannot be used as the pixel array unit PXLU.

6 is a diagram showing a schematic structure of a micro display device according to embodiments of the present invention.

Referring to FIG. 6 , a microdisplay device 600 according to example embodiments may include a display panel chip (DPC) and a driving circuit chip (DCC).

Also, the display panel chip DPC and the driving unit DVU have a stacked structure. As shown in FIG. 6 , the driving circuit chip DCC may be disposed below the display panel chip DPC.

However, the driving circuit chip DCC may be disposed on the side of the display panel chip DPC.

The display panel chip DPC includes a plurality of pixel array units PXLUs arranged in a matrix pattern.

6 shows that the display panel chip (DPC) includes 2*2 pixel array units (PXLUs) as an example, but the number of pixel array units (PXLUs) included in the display panel chip (DPC) is a micro display device. It can be variously adjusted according to the size or resolution required for 600.

In addition, the plurality of pixel array units PXLU includes a plurality of gate lines GL, a plurality of data lines GL, and a plurality of sub-pixels (defined by the plurality of gate lines GL and the plurality of data lines GL). SP) is placed.

Here, the plurality of pixel array units PXLU is the same sub-pixel array PXL and includes the same number of sub-pixels SP.

Here, each of the plurality of pixel array units PXLU is a die manufactured on a silicon wafer according to a manufacturing process (semiconductor process) and can be regarded as a kind of integrated circuit.

Further, each of the plurality of pixel array units PXLUs further includes a plurality of through silicon vias (TSVs) electrically connected to the plurality of gate lines and the plurality of data lines.

As is well known, a through electrode (TSV) is an electrical connection line that penetrates the inside of a chip by being implemented by filling a conductive material in a fine via penetrating a silicon wafer.

Therefore, the plurality of through electrodes TSV electrically connect the plurality of gate lines and the plurality of data lines disposed on the plurality of pixel array units PXLU by penetrating to the bottom of the plurality of pixel array units PXLU.

As the plurality of pixel array units PXLU include the through electrode TSV, the plurality of pixel array units PXLU may be electrically connected to the driving unit DVU through the through electrode TSV.

Meanwhile, the driving circuit chip DCC may include a plurality of driving units DVU corresponding to the plurality of pixel array units PXLU included in the display panel chip DPC.

The plurality of driving units DVU are provided with the same size and number as the plurality of pixel array units PXLU, and are disposed under the corresponding pixel array units PXLU.

And like the pixel array unit (PXLU), the plurality of driving units (DVU) are also dies manufactured on a silicon wafer according to a manufacturing process (semiconductor process) and can be regarded as a kind of integrated circuit.

The plurality of driving units DVU includes at least one gate driving circuit GDC and a source driving circuit for driving the plurality of gate lines GL and the plurality of data lines DL disposed in the corresponding pixel array unit PXLU. It may include a low (SDC).

Also, the plurality of driving units DVU may include a plurality of connection ports PRT electrically connected to at least one gate driving circuit GDC and the source driving circuit SDC.

The plurality of connection ports PRT may be formed of conductive bumps, solder balls, or conductive spacers arranged in a sphere aligned with the through electrodes TSV of the corresponding pixel array unit PXLU. spacer) to electrically connect at least one gate driving circuit GDC and at least one source driving circuit SDC of the driving unit DVU to the through electrodes TSV of the pixel array unit PXLU.

That is, the plurality of driving units DVU connect the plurality of gate lines GL and the plurality of data lines DL of the pixel array unit PXLU through the plurality of connection ports PRT and the plurality of through electrodes TSV. can drive

In addition, the plurality of driving units DVU may further include a plurality of penetration electrodes or a plurality of pads to be connected to an external device.

Meanwhile, the plurality of driving units DVU may further include a controller CONT for controlling at least one gate driving circuit GDC and at least one source driving circuit SDC.

The controller CONT receives input image data from an external device through a plurality of through electrodes or a plurality of pads, and according to the received input image data, at least one gate driving circuit (GDC) and at least one source driving circuit ( SDC) can be controlled.

At this time, the input image data may be a divided part of the input image data for the entire image to be displayed on the micro display device 600 . That is, the controller CONT of each of the plurality of driving units DVU may receive divided input image data and control at least one gate driving circuit GDC and at least one source driving circuit SDC.

In this case, the micro display device 600 may further include a separate integrated controller. The integrated controller receives input image data from an external device and divides the received input image data according to the number and arrangement positions of the plurality of pixel array units (PXLUs) included in the display panel chip (DPC). In addition, the divided input image data may be transmitted to the driving unit DVU corresponding to each pixel array unit PXLU.

The integrated controller may be implemented as a semiconductor chip disposed on a silicon substrate, similar to a display panel chip (DPC) or a driving circuit chip (DCC), but is electrically connected to through electrodes or pads of a plurality of driving units (DVU). It may be implemented as a separate circuit.

In addition, when the controller is not included in the plurality of driving units (DVU), the integrated controller includes at least one gate driving circuit (GDC) and at least one source driving circuit through through electrodes or pads of the plurality of driving units (DVU). (SDC) can also be directly controlled.

As a result, the micro display device 600 according to the embodiments of the present invention shown in FIG. 6 distinguishes a component for displaying an image from a component for controlling it and separately arranges them, thereby displaying an image. A plurality of pixel array units (PXLUs) may be disposed adjacent to each other on the display panel chip (DPC), which is a configuration for the display.

In addition, the driving circuit chip (DCC) including the plurality of driving units (DVU) controls the corresponding plurality of pixel array units (PXLUs), so that the plurality of pixel array units (PXLUs) are combined and arranged in various patterns. Even if it is, it is possible to express the image according to the arrangement position.

Accordingly, the micro display device 600 of FIG. 6 may combine and arrange a plurality of pixel array units (PXLUs) in various patterns and numbers, thereby displaying images of various resolutions and sizes.

FIG. 7 is a diagram schematically showing the structure of the display panel chip (DPC) of FIG. 6 , and FIG. 8 is a diagram schematically showing the structure of the driving circuit chip (DCC) of FIG. 6 .

5 and 6, by arranging a plurality of pixel array units (PXLUs) adjacently, the micro display device 600 can display images of various resolutions and sizes.

However, it is very difficult to adjacently place a plurality of pixel array units (PXLUs) fabricated in the form of semiconductor dies on a silicon wafer and separated by sawing.

In particular, it is very difficult to accurately adjust the spacing or position between adjacent pixel array units (PXLUs) and arrange them in an accurate position.

If the arrangement positions and directions of the pixel array units PXLU are not accurately aligned, images displayed in each pixel array unit PXLU are also not accurately aligned.

Also, there is a limit to reducing the distance between adjacent pixel array units PXLUs.

This problem makes it difficult to recognize the entire image displayed on the micro display device 600 as one image, and the micro display device 600 cannot display a high quality image.

In addition, even when the plurality of pixel array units PXLUs are not arranged at uniform heights, that is, even when the surface heights of the pixel array units PXLUs are not uniformly arranged, the micro display device 600 provides a high-quality display. The image cannot be expressed.

Accordingly, embodiments of the present invention correspond to the size or resolution required for the micro display device 600 in a pixel array unit wafer (PXLU wafer) on which a plurality of pixel array units (PXLUs) are manufactured, as shown in FIG. 7 . The display panel chip DPC is obtained by sawing M * N (where M and N are natural numbers) pixel array units PXLU in group units.

However, when sawing M * N pixel array units PXLUs in groups, the yield may be lowered because the size of the display panel chip DPC is the same as the increased size.

However, the pixel array units PXLU are each individually driven semiconductor die. Therefore, when it is determined that a specific pixel array unit (PXLU) has a defect on the pixel array unit wafer (PXLU wafer), M * N pixel array units (PXLUs) are selected so that the defective pixel array unit (PXLU) is not included. can be sawed

Accordingly, the yield may be higher than when the display panel chip (DPC) is manufactured with a single semiconductor die.

In addition, individual pixel array units (PXLUs) that are not included in M*N pixel array unit (PXLU) groups on a pixel array unit wafer (PXLU wafer) may be used in a micro display device requiring a lower resolution. That is, since individual pixel array units PXLUs can be recycled, productivity can be increased and manufacturing costs can be reduced.

In FIG. 7, referring to FIG. 6, it is assumed that the display panel chip (DPC) includes 2*2 pixel array units (PXLUs), but is not limited thereto.

As shown in FIG. 7 , a plurality of pixel array units PXLUs are manufactured in an already aligned state on a pixel array unit wafer PXLU wafer that is a silicon wafer.

In general, a plurality of manufactured pixel array units (PXLUs) are individually sawed and used, but in the embodiments of the present invention, they are not individually sawed, but M * N pixel array units (PXLUs) are grouped as a unit. By sawing, the alignment process for M*N pixel array units (PXLUs) can be eliminated.

Also, since M*N pixel array units PXLUs are disposed on the same pixel array unit wafer, the heights of the pixel array units PXLUs are also uniform.

Although there is a scribe line (SCL), which is a blank space for sawing individual pixel array units (PXLU), between the M * N pixel array units (PXLU), it is a plurality of physically separated pixel array units. This is a very narrow spacing compared to the method of relocating (PXLU).

That is, in the embodiments of the present invention, instead of individually sawing a plurality of pixel array units (PXLUs) on a pixel array unit wafer (PXLU wafer), required M * N pixel array units (PXLUs) are sawed in groups. By doing so, it is possible to further narrow the interval between the M*N pixel array units PXLU.

For example, the width and height of each pixel array unit PXLU may be several cm, and the width of the scribe line SCL may be several tens of μm.

As a result, the micro display device 600 can display high-quality images without a separate alignment process.

Also, the M * N number of pixel array units PXLU may include a pixel array area PAZ and a through area TSVZ.

As described above, a plurality of subpixels SP defined by a plurality of gate lines and a plurality of data lines may be arranged in the pixel array area PAZ.

The pass-through area TSVZ may be disposed in an outer area of the pixel array area PAZ. For example, the through area TSVZ may exist on one side, two sides, or three sides of the pixel array area PAZ, or may exist while surrounding the periphery of the pixel array area PAZ.

A plurality of through electrodes TSV electrically connected to a plurality of gate lines and a plurality of data lines are disposed in the through region.

Here, the plurality of through electrodes may be classified into a gate through electrode and a data through electrode according to a connected line.

Accordingly, the through area includes at least one gate through area (GTSVZ) in which a plurality of gate through electrodes connected to a plurality of gate lines among the plurality of through electrodes are disposed and a plurality of data through areas connected to a plurality of data lines among the plurality of through electrodes. It may include at least one source pass-through region STSVZ in which an electrode is disposed.

At least one gate pass-through area GTSVZ may be present on only one side of the pixel array area PAZ, or may be present on both sides (left and right or upper and lower sides).

Also, at least one source pass-through area STSVZ may be present on only one side of the pixel array area PAZ, or may exist on both sides (left and right or upper and lower sides).

That is, the at least one gate through region GTSVZ is disposed on the side in the first direction where the plurality of gate lines GL extend in the outer region of the pixel array region PAZ, and the at least one source through region STSVZ, In the outer area of the pixel array area PAZ, the plurality of data lines DL may be disposed in the second direction.

The number and arrangement position of the gate pass-through area GTSVZ and the source pass-through area STSVZ are determined by at least one gate driver circuit GDC and at least one source driver disposed in the circuit area CZ of the corresponding drive unit DVU. It may be determined according to the number and arrangement position of the circuits SDC.

In FIG. 8 , the driving circuit chip DCC includes 2x2 driving units DVUs corresponding to the display panel chip DPC including 2x2 pixel array units PXLUs.

Also, the driving unit DVU may be manufactured in an already aligned state on a driving unit wafer (DVU wafer), which is a silicon wafer, and may be obtained by sawing M*N driving units DVU in a group unit.

Also, the M*N driving units DVU may include a circuit zone CZ and a connection zone CPZ.

Here, the connection area CPZ may exist on one side, two sides, or three sides of the circuit area CZ, for example, or may exist while surrounding the periphery of the circuit area CZ.

However, the connection area CPZ is disposed at a position corresponding to the position of the through area TSVZ of the corresponding pixel array unit PXLU.

A driving circuit DRV for driving the plurality of gate lines GL and the plurality of data lines DL is disposed in the circuit area CZ.

Also, a plurality of connection ports PRT electrically connecting the plurality of through electrodes and the driving circuit DRV disposed in the circuit zone CZ are disposed in the connection area CPZ.

Here, the plurality of connection ports PRT are formed by at least one of conductive bumps, solder balls, and conductive spacers disposed in alignment with the through electrodes on the driving unit DVU. can be implemented

Accordingly, as shown in FIG. 6 , the plurality of connection ports PRT may electrically connect the through electrode of the corresponding pixel array unit PXLU and the driving unit DVU.

Meanwhile, the connection region CPZ is disposed at a position corresponding to at least one gate connection region GCPZ disposed at a position corresponding to the at least one gate passing region GTSVZ and at a position corresponding to at least one source passing region STSVZ. It may include at least one source access zone (SCPZ).

As shown in FIG. 8 , the driving circuit chip DCC includes M * N driving units DVU corresponding to the display panel chip DPC including M * N pixel array units PXLU. Accordingly, the M*N driving units DVU of the driving circuit chip DCC may individually drive the M*N pixel array units PXLU.

9 is a diagram showing another structure of a micro display device according to embodiments of the present invention.

In the micro display device 600 of FIG. 6 , M*N driving units DVU of the driving circuit chip DCC may individually control the corresponding pixel array units PXLU of the display panel chip DPC.

However, in some cases, M*N driving units (DVUs) may need to be driven in conjunction.

For example, in order to adjust timings of images to be displayed on M * N pixel array units PXLUs, M * N driving units DVUs may need to check the operation timings of adjacent driving units DVUs.

In this case, a means for electrically connecting the M*N driving units (DVUs) is further required.

Accordingly, the micro display device 900 of FIG. 9 further includes an interposer (ITP).

In general, an interposer (ITP) is used to facilitate electrical connection between a plurality of semiconductor dies or between a semiconductor die and external devices in a single package, and a plurality of redistribution lines may be disposed therein. can

In the micro display device 900 shown in FIG. 9 , the interposer ITP may include a plurality of driving redistribution lines DVRDL and a plurality of gate/data redistribution lines GDRLD.

Here, the plurality of gate/data redistribution lines GDRLD electrically connect the gate lines GL of the pixel array units PXLU disposed adjacent to each other among the M×N pixel array units PXLU, or electrically connect the data lines to each other. (DLs) are electrically connected to each other.

When the gate lines GL and data lines DL of the pixel array units PXLU disposed adjacent to each other are connected through a plurality of gate/data redistribution lines GDRLD, M * N number of pixel array units PXLUs The gate lines GL and data lines DL of ) are driven in connection with each other.

That is, the micro display device 900 of FIG. 9 is a single display panel chip (DPC) corresponding to the size of M * N pixel array units (PXLUs) even though each of the M * N pixel array units (PXLUs) is manufactured as an individual circuit. It can be driven in the same way as driving .

For example, when the gate driving circuit GDC drives the gate line GL of one pixel array unit PXLU among M * N pixel array units PXLU, the gate/data redistribution line GDRLD The gate line GL of another pixel array unit PXLU connected through a channel may be driven together.

That is, the display panel chip (DPC) can be driven in the same way as driving a single display device.

However, as shown in FIG. 9 , since the display panel chip DPC is disposed above the driving circuit chip DCC, it may be directly connected to the gate/data redistribution line GDRLD disposed in the interposer ITP. does not exist.

Accordingly, in FIG. 9 , a through electrode TSV corresponding to the through electrode TSV of the pixel array unit PXLU is disposed also in the driving unit DVU, so that the gate line GL or the data line ( DL) can be connected through the through electrode (TSV) of the pixel array unit (PXLU) and the driving unit (DVU) and the gate/data redistribution line (GDRLD).

Meanwhile, the plurality of driving redistribution lines DVRDL electrically connects driving circuits of the M*N driving units DVU. With such a plurality of driving redistribution lines DVRDL, the driving unit DVU can determine the operating state or timing of the other driving units DVU, and from this, the corresponding pixel array unit PXLU is configured at the correct timing. can drive

In the above, the timing control has been described as a function of the drive redistribution line (DVRDL) as an example, but is not limited thereto.

In addition, when the controller CONT is disposed, the driving redistribution line DVRDL may be used to electrically connect the M*N driving units DVU and the controller CONT.

The micro display device 900 shown in FIG. 9 further includes an interposer (ITP) including a plurality of redistribution lines, so that the pixel array units (PXLUs) of the display panel chip (DPC) and the driving circuit chip (DCC) ) of the drive unit (DVU) and the controller (CONT) can be connected in various ways as needed.

10 is a diagram showing another structure of a micro display device according to embodiments of the present invention.

9 illustrates a micro display device 900 in which a display panel chip (DPC), a driving circuit chip (DCC), and an interposer (ITP) are stacked.

In the micro display device 900 of FIG. 9 , a drive circuit chip (DCC) drives the display panel chip (DPC), and a redistribution line is arranged in the interposer (ITP).

The interposer (ITP) in which the redistribution line is disposed in this way is referred to as a passive interposer.

However, the interposer (ITP) may be made of a silicon substrate as a kind of functional package substrate. Also recently, it can be manufactured as a glass substrate. Accordingly, various circuits may be disposed in the interposer ITP.

Also, an interposer including a circuit as well as a redistribution line is referred to as an active interposer.

In FIG. 10 , a driving interposer (DITP) including a driving circuit (DRV) as an active interposer is exemplified.

Since the driving circuit DRV is disposed within the driving interposer DITP, the micro display device 1000 of FIG. 10 does not include the driving circuit chip DCC unlike the micro display device 900 of FIG. 9 .

Here, the driving circuit DRV may include at least one gate driving circuit GDC and at least one source driving circuit SDC included in the driving circuit chip DCC of FIG. 9 .

And it may further include a controller (CONT).

Also, the drive interposer DITP of FIG. 10 includes a plurality of connection ports PRT and may be electrically connected to the through electrode of the pixel array chip PAC.

Also, as in FIG. 9 , a plurality of redistribution lines may be disposed therein.

Accordingly, in the micro display device 1000 of FIG. 10 , the driving circuit chip (DCC) of the micro display device 600 of FIG. 6 may be replaced with a driving interposer (DITP).

However, as described above, unlike the driving circuit chip DCC, the driving interposer DITP may further arrange a plurality of redistribution lines therein, and thus the display panel chip DPC and the driving circuit DRV At least one gate driving circuit (GDC), at least one source driving circuit (SDC) and the controller (CONT) can be electrically connected more easily.

11 and 12 are diagrams showing another structure of the micro display device according to the exemplary embodiments of the present invention.

6, 9, and 10, the driving circuit DRV for driving the plurality of pixel array units PXLU of the display panel chip DPC is disposed under the display panel chip DPC.

However, FIGS. 11 and 12 show the micro display device 1100 in which the driving circuit DRV for driving the plurality of pixel array units PXLU is disposed on the side of the display panel chip DPC.

Since the micro display devices 600, 900, and 1000 shown in FIGS. 6, 9, and 10 have a structure in which a plurality of pixel array units PXLUs and driving circuits DRV are vertically stacked, the micro display device 600 , 900, 1000) has the advantage that it can be manufactured in a small size.

However, in the case of such a vertical stacking method, heat dissipation may not be easy. In addition, when the driving circuit DRV is included in the active interposer D as in the driving interposer DITP shown in FIG. 10, the design of the driving circuit DRV becomes complicated due to a plurality of redistribution lines. can

Accordingly, in the micro display device 1100 shown in FIGS. 11 and 12 , the drive circuit DRV is disposed on the side of the display panel chip DPC, so that heat dissipation and the drive circuit can be easily designed.

Accordingly, the micro display device 1100 of FIGS. 11 and 12 includes at least one gate driving chip (GDVC) including at least one gate driving circuit among the display panel chip (DPC) and a plurality of gate driving circuits, and a plurality of source driving circuits. and at least one source driving chip (SDVC) including at least one source driving circuit of the circuitry.

Here, at least one gate driving chip GDVC and at least one source driving chip SDVC constitute a driving circuit DRV.

Also, at least one gate driving chip GDVC may be disposed on a side surface of the display panel chip DPC in the first direction where a plurality of gate lines extend, and the at least one source driving chip may be disposed on a side surface of the display panel chip DPC. ) may be disposed on a side surface in the second direction from which the plurality of source lines extend.

Here, the driving circuit (DRV) is separated into at least one gate driving chip (GDVC) and at least one source driving chip (SDVC), and is divided into a first direction side and a second direction side of the display panel chip (DPC), respectively. The arrangement is to easily drive the plurality of gate lines GL and the plurality of data lines DL and to increase yield by reducing the size of individual chips.

Meanwhile, at least one gate driving chip GDVC and at least one source driving chip SDVC may include a plurality of pads or a plurality of through electrodes, and may be electrically connected to the display panel chip DPC.

In FIG. 12, for example, at least one gate driving chip (GDVC) and at least one source driving chip (SDVC) are shown as being connected to the display panel chip (DPC) through a plurality of pads and wires. The pads and wires of can be replaced with multiple through electrodes.

As shown in FIG. 12 , in order to connect the through electrode of the display panel chip DPC to the through electrode of the display panel chip DPC, the pad or through electrode of the at least one gate driving chip GDVC and the at least one source driving chip SDVC is connected. Similar to the micro display device 900, an interposer ITP in which a plurality of driving redistribution lines DVRDL are disposed may be further included.

The plurality of drive redistribution lines (DVRDL) may include a plurality of gate drive redistribution lines (GDVRDL) and a plurality of data drive redistribution lines (DDVRDL).

The plurality of gate driving redistribution lines (GDVRDL) connect at least one gate driving chip (GDVC) and the plurality of gate lines of the pixel array unit (PXLU) through through electrodes, and the plurality of data driving redistribution lines (DDVRDL) Connects at least one source driving chip SDVC and a plurality of source lines of the pixel array unit PXLU through silver through electrodes.

It may also include a plurality of gate/data redistribution lines (GDRLD) of the interposer (ITP).

Among the plurality of gate/data redistribution lines GDRLD, the plurality of gate redistribution lines GDRL are the plurality of gate lines of the plurality of pixel array units PXLUs disposed adjacent to each other in the first direction. connect them electrically

Also, among the plurality of gate/data redistribution lines GDRLD, the plurality of data redistribution lines SDRL are used to transmit data of the pixel array units PXLUs disposed adjacent to each other in the second direction among the plurality of pixel array units PXLUs. Connect the lines electrically.

Connecting the plurality of gate lines GL and the plurality of data lines DL of the pixel array units PXLUs in which the plurality of gate redistribution lines GDRL and the plurality of data redistribution lines SDRL are disposed adjacent to each other is At least one gate driving chip (GDVC) and at least one source driving chip (SDVC) disposed separately on the first and second direction sides of the display panel chip (DPC) constitute a plurality of pixel array units (PXLU). This is to enable a display panel chip (DPC) including a to be driven in the same manner as a single display device.

Unlike the micro display devices 600, 900, and 1000 of FIGS. 6, 9, and 10 in which a plurality of pixel array units PXLUs and driving circuits DRV are vertically stacked, the micro display device shown in FIG. 11 1100 has a structure in which it is difficult for at least one gate driving chip GDVC and at least one source driving chip SDVC to individually drive a plurality of pixel array units PXLU.

Accordingly, as shown in FIGS. 11 and 12 , when a plurality of gate lines GL and a plurality of data lines DL of adjacent pixel array units PXLUs are interconnected, each of the plurality of pixel array units PXLUs The display panel chip (DPC) can be driven in the same way as a single display device without distinction.

And as shown in FIG. 11 , the micro display device 1100 may further include an integrated controller CONT for controlling at least one gate driving chip GDVC and at least one source driving chip SDVC. .

Here, the integrated controller CONT may be implemented as a control chip manufactured on a silicon substrate or as a separate external circuit.

When the integrated controller CONT is implemented as a control chip, the control chip, like at least one gate driving chip GDVC and at least one source driving chip SDVC, may be disposed on the interposer ITP.

In this case, the interposer ITP may further include a control redistribution line electrically connecting the at least one gate driving chip GDVC and the at least one source driving chip SDVC to the control chip.

However, the control chip may be implemented as a separate semiconductor package.

As a result, the micro display device according to embodiments of the present invention can easily provide a large screen and high-resolution image by sawing a plurality of pixel array units (PXLU) in groups to obtain a display panel chip (DPC). there is.

In addition, micro display devices of various sizes and resolutions can be manufactured at low cost.

The above description and accompanying drawings are merely illustrative of the technical idea of the present invention, and those skilled in the art can combine the configuration within the scope not departing from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, and the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: organic light emitting display device
PXL: pixel array
GDC: gate driving circuit
SDC: source driving circuit
CONT: Controller
200: micro display device
PAZ: Pixel Array Zone
CZ: circuit zone
PXLU: Pixel Array Unit

Claims (16)

A display panel chip including M*N pixel array units in which a plurality of subpixels defined by a plurality of gate lines and a plurality of data lines are arranged, the display panel chip being connected to the plurality of gate lines and the display panel chip further comprising a plurality of gate through-electrodes penetrating the panel chip and a plurality of data through-electrodes connected to the plurality of data lines and penetrating the display panel chip; and
Provided separately from the display panel chip,
at least two connection ports disposed in alignment with the plurality of gate through-electrodes and the plurality of data through-electrodes and implemented with at least one of a conductive bump, a soda ball, or a conductive spacer; any one of the at least two connection ports and the plurality of at least one gate driving circuit for driving the plurality of gate lines through a gate through electrode, and at least one driving the plurality of data lines through the other one of at least two connection ports and the plurality of data through electrodes. A driving circuit unit including a source driving circuit;
The display panel chip
A micro display device in which M * N pixel array units are arranged corresponding to at least one of a predetermined size or resolution. According to claim 1,
The display panel chip,
A micro display device obtained by sawing a plurality of pixel array units manufactured on a silicon wafer in units of M*N groups. According to claim 1,
The plurality of pixel array units,
a pixel array area in which the plurality of sub-pixels are arranged; and
and a through area in which the plurality of gate through electrodes and the plurality of data through electrodes are disposed in an outer area of the pixel array area. According to claim 3,
The at least one gate driving circuit includes a plurality of gate driving circuits,
The at least one source driving circuit includes a plurality of source driving circuits. According to claim 4,
The driving circuit part,
and M*N driving chips including the at least one gate driving circuit and the at least one source driving circuit, wherein the M*N driving chips are disposed below the display panel chip. According to claim 5,
Each of the M * N driving chips,
and at least one controller controlling the at least one gate driving circuit and the at least one source driving circuit. According to claim 6,
The driving circuit part,
The micro display further includes an integrated controller that receives input image data, divides the received input image data into M*N divided image data for each region, and transfers the received input image data to the controller included in each of the M*N driving chips. Device. According to claim 5,
The driving circuit part,
Receiving input image data, dividing the received input image data into M*N divided image data for each region, and the at least one gate driving circuit of each of the M*N driving chips according to the divided image data; A micro display device further comprising an integrated controller controlling at least one source driving circuit. According to claim 4,
The micro display device,
Further comprising an active interposer disposed under the display panel chip,
The active interposer,
The plurality of gate driving circuits and the plurality of source driving circuits are disposed, the plurality of gate driving circuits are electrically connected to the plurality of gate through-electrodes, and the plurality of source passive circuits and the plurality of data through-electrodes are electrically connected. A micro display device including a plurality of redistribution lines electrically connected to each other. According to claim 9,
The active interposer,
The micro display device further comprises an integrated controller controlling the plurality of gate driving circuits and the plurality of source driving circuits. According to claim 4,
The micro display device,
Further comprising a passive interposer disposed under the display panel,
The passive interposer,
A plurality of gate redistribution lines electrically connecting a plurality of gate through electrodes of the pixel array units arranged adjacent to each other among the M * N pixel array units, and a plurality of gate redistribution lines electrically connecting a plurality of data through electrodes to each other. A micro display device comprising a data redistribution line. According to claim 10,
The driving circuit part,
at least one gate driving chip including the at least one gate driving circuit; and
A micro display device comprising at least one source driving chip including the at least one source driving circuit. According to claim 12,
The at least one gate driving chip,
disposed in a first direction in which the plurality of gate lines extend from the display panel chip;
The at least one source driving chip,
A micro display device disposed on a side in a second direction in which the plurality of source lines extend from the display panel chip. According to claim 11,
The passive interposer,
a gate drive redistribution line electrically connecting a plurality of gate through-electrodes of the pixel array unit disposed at an outermost side of the M*N pixel array units in a first direction and the at least one gate driving chip; and
and a data drive redistribution line electrically connecting a plurality of data through electrodes of a pixel array unit disposed at an outermost side of the M*N pixel array units in a second direction and the at least one source driving chip. display device. According to claim 14,
The driving circuit part,
a control chip controlling the at least one gate driving chip and the at least one source driving chip;
The passive interposer,
and a control redistribution line electrically connecting the at least one gate driving chip and the at least one source driving chip to the control chip. It includes M * N pixel array units in which a plurality of subpixels each defined by a plurality of gate lines and a plurality of data lines are arranged;
The pixel array unit,
a plurality of gate through electrodes connected to the plurality of gate lines and penetrating the pixel array unit, and a plurality of data through electrodes connected to the plurality of data lines and penetrating the pixel array unit;
The M * N pixel array units,
M * N pixel array units corresponding to at least one of a predetermined size or resolution among a plurality of pixel array units on the silicon wafer are sawed in groups,
the pixel array unit;
at least two connection ports provided separately from the pixel array unit, arranged in alignment with the plurality of gate through-electrodes and the plurality of data through-electrodes, and realized with at least one of a conductive bump, a sodder ball, or a conductive spacer; at least one gate driving circuit for driving the plurality of gate lines through one of two connection ports and the plurality of gate through-electrodes; and the other one of at least two connection ports and the plurality of data through-electrodes. A driving circuit unit including at least one source driving circuit for driving a plurality of data lines,
The display integrated circuit electrically connected to each other through the plurality of gate through electrodes, the plurality of data through electrodes, and the at least two connection ports.

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