KR102507275B1 - Simd 게더 및 카피 동작들을 수행하기 위한 방법 및 장치 - Google Patents

Simd 게더 및 카피 동작들을 수행하기 위한 방법 및 장치 Download PDF

Info

Publication number
KR102507275B1
KR102507275B1 KR1020187036298A KR20187036298A KR102507275B1 KR 102507275 B1 KR102507275 B1 KR 102507275B1 KR 1020187036298 A KR1020187036298 A KR 1020187036298A KR 20187036298 A KR20187036298 A KR 20187036298A KR 102507275 B1 KR102507275 B1 KR 102507275B1
Authority
KR
South Korea
Prior art keywords
memory
processor
simd
copy
getter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020187036298A
Other languages
English (en)
Korean (ko)
Other versions
KR20190020672A (ko
Inventor
에릭 웨인 마후린
자쿠브 파월 골라브
루시안 커드레스쿠
Original Assignee
퀄컴 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20190020672A publication Critical patent/KR20190020672A/ko
Application granted granted Critical
Publication of KR102507275B1 publication Critical patent/KR102507275B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043LOAD or STORE instructions; Clear instruction
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656Data buffering arrangements
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3005Arrangements for executing specific machine instructions to perform operations for flow control
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824Operand accessing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Mathematical Physics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
  • Display Devices Of Pinball Game Machines (AREA)
  • Image Processing (AREA)
KR1020187036298A 2016-06-24 2017-06-06 Simd 게더 및 카피 동작들을 수행하기 위한 방법 및 장치 Active KR102507275B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/192,992 2016-06-24
US15/192,992 US20170371657A1 (en) 2016-06-24 2016-06-24 Scatter to gather operation
PCT/US2017/036041 WO2017222798A1 (en) 2016-06-24 2017-06-06 Method and apparatus for performing simd gather and copy operations

Publications (2)

Publication Number Publication Date
KR20190020672A KR20190020672A (ko) 2019-03-04
KR102507275B1 true KR102507275B1 (ko) 2023-03-06

Family

ID=59054330

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020187036298A Active KR102507275B1 (ko) 2016-06-24 2017-06-06 Simd 게더 및 카피 동작들을 수행하기 위한 방법 및 장치

Country Status (8)

Country Link
US (1) US20170371657A1 (https=)
EP (1) EP3475808B1 (https=)
JP (1) JP7134100B2 (https=)
KR (1) KR102507275B1 (https=)
CN (1) CN109313548B (https=)
ES (1) ES2869865T3 (https=)
SG (1) SG11201810051VA (https=)
WO (1) WO2017222798A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10795678B2 (en) * 2018-04-21 2020-10-06 Microsoft Technology Licensing, Llc Matrix vector multiplier with a vector register file comprising a multi-port memory
US10782918B2 (en) * 2018-09-06 2020-09-22 Advanced Micro Devices, Inc. Near-memory data-dependent gather and packing
KR102811045B1 (ko) 2020-03-06 2025-05-21 삼성전자주식회사 데이터 버스, 그것의 데이터 처리 방법 및 데이터 처리 장치
US12443412B2 (en) 2022-01-30 2025-10-14 Simplex Micro, Inc. Method and apparatus for a scalable microprocessor with time counter
US12190116B2 (en) 2022-04-05 2025-01-07 Simplex Micro, Inc. Microprocessor with time count based instruction execution and replay
US12288065B2 (en) 2022-04-29 2025-04-29 Simplex Micro, Inc. Microprocessor with odd and even register sets
US12282772B2 (en) * 2022-07-13 2025-04-22 Simplex Micro, Inc. Vector processor with vector data buffer
US12541369B2 (en) 2022-07-13 2026-02-03 Simplex Micro, Inc. Executing phantom loops in a microprocessor
US12566609B2 (en) 2023-03-14 2026-03-03 Simplex Micro, Inc. Microprocessor with apparatus and method for handling of instructions with long throughput
US12566610B2 (en) 2023-03-14 2026-03-03 Simplex Micro, Inc. Microprocessor with apparatus and method for replaying load instructions
US12566613B2 (en) 2023-11-13 2026-03-03 Simplex Micro, Inc. Microprocessor with speculative and in-order register sets

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120151156A1 (en) * 2010-12-08 2012-06-14 International Business Machines Corporation Vector gather buffer for multiple address vector loads
US20140136811A1 (en) * 2012-11-12 2014-05-15 International Business Machines Corporation Active memory device gather, scatter, and filter

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761706A (en) * 1994-11-01 1998-06-02 Cray Research, Inc. Stream buffers for high-performance computer memory system
US5887183A (en) * 1995-01-04 1999-03-23 International Business Machines Corporation Method and system in a data processing system for loading and storing vectors in a plurality of modes
US6513107B1 (en) * 1999-08-17 2003-01-28 Nec Electronics, Inc. Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page
US7484062B2 (en) * 2005-12-22 2009-01-27 International Business Machines Corporation Cache injection semi-synchronous memory copy operation
US7454585B2 (en) * 2005-12-22 2008-11-18 International Business Machines Corporation Efficient and flexible memory copy operation
US8432409B1 (en) * 2005-12-23 2013-04-30 Globalfoundries Inc. Strided block transfer instruction
US8060724B2 (en) * 2008-08-15 2011-11-15 Freescale Semiconductor, Inc. Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor
US9218183B2 (en) * 2009-01-30 2015-12-22 Arm Finance Overseas Limited System and method for improving memory transfer
US20120060016A1 (en) * 2010-09-07 2012-03-08 International Business Machines Corporation Vector Loads from Scattered Memory Locations
US9626333B2 (en) * 2012-06-02 2017-04-18 Intel Corporation Scatter using index array and finite state machine
US8972697B2 (en) * 2012-06-02 2015-03-03 Intel Corporation Gather using index array and finite state machine
US9563425B2 (en) * 2012-11-28 2017-02-07 Intel Corporation Instruction and logic to provide pushing buffer copy and store functionality
JP6253514B2 (ja) * 2014-05-27 2017-12-27 ルネサスエレクトロニクス株式会社 プロセッサ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120151156A1 (en) * 2010-12-08 2012-06-14 International Business Machines Corporation Vector gather buffer for multiple address vector loads
US20140136811A1 (en) * 2012-11-12 2014-05-15 International Business Machines Corporation Active memory device gather, scatter, and filter

Also Published As

Publication number Publication date
EP3475808A1 (en) 2019-05-01
KR20190020672A (ko) 2019-03-04
EP3475808B1 (en) 2021-04-14
WO2017222798A1 (en) 2017-12-28
BR112018076270A2 (pt) 2019-03-26
JP2019525294A (ja) 2019-09-05
CN109313548A (zh) 2019-02-05
US20170371657A1 (en) 2017-12-28
CN109313548B (zh) 2023-05-26
ES2869865T3 (es) 2021-10-26
BR112018076270A8 (pt) 2023-01-31
SG11201810051VA (en) 2019-01-30
JP7134100B2 (ja) 2022-09-09

Similar Documents

Publication Publication Date Title
KR102507275B1 (ko) Simd 게더 및 카피 동작들을 수행하기 위한 방법 및 장치
US9678758B2 (en) Coprocessor for out-of-order loads
US9830156B2 (en) Temporal SIMT execution optimization through elimination of redundant operations
JP5698445B2 (ja) 多重プロセッサ・コア・ベクトル・モーフ結合機構
US8615646B2 (en) Unanimous branch instructions in a parallel thread processor
JP5209933B2 (ja) データ処理装置
US20150205590A1 (en) Confluence analysis and loop fast-forwarding for improving simd execution efficiency
JP7084379B2 (ja) ロードストアユニットをバイパスすることによるストア及びロードの追跡
TW201702866A (zh) 用戶等級分叉及會合處理器、方法、系統及指令
US9286114B2 (en) System and method for launching data parallel and task parallel application threads and graphics processing unit incorporating the same
JP2008226236A (ja) 構成可能なマイクロプロセッサ
US10120693B2 (en) Fast multi-width instruction issue in parallel slice processor
US11023242B2 (en) Method and apparatus for asynchronous scheduling
CN109564510B (zh) 用于在地址生成时间分配加载和存储队列的系统和方法
CN103294449B (zh) 发散操作的预调度重演
JP2022549493A (ja) リタイアキューの圧縮
US11093246B2 (en) Banked slice-target register file for wide dataflow execution in a microprocessor
JP2014191663A (ja) 演算処理装置、情報処理装置、および演算処理装置の制御方法
HK1260879A1 (en) Method and apparatus for performing simd gather and copy operations
CN116134418B (zh) 在处理器中的指令流水线中插入代理读取指令
US11119774B2 (en) Slice-target register file for microprocessor
US20090204787A1 (en) Butterfly Physical Chip Floorplan to Allow an ILP Core Polymorphism Pairing
US20140075140A1 (en) Selective control for commit lines for shadowing data in storage elements

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000