JP2019525294A - Simdの集中およびコピー動作を実行するための方法および装置 - Google Patents
Simdの集中およびコピー動作を実行するための方法および装置 Download PDFInfo
- Publication number
- JP2019525294A JP2019525294A JP2018566347A JP2018566347A JP2019525294A JP 2019525294 A JP2019525294 A JP 2019525294A JP 2018566347 A JP2018566347 A JP 2018566347A JP 2018566347 A JP2018566347 A JP 2018566347A JP 2019525294 A JP2019525294 A JP 2019525294A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- processor
- data elements
- result buffer
- centralized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000003860 storage Methods 0.000 claims description 8
- 239000012141 concentrate Substances 0.000 abstract description 3
- 238000012545 processing Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 7
- 230000009471 action Effects 0.000 description 6
- 230000007246 mechanism Effects 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012432 intermediate storage Methods 0.000 description 1
- 239000006249 magnetic particle Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Mathematical Physics (AREA)
- Advance Control (AREA)
- Image Processing (AREA)
- Executing Machine-Instructions (AREA)
- Memory System (AREA)
- Display Devices Of Pinball Game Machines (AREA)
Abstract
Description
102 プロセッサ
103 レジスタ
104 バス
106 トランザクション入力バッファ
108 バス
110 トランザクションシーケンサ
112 バス
114 メモリ
115 集中結果バッファ
120 連続メモリアクセス
122 スコアボード
400 コンピューティングデバイス
402 プロセッサ
422 システムオンチップデバイス
426 ディスプレイコントローラ
428 ディスプレイ
430 入力デバイス
432 メモリ
434 コーデック
436 スピーカー
438 マイクロフォン
440 ワイヤレスコントローラ
442 ワイヤレスアンテナ
444 電源
Claims (23)
- メモリ動作を行う方法であって、
プロセッサによって、メモリの2つ以上のソースアドレスを与えるステップと、
前記メモリ内の前記2つ以上のソースアドレスから集中結果バッファに2つ以上のデータ要素をコピーするステップと、
単一命令複数データ(SIMD)ロード動作を使用して、前記集中結果バッファから前記プロセッサ内のベクトルレジスタに前記2つ以上のデータ要素をロードするステップと
を含む、方法。 - 前記集中結果バッファが、前記メモリ内または前記メモリの極近傍にある、請求項1に記載の方法。
- 前記集中結果バッファが循環バッファである、請求項1に記載の方法。
- 前記2つ以上のソースアドレスが、前記メモリにおいて直交し、または独立し、不連続である、請求項1に記載の方法。
- 前記2つ以上のデータ要素を前記集中結果バッファにアウトオブオーダーにコピーするステップを含む、請求項1に記載の方法。
- 前記2つ以上のデータ要素を前記集中結果バッファにアウトオブオーダーにコピーするステップが、2つ以上の異なるレイテンシを伴う、請求項5に記載の方法。
- 前記プロセッサによる指示なしでバックグラウンドモードで、前記2つ以上のデータ要素を前記集中結果バッファにアウトオブオーダーにコピーするステップを含む、請求項5に記載の方法。
- 前記集中結果バッファをトラッキングするステップと、前記集中結果バッファが完了した後、前記集中結果バッファから前記2つ以上のデータ要素をロードするステップとを含む、請求項5に記載の方法。
- メモリ動作を行う方法であって、
プロセッサによって、メモリの2つ以上のソースアドレスおよび対応する2つ以上の宛先アドレスを与えるステップと、
プロセッサ内のレジスタへの中間コピーなしで、前記メモリ内で前記2つ以上のソースアドレスから前記対応する2つ以上の宛先アドレスに2つ以上のデータ要素をコピーするための2つ以上の命令を実行するステップと
を含む、方法。 - 前記2つ以上のソースアドレスが直交し、または独立し、不連続である、請求項9に記載の方法。
- 前記2つ以上の宛先アドレスが、前記メモリにおいて直交し、または独立し、不連続である、請求項9に記載の方法。
- 前記メモリ内で前記2つ以上のソースアドレスから前記対応する2つ以上の宛先アドレスに前記2つ以上のデータ要素を前記コピーすることが、単一命令複数データ(SIMD)コピー命令を実行することを含む、請求項9に記載の方法。
- 前記プロセッサによる指示なしでバックグラウンドモードで前記SIMDコピー命令を実行するステップを含む、請求項12に記載の方法。
- 装置であって、
メモリの2つ以上のソースアドレスを与えるように構成されたプロセッサと、
前記メモリ内の前記2つ以上のソースアドレスからコピーされた2つ以上のデータ要素を受け取るように構成された集中結果バッファと、
前記プロセッサによって実行された単一命令複数データ(SIMD)ロード動作に基づいて、前記集中結果バッファから前記プロセッサ内のベクトルレジスタに前記2つ以上のデータ要素をロードするように構成された論理手段と
を含む、装置。 - 前記集中結果バッファが、前記メモリ内または前記メモリの極近傍にある、請求項14に記載の装置。
- 前記集中結果バッファが、前記2つ以上のデータ要素をアウトオブオーダーに受け取るように構成された循環バッファまたはストレージ構造である、請求項14に記載の装置。
- 前記2つ以上のソースアドレスが、前記メモリにおいて直交し、または独立し、不連続である、請求項14に記載の装置。
- 前記2つ以上のデータ要素が、前記プロセッサによる指示なしでバックグラウンドモードで、前記集中結果バッファにアウトオブオーダーにコピーされる、請求項14に記載の装置。
- 前記論理手段が、前記集中結果バッファを追跡し、前記集中結果バッファが完了するとき、ベクトル完了信号を生成するように構成されたトランザクションシーケンスを含む、請求項14に記載の装置。
- 装置であって、
メモリの2つ以上のソースアドレスおよび対応する2つ以上の宛先アドレスを与えるように構成されたプロセッサと、
プロセッサ内のレジスタへの中間コピーなしで、前記メモリ内で前記2つ以上のソースアドレスから前記対応する2つ以上の宛先アドレスに2つ以上のデータ要素をコピーするように構成された論理手段と
を含む、装置。 - 前記2つ以上のソースアドレスが直交し、または独立し、不連続である、請求項20に記載の装置。
- 前記2つ以上の宛先アドレスが、前記メモリにおいて直交し、または独立し、不連続である、請求項20に記載の装置。
- 前記プロセッサによる指示なしでバックグラウンドモードで、前記2つ以上のソースアドレスから前記対応する2つ以上の宛先アドレスに前記2つ以上のデータ要素をコピーするように構成された論理手段を含む、請求項20に記載の装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/192,992 | 2016-06-24 | ||
US15/192,992 US20170371657A1 (en) | 2016-06-24 | 2016-06-24 | Scatter to gather operation |
PCT/US2017/036041 WO2017222798A1 (en) | 2016-06-24 | 2017-06-06 | Method and apparatus for performing simd gather and copy operations |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2019525294A true JP2019525294A (ja) | 2019-09-05 |
JP2019525294A5 JP2019525294A5 (ja) | 2020-07-02 |
JP7134100B2 JP7134100B2 (ja) | 2022-09-09 |
Family
ID=59054330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018566347A Active JP7134100B2 (ja) | 2016-06-24 | 2017-06-06 | Simdの集中およびコピー動作を実行するための方法および装置 |
Country Status (9)
Country | Link |
---|---|
US (1) | US20170371657A1 (ja) |
EP (1) | EP3475808B1 (ja) |
JP (1) | JP7134100B2 (ja) |
KR (1) | KR102507275B1 (ja) |
CN (1) | CN109313548B (ja) |
BR (1) | BR112018076270A8 (ja) |
ES (1) | ES2869865T3 (ja) |
SG (1) | SG11201810051VA (ja) |
WO (1) | WO2017222798A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10795678B2 (en) * | 2018-04-21 | 2020-10-06 | Microsoft Technology Licensing, Llc | Matrix vector multiplier with a vector register file comprising a multi-port memory |
US10782918B2 (en) * | 2018-09-06 | 2020-09-22 | Advanced Micro Devices, Inc. | Near-memory data-dependent gather and packing |
KR20210112949A (ko) | 2020-03-06 | 2021-09-15 | 삼성전자주식회사 | 데이터 버스, 그것의 데이터 처리 방법 및 데이터 처리 장치 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007172609A (ja) * | 2005-12-22 | 2007-07-05 | Internatl Business Mach Corp <Ibm> | 効率的かつ柔軟なメモリ・コピー動作 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5887183A (en) * | 1995-01-04 | 1999-03-23 | International Business Machines Corporation | Method and system in a data processing system for loading and storing vectors in a plurality of modes |
US6513107B1 (en) * | 1999-08-17 | 2003-01-28 | Nec Electronics, Inc. | Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page |
US7484062B2 (en) * | 2005-12-22 | 2009-01-27 | International Business Machines Corporation | Cache injection semi-synchronous memory copy operation |
US8432409B1 (en) * | 2005-12-23 | 2013-04-30 | Globalfoundries Inc. | Strided block transfer instruction |
US8060724B2 (en) * | 2008-08-15 | 2011-11-15 | Freescale Semiconductor, Inc. | Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor |
US9218183B2 (en) * | 2009-01-30 | 2015-12-22 | Arm Finance Overseas Limited | System and method for improving memory transfer |
US20120060016A1 (en) * | 2010-09-07 | 2012-03-08 | International Business Machines Corporation | Vector Loads from Scattered Memory Locations |
US8635431B2 (en) * | 2010-12-08 | 2014-01-21 | International Business Machines Corporation | Vector gather buffer for multiple address vector loads |
US9626333B2 (en) * | 2012-06-02 | 2017-04-18 | Intel Corporation | Scatter using index array and finite state machine |
US8972697B2 (en) * | 2012-06-02 | 2015-03-03 | Intel Corporation | Gather using index array and finite state machine |
US10049061B2 (en) * | 2012-11-12 | 2018-08-14 | International Business Machines Corporation | Active memory device gather, scatter, and filter |
US9563425B2 (en) * | 2012-11-28 | 2017-02-07 | Intel Corporation | Instruction and logic to provide pushing buffer copy and store functionality |
-
2016
- 2016-06-24 US US15/192,992 patent/US20170371657A1/en active Pending
-
2017
- 2017-06-06 BR BR112018076270A patent/BR112018076270A8/pt unknown
- 2017-06-06 SG SG11201810051VA patent/SG11201810051VA/en unknown
- 2017-06-06 EP EP17729733.0A patent/EP3475808B1/en active Active
- 2017-06-06 CN CN201780035161.6A patent/CN109313548B/zh active Active
- 2017-06-06 ES ES17729733T patent/ES2869865T3/es active Active
- 2017-06-06 JP JP2018566347A patent/JP7134100B2/ja active Active
- 2017-06-06 WO PCT/US2017/036041 patent/WO2017222798A1/en unknown
- 2017-06-06 KR KR1020187036298A patent/KR102507275B1/ko active IP Right Grant
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007172609A (ja) * | 2005-12-22 | 2007-07-05 | Internatl Business Mach Corp <Ibm> | 効率的かつ柔軟なメモリ・コピー動作 |
Also Published As
Publication number | Publication date |
---|---|
US20170371657A1 (en) | 2017-12-28 |
CN109313548A (zh) | 2019-02-05 |
EP3475808A1 (en) | 2019-05-01 |
JP7134100B2 (ja) | 2022-09-09 |
BR112018076270A2 (pt) | 2019-03-26 |
CN109313548B (zh) | 2023-05-26 |
SG11201810051VA (en) | 2019-01-30 |
WO2017222798A1 (en) | 2017-12-28 |
ES2869865T3 (es) | 2021-10-26 |
BR112018076270A8 (pt) | 2023-01-31 |
KR20190020672A (ko) | 2019-03-04 |
KR102507275B1 (ko) | 2023-03-06 |
EP3475808B1 (en) | 2021-04-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8135941B2 (en) | Vector morphing mechanism for multiple processor cores | |
US8615646B2 (en) | Unanimous branch instructions in a parallel thread processor | |
US9830156B2 (en) | Temporal SIMT execution optimization through elimination of redundant operations | |
US9678758B2 (en) | Coprocessor for out-of-order loads | |
US9612811B2 (en) | Confluence analysis and loop fast-forwarding for improving SIMD execution efficiency | |
TW201702866A (zh) | 用戶等級分叉及會合處理器、方法、系統及指令 | |
JP7084379B2 (ja) | ロードストアユニットをバイパスすることによるストア及びロードの追跡 | |
US8572355B2 (en) | Support for non-local returns in parallel thread SIMD engine | |
US10761851B2 (en) | Memory apparatus and method for controlling the same | |
JP2017107587A (ja) | 複数のビットを左にシフトし、複数の1を複数の下位ビットにプルインするための命令 | |
JP7134100B2 (ja) | Simdの集中およびコピー動作を実行するための方法および装置 | |
US10489155B2 (en) | Mixed-width SIMD operations using even/odd register pairs for wide data elements | |
US20130339689A1 (en) | Later stage read port reduction | |
JP2017045151A (ja) | 演算処理装置及び演算処理装置の制御方法 | |
US11023242B2 (en) | Method and apparatus for asynchronous scheduling | |
US7047397B2 (en) | Method and apparatus to execute an instruction with a semi-fast operation in a staggered ALU | |
US11093246B2 (en) | Banked slice-target register file for wide dataflow execution in a microprocessor | |
TWI587137B (zh) | 經改良之單一指令多重資料(simd)的k最近鄰居法之實施技術 | |
WO2014202825A1 (en) | Microprocessor apparatus | |
CN109564510A (zh) | 用于在地址生成时间分配加载和存储队列的系统和方法 | |
US11609764B2 (en) | Inserting a proxy read instruction in an instruction pipeline in a processor | |
JP2011060048A (ja) | 情報処理装置、情報処理方法及び情報処理プログラム | |
US20090204792A1 (en) | Scalar Processor Instruction Level Parallelism (ILP) Coupled Pair Morph Mechanism | |
US20190087521A1 (en) | Stochastic dataflow analysis for processing systems | |
JP2015191463A (ja) | 演算処理装置及び演算処理装置の制御方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200518 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20200518 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20210528 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20210614 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20210914 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20211004 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220104 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20220124 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220524 |
|
C60 | Trial request (containing other claim documents, opposition documents) |
Free format text: JAPANESE INTERMEDIATE CODE: C60 Effective date: 20220524 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20220601 |
|
C21 | Notice of transfer of a case for reconsideration by examiners before appeal proceedings |
Free format text: JAPANESE INTERMEDIATE CODE: C21 Effective date: 20220606 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220808 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220830 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7134100 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |