KR102502234B1 - Programming method of a non volatile memory device - Google Patents

Abstract

A method of programming a non-volatile memory device is disclosed. A programming method of a nonvolatile memory device according to an embodiment of the present disclosure includes programming memory cells based on a first program voltage set to program at least some of the memory cells to a target state; dividing the memory cells into a plurality of cell groups having different threshold voltage distribution widths based on program speeds of the memory cells determined according to the threshold voltage distribution of the memory cells; Based on a plurality of secondary program voltages set based on differences in threshold voltages between the plurality of cell groups, other cell groups other than the first cell group programmed to the target state among the plurality of cell groups are brought into the target state. Including reprogramming.

Description

Programming method of a non volatile memory device

The technical concept of the present disclosure relates to a semiconductor device, and more specifically, to a method for programming a non-volatile memory device.

Memory devices are used to store data and are classified into volatile memory devices and non-volatile memory devices. As an example of a non-volatile memory device, a flash memory device may be used in a mobile phone, a digital camera, a personal digital assistant (PDA), a mobile computer device, a stationary computer device, and other devices.

An object to be solved by the technical idea of the present disclosure is to provide a non-volatile memory device and a method for programming the non-volatile memory device capable of improving program speed and reducing the width of threshold voltage distribution of memory cells in a programmed state. .

In order to achieve the above technical problem, a method for programming a non-volatile memory device including memory cells storing multi-bit data according to an embodiment of the present disclosure includes a first program set to program at least some of the memory cells to a target state. programming the memory cells based on voltage; dividing the memory cells into a plurality of cell groups having different threshold voltage distribution widths based on program speeds of the memory cells determined according to the threshold voltage distribution of the memory cells; and other cell groups other than the first cell group programmed to the target state among the plurality of cell groups based on a plurality of secondary program voltages set based on differences in threshold voltages between the plurality of cell groups. It includes reprogramming to

A programming method of a nonvolatile memory device according to another embodiment of the present disclosure for achieving the above technical problem includes programming memory cells to an N−1th state (N is an integer greater than or equal to 2); detecting a program speed of a word line connected to the memory cells; adjusting a voltage level of an Nth program voltage set corresponding to an Nth state based on the detected program speed of the word line; and programming at least some of the memory cells to the Nth state based on the Nth program voltage set, wherein the programming of the memory cells to the N−1th state comprises: Based on the threshold voltage distribution of memory cells according to the first program voltage, the memory cells are divided into a plurality of cell groups having different threshold voltage ranges according to the program speed, and some of the plurality of cell groups have the A plurality of secondary program voltages set based on differences in threshold voltages of the plurality of cell groups may be applied.

In order to achieve the above technical problem, a method for programming a non-volatile memory device including memory cells storing multi-bit data according to another embodiment of the present disclosure includes memory cells of an n-th (n is an integer) word line as the n programming based on a first program voltage corresponding to a th word line; programming memory cells of an n+1 th word line based on a first program voltage corresponding to the n+1 th word line; and classifying the memory cells of the n-th word line into a plurality of cell groups according to program speeds, and based on a plurality of secondary program voltages set based on a threshold voltage difference between the plurality of cell groups, and reprogramming memory cells of a word line to the target state.

According to a method for programming a non-volatile memory device according to technical features of the present disclosure, memory cells are divided into a plurality of cell groups according to program speeds based on threshold voltage distribution of one-shot memory cells, and different threshold voltage distributions are obtained. It takes time to program data into a memory cell array by programming each cell group based on program voltages set based on a threshold voltage difference between the plurality of cell groups so that each cell group having a width is programmed to a target state. time and the width of the threshold voltage distribution of each program state may be reduced.

In addition, according to the method of programming a nonvolatile memory device according to the technical idea of the present disclosure, before programming memory cells in respective program states, a program speed for each word line is checked, and a compensation voltage according to the program speed is set to a program voltage. The width of the threshold voltage distribution of each program state programmed into the memory cell array can be reduced by reflecting the .

In addition, according to the method of programming a nonvolatile memory device according to the technical concept of the present disclosure, when performing programming on memory cells of one word line, each word line is programmed for the word line and word lines adjacent to the word line. After performing the first program by applying the corresponding first program voltage, and then performing the second program on the memory cells of the word line based on the threshold voltage distribution of the one-shot memory cell of the word line, the word It is possible to prevent a shift in threshold voltage distribution of each program state due to an inter-line coupling effect.

In order to more fully understand the drawings cited in the detailed description of the present disclosure, a brief description of each drawing is provided.
1 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure.
2 is a circuit diagram illustrating an example of a memory block according to an exemplary embodiment of the present disclosure.
3 is a circuit diagram illustrating another example of a memory block according to an exemplary embodiment of the present disclosure.
FIG. 4 is a perspective view illustrating a memory block according to the circuit diagram of FIG. 3 .
5A and 5B are views illustrating an operating method of a memory device according to an exemplary embodiment of the present disclosure.
6 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.
7A and 7B are graphs illustrating distribution of memory cells according to setting threshold voltage ranges of cell groups.
8(a) to (d) are graphs showing an example of a program method step by step according to an embodiment of the present disclosure.
FIG. 9 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG. 8 .
10 is a diagram illustrating a program method according to an embodiment of the present disclosure in more detail.
11 (a) to (c) are graphs showing an example of a program method step by step according to an embodiment of the present disclosure.
FIG. 12 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG. 11 .
13 is a diagram illustrating a program method according to an embodiment of the present disclosure in more detail.
14A and 14B are views illustrating an operating method of a memory device according to an exemplary embodiment of the present disclosure.
15 (a) to (f) are graphs showing an example of a program method step by step according to an embodiment of the present disclosure.
FIG. 16 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG. 15 .
17 (a) to (d) are graphs showing an example of a program method step by step according to an embodiment of the present disclosure.
FIG. 18 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG. 17 .
19 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.
20 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.
21 shows threshold voltage distribution of memory cells according to each program state.
22 is a waveform illustrating a voltage pulse applied to a word line as an example of a method of operating a memory device according to an embodiment of the present disclosure.
23 is a waveform illustrating a voltage pulse applied to a word line as an example of a method of operating a memory device according to an embodiment of the present disclosure.
24 is a flowchart illustrating another example of a program method according to an embodiment of the present disclosure.
25A to 25C are graphs showing the distribution of threshold voltages of word lines according to each step in the flowchart of FIG. 24 .
26A and 26B are diagrams illustrating an initial programming step and a later programming step for memory cells of a word line.
27 is a flowchart illustrating another example of a program method according to an embodiment of the present disclosure.
28 illustrates a method of programming a memory cell array according to an embodiment of the present disclosure.
29 is a graph showing program speed for each word line.
30 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.
31 is a diagram explaining a method of detecting a program speed of a word line and compensating for a program voltage level according to an embodiment of the present disclosure.
32 is a diagram illustrating a method of setting a program voltage level by reflecting a program speed of a word line according to an embodiment of the present disclosure.
33A to 33C are graphs illustrating threshold voltage distributions of word lines in each step of a program method according to an embodiment of the present disclosure.
34 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.
35 is a diagram illustrating a method of detecting a program speed of a word line during program execution.
36 illustrates an embodiment of a method of operating a memory device according to an embodiment of the present disclosure.
37 is a flowchart illustrating in detail a method of operating a memory device according to an exemplary embodiment of the present disclosure.
38 is a block diagram illustrating an example of a program control unit according to an embodiment of the present disclosure.
39 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
40 is a block diagram illustrating a memory card system according to an exemplary embodiment of the present disclosure.
41 is a block diagram illustrating a computing system according to an embodiment of the present disclosure.
42 is a block diagram illustrating an SSD system according to an embodiment of the present disclosure.
43 is a block diagram illustrating a uiversal flash storage (UFS) according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Since the present invention can have various changes and various forms, specific embodiments are illustrated in the drawings and described in detail. However, it should be understood that this is not intended to limit the present invention to the specific disclosed form, and includes all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing each figure, like reference numbers are used for like elements. In the accompanying drawings, the dimensions of the structures are shown enlarged or reduced than actual for clarity of the present invention.

Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, terms such as "comprise" or "have" are intended to designate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, but one or more other features It should be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Also, terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the present invention.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the related art, and unless explicitly defined in this application, it should not be interpreted in an ideal or excessively formal meaning. don't

1 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , a memory device 100 may include a memory cell array 110 , a row decoder 120 , an input/output circuit 130 , a voltage generator 140 and a control logic 150 . The memory device 100 may be a non-volatile memory device including non-volatile memory cells.

The memory cell array 110 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. Hereinafter, embodiments will be described in detail taking a case in which the plurality of memory cells are NAND flash memory cells as an example. However, the technical spirit of the present disclosure is not limited thereto, and in another embodiment, the plurality of memory cells may be resistive memory cells such as resistive RAM (RRAM), phase change RAM (PRAM), or magnetic RAM (MRAM). .

In one embodiment, memory cell array 110 may be a three-dimensional (3D) memory cell array. A three-dimensional memory cell array is monolithically formed on at least one physical level of memory cell arrays having an active region disposed over a silicon substrate and circuitry associated with operation of the memory cells formed on or within the substrate. do. The term "monolithic" means that the layers of each level of the array are stacked directly on top of the layers of each lower level of the array. The 3D memory cell array includes NAND strings arranged in a vertical direction such that at least one memory cell is positioned above another memory cell. The at least one memory cell may include a charge trap layer. However, it is not limited thereto, and in another embodiment, the memory cell array 110 It may be a two-dimensional memory cell array.

In this embodiment, each memory cell included in the memory cell array 110 may be a multi-level cell (MLC) that stores data of 2 bits or more. For example, the memory cell may be a multi-level cell (MLC) that stores 2-bit data. As another example, the memory cell may be a triple level cell (TLC) that stores 3-bit data. However, the present disclosure is not limited thereto, and in another embodiment, some memory cells included in the memory cell array 110 are single level cells (SLCs) that store 1-bit data, and some other memory cells may be multi-level cells (MLC).

The memory cell array 110 includes a plurality of memory cells and may be connected to word lines WL, string select lines SSL, ground select lines GSL, and bit lines BL. Specifically, the memory cell array 110 is connected to the row decoder 120 through word lines WL or select lines SSL and GSL, and is connected to the input/output circuit 130 through bit lines BL. can

The memory cell array 110 may include a plurality of memory blocks BL1 to BLKi. The plurality of memory blocks BLK1 to BLKi may include at least one of a single-level cell block including single-level cells, a multi-level cell block including multi-level cells, and a triple-level cell block including triple-level cells. . Some of the plurality of memory blocks included in the memory cell array 110 may be single-level cell blocks, and other blocks may be multi-level cell blocks or triple-level cell blocks.

When an erase voltage is applied to the memory cell array 110, a plurality of memory cells are in an erase state, and when a program voltage is applied to the memory cell array 110, a plurality of memory cells are in a program state. In this case, each memory cell may have an erase state (E) and at least one program state classified according to a threshold voltage (Vth).

In one embodiment, when the memory cell is a single-level cell, the memory cell may have an erase state and a program state. In another embodiment, when the memory cell is a multi-level cell, the memory cell may have an erase state and at least three program states.

In this embodiment, memory cells may be divided into a plurality of cell groups according to programming speeds and programmed.

For example, memory cells are programmed based on a preset primary program voltage corresponding to a program state, and then the program speed is determined based on a Gaussian-type threshold voltage distribution of the memory cells (hereinafter referred to simply as distribution). It can be divided into three cell groups according to Thereafter, cell groups other than the first cell group corresponding to the uppermost region of the distribution of memory cells among the three cell groups may be reprogrammed to the programmed state based on the plurality of secondary program voltages. In this case, the plurality of secondary program voltages may be preset according to the distribution of one-shot memory cells and the primary program voltage.

In one embodiment, the first cell group is programmed at the fastest speed among the three cell groups, and the distribution of the first cell group may be included in the target distribution of programmed states.

In one embodiment, a threshold voltage range of a cell group corresponding to a middle region of the distribution of memory cells may be narrower than that of other cell groups.

During one program cycle including these steps, the memory cells may be programmed into one of a plurality of program states. Memory cells may be programmed into a plurality of program states during a plurality of program cycles. For example, when a memory cell is a multi-bit cell storing 2-bit data, the memory cell may have three program states, and each of a plurality of memory cells is programmed into one of the three program states during three program cycles. It can be.

The row decoder 120 may select some word lines from among the word lines WL in response to the row address X-ADDR. The row decoder 120 transfers the word line voltage to the word line. During a program operation, the row decoder 120 may apply a program voltage and a verify voltage to a selected word line and a program inhibit voltage to an unselected word line (Unselected WL). For example, during a read operation, the row decoder 120 may apply a read voltage to a selected word line and a read inhibit voltage to an unselected word line. Also, the row decoder 120 may select some string selection lines among the string selection lines SSL or some ground selection lines among the ground selection lines GSL in response to the row address X-ARRD.

The input/output circuit 130 receives data from the outside (eg, a memory controller) and stores the input data in the memory cell array 110 . Also, the input/output circuit 130 may read data from the memory cell array 110 and output the read data to the outside. The input/output circuit 130 may include page buffers (not shown) corresponding to the bit lines BL. The page buffer may be connected to the memory cell array 110 through bit lines BL, and some of the bit lines BL in response to the column address Y-ADDR received from the control logic 150. can choose During the program operation, the page buffer operates as a write driver to program data DATA to be stored in the memory cell array 110 .

The voltage generator 140 may generate various types of voltages for performing program, read, and erase operations on the memory cell array 110 based on the voltage control signal CTRL_vol. Specifically, the voltage generator 140 may generate a word line voltage, eg, a program voltage (or write voltage), a read voltage, a pass voltage (or a word line unselect voltage), or a verify voltage. The voltage generator 140 may generate a bit line voltage, eg, a bit line forcing voltage or an inhibit voltage. Also, the voltage generator 140 may further generate a string selection line voltage and a ground selection line voltage based on the voltage control signal CTRL_vol.

The control logic 150 writes data into the memory cell array 110 or writes data to the memory cell array 110 based on the command CMD, address ADDR, and control signal CTRL received from the memory controller (200 in FIG. 1). Various control signals for reading data from the array 110 may be output. Accordingly, the control logic 150 may control various operations within the memory device 100 as a whole.

Various control signals output from the control logic 150 may be provided to the voltage generator 140 , the row decoder 120 , and the input/output circuit 130 . Specifically, the control logic 150 may provide a voltage control signal CTRL_vol to the voltage generator 140, may provide a row address X-ADDR to the row decoder 120, and an input/output circuit ( 130) may be provided with a column address (Y-ADDR). However, the present disclosure is not limited thereto, and the control logic 150 may further provide other control signals to the voltage generator 140 , the row decoder 120 , and the input/output circuit 130 .

The control logic 150 may include a program controller 160 for controlling a program for the memory cell array 110 according to a program sequence according to the programming method of the present disclosure.

The program controller 160 may control a program operation of the memory device 100 . In an embodiment, the program controller 160 may set voltage levels of a plurality of driving voltages corresponding to each of a plurality of program states. The plurality of driving voltages may include program voltages corresponding to each of a plurality of program states, verification voltages, offset voltages, compensation voltages according to a program speed of a word line, and the like.

In an embodiment, the program controller 160 may apply a test program voltage to the memory cell array 110 and determine a Gaussian-shaped threshold voltage distribution of memory cells based on at least one read voltage. The program control unit 160 generates control signals for dividing memory cells to be programmed into groups according to program speeds during a program operation based on the distribution of threshold voltages of the memory cells, for example, at least one verify voltage, and during a verify read operation, sensing You can set the time, signal, etc. In addition, the program control unit 160 may set the voltage level of a program voltage set (eg, a first program voltage and a plurality of second program voltages) corresponding to each program state.

In an embodiment, the program control unit 160 detects the program speed of each word line before programming the memory cells to each program state, eg, when the program of the previous state is executed, and compensates for each word line according to the program speed. voltage can be set. Also, when setting the program voltage for each program state, the program control unit 160 may adjust the voltage level of the program voltage based on the compensation voltage and the program voltage of the previous state.

In an exemplary embodiment, the program controller 160 may control a program sequence for each word line of the memory cell array 110 . When programming is performed on memory cells of one word line, the program control unit 160 performs the first program on the memory cells of the word line based on the first program voltage, and performs the first program on the memory cells where the first program is performed. Cells may be divided into a plurality of cell groups according to program speeds, and secondary programming may be performed on the memory cells based on a plurality of secondary program voltages set based on differences in threshold voltages of the plurality of cell groups. At this time, the program control unit 160 performs a first program on the memory cells of one word line, performs a first program on an adjacent word line, and then performs a second program on the memory cells of the word line. By setting the program sequence to do so, the coupling effect between adjacent word lines can be prevented.

When performing a program, the memory device 100 according to this embodiment may program memory cells based on a preset program voltage corresponding to each of a plurality of program states. Also, the memory device 100 divides memory cells into a plurality of cell groups according to program speeds based on the threshold voltage distribution of the one-shot memory cells, and each of the plurality of cell groups having different threshold voltage distribution widths By programming each cell group based on program voltages set based on a difference in threshold voltages of the plurality of cell groups to be programmed to a target state, the same program number may be applied to each program state for programming. Accordingly, the program time of the memory device 100 may be reduced and the width of the threshold voltage distribution in each program state may be reduced.

In addition, the memory device 100 according to the present embodiment checks the program speed of memory cells for each word line before programming the memory cells to each program state, and reflects a compensation voltage according to the program speed to the program voltage. , the width of the threshold voltage distribution of each program state programmed into the memory cell array may be reduced.

In addition, when performing programming on memory cells of one word line, the memory device 100 according to the present embodiment performs a first program corresponding to each word line with respect to the word line and word lines adjacent to the word line. After performing the first program by applying a voltage, and then performing the second program on the memory cells of the word line based on the threshold voltage distribution of the one-shot memory cell of the word line, the coupling effect between word lines is reduced. can reduce

Hereinafter, the memory device 100 and a programming method and operating method of the memory device according to an exemplary embodiment of the present disclosure will be described in detail.

2 is a circuit diagram illustrating an example of a memory block according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2 , the memory block BLKa may be a NAND flash memory having a horizontal structure. The memory block BLKa may include, for example, d (d is an integer greater than or equal to 2) strings STRs in which the memory cells are connected in series. Each string STR may include a string select transistor SST and a ground select transistor GST respectively connected to both ends of the memory cells MC connected in series. Here, the number of strings STR, the number of word lines WL, and the number of bit lines BL may be variously changed according to embodiments.

In a NAND flash memory device including a memory block having the structure shown in FIG. 2 , erasing may be performed in units of memory blocks, and programming may be performed in units of pages corresponding to word lines WL1 to WL8 . In one example, when the memory cells MC are single-level cells, one page may correspond to each word line. In another example, when the memory cell MC is a multi-level cell or a triple-level cell, a plurality of pages PAGE may correspond to each word line.

3 is a circuit diagram illustrating another example of a memory block according to an exemplary embodiment of the present disclosure.

Referring to FIG. 3 , the memory block BLKb may be a NAND flash memory having a vertical structure. The memory block BLKb includes a plurality of NAND strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, and ground select lines GSL1, GSL2, and GSL3. , a plurality of string select lines SSL1 to SSL3 and a common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may be variously changed according to embodiments.

NAND strings NS11, NS21, and NS31 are provided between the first bit line BL1 and the common source line CSL, and the NAND strings are provided between the second bit line BL2 and the common source line CSL. NS12, NS22, and NS32 are provided, and NAND strings NS13, NS23, and NS33 are provided between the third bit line BL3 and the common source line CSL. Each NAND string (eg, NS11) may include a string select transistor SST, a plurality of memory cells MC1 to MC8, and a ground select transistor GST connected in series. Hereinafter, for convenience, a NAND string will be referred to as a string.

Strings commonly connected to one bit line constitute one column. For example, the strings NS11, NS21, and NS31 commonly connected to the first bit line BL1 correspond to the first column, and the strings NS12, NS22, and NS22 are commonly connected to the second bit line BL2. NS32) may correspond to the second column, and strings NS13, NS23, and NS33 commonly connected to the third bit line BL3 may correspond to the third column.

Strings connected to one string selection line constitute one row. For example, the strings NS11, NS12, and NS13 connected to the first string selection line SSL1 correspond to the first row, and the strings NS21, NS22, and NS23 connected to the second string selection line SSL2 corresponds to the second row, and the strings NS31, NS32, and NS33 connected to the third string selection line SSL3 may correspond to the third row.

The string select transistor SST is connected to the string select lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 are connected to corresponding word lines WL1 to WL8, respectively. The ground select transistor GST is connected to the ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST is connected to the corresponding bit line BL, and the ground select transistor GST is connected to the common source line CSL.

Word lines (eg, WL1) of the same height are commonly connected, and string select lines SSL1 to SSL3 are separated from each other. For example, when programming memory cells connected to the first word line WL1 and belonging to the strings NS11, NS12, and NS13, the first word line WL1 and the first string select line SSL1 can be selected. In one embodiment, as shown in FIG. 4 , the ground select lines GSL1 , GSL2 , and GSL3 may be separated from each other. In another embodiment, the ground selection lines GSL1 , GSL2 , and GSL3 may be connected to each other.

FIG. 4 is a perspective view illustrating a memory block according to the circuit diagram of FIG. 3 .

Referring to FIG. 4 , the memory block BLK is formed in a direction perpendicular to the substrate SUB. The substrate SUB may be the first semiconductor layer 10 of FIG. 1 . The substrate SUB has a first conductivity type (eg, p-type), extends on the substrate SUB in a first direction (eg, x direction), and has a second conductivity type (eg, x direction). , n-type) impurities may be doped with the common source line CSL. The common source line CSL may function as a source region supplying current to vertical memory cells.

On a region of the substrate SUB between two adjacent common source lines CSL, a plurality of insulating layers IL extending along a second direction (eg, y direction) are formed in a third direction (eg, y direction). z direction), and the plurality of insulating layers IL are spaced apart by a specific distance along the third direction. For example, the plurality of insulating layers IL may include an insulating material such as silicon oxide.

Channel holes sequentially disposed along the first direction and penetrating the plurality of insulating layers IL along the third direction may be formed on a region of the substrate SUB between two adjacent common source lines CSL. can The channel hole may be formed in a cup shape (or a cylinder shape with a closed bottom) extending in a vertical direction. Alternatively, the channel hole may be formed in a pillar shape as shown. Hereinafter, channel holes will be referred to as pillars. The plurality of pillars P may contact the substrate SUB by penetrating the plurality of insulating layers IL. Specifically, the surface layer (S) of each pillar (P) may include a first type silicon material and may function as a channel region. Meanwhile, the inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

In a region between two adjacent common source lines CSL, a charge storage layer CS is provided along the insulating layers IL, the pillars P, and the exposed surface of the substrate SUB. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, a gate electrode GE may be provided on an exposed surface of the charge storage layer CS in a region between two adjacent common source lines CSL.

Drains or drain contacts DR are respectively provided on the plurality of pillars P. For example, the drains or drain contacts DR may include a silicon material doped with impurities of the second conductivity type. Bit lines BL extending in the second direction (eg, y direction) and spaced apart by a specific distance along the first direction may be provided on the drains or drain contacts DR.

An exemplary embodiment of a memory block has been described with reference to FIG. 4 . However, it is not limited thereto and the structure of the memory block may be variously modified.

5A and 5B are views illustrating an operating method of a memory device according to an exemplary embodiment of the present disclosure. 5A shows a method of classifying memory cells into a plurality of cell groups according to program speeds based on a one-shot distribution of memory cells, and FIG. 5B shows a program voltage applied to a plurality of cell groups classified according to program speeds. indicate

The one-shot distribution refers to distribution of threshold voltages of memory cells generated when one program pulse voltage is applied to a selected word line. Referring to FIG. 5A , when one program pulse voltage is applied to a word line, a threshold voltage distribution of memory cells connected to the word line, that is, a one-shot distribution, may have a Gaussian distribution.

According to a method of operating a memory device according to the present embodiment, that is, a program method, a one-shot distribution (OS) of a memory cell formed based on a primary program voltage, for example, the first program voltage Vpgm1. ), the memory cells are divided into a plurality of cell groups MCG1, MCG2, and MCG3 according to the program speed, and the threshold voltage difference between the plurality of cell groups MCG1, MCG2, and MCG3 or the plurality of cell groups MCG1 , MCG2, MCG3, a plurality of secondary program voltages set based on the threshold voltage ranges (dVth1, dVth2, dVth3; or referred to as threshold voltage distribution width), for example, the second program voltage (Vpgm2) and the third program voltage Based on (Vpgm3), memory cells may be programmed to the target program state Pn. In this case, the threshold voltage ranges dVth1 , dVth2 , and dVth3 of the plurality of cell groups MCG1 , MCG2 , and MCG3 may be set differently. In an embodiment, the threshold voltage ranges dVth1, dVth2, and dVth3 may be set based on the number of memory cells included in the unit threshold voltage range of each cell group. For example, the threshold voltage ranges dVth1, dVth2, and dVth3 may be set in inverse proportion to the number of memory cells included in the unit threshold voltage range of each cell group (hereinafter referred to as the number of unit cells). According to the illustrated Gaussian-shaped one-shot distribution, the number of unit cells of the second cell group MCG2 included in the middle area of the one-shot distribution is the first cell group MCG1 included in the edge area of the one-shot distribution. ) or the number of unit cells of the third cell group MCG3. Accordingly, the threshold voltage range dVth2 of the second cell group MCG2 may be set narrower than the threshold voltage ranges dVth1 and dVth3 of the first cell group MCG1 or the second cell group CMG3.

Meanwhile, the offset voltages (Voff1, Voff2) between the program voltages (Vpgm1, Vpgm2, Vpgm3), that is, the amount of voltage increase is the threshold voltage difference or the threshold voltage range (dVth1, dVth2) of the plurality of cell groups (MCG1, MCG2, MCG3). , dVth3). For example, the first offset voltage Voff1 and the second offset voltage Voff2 are based on the threshold voltage range dVth2 of the second cell group MCG2 and the threshold voltage range dVth3 of the third cell group MCG3. can be set. In an embodiment, the first offset voltage Voff1 and the second offset voltage Voff2 are the threshold voltage range dVth2 of the second cell group MCG2 and the threshold voltage range dVth3 of the third cell group MCG3. can be proportional to In an embodiment, the first offset voltage Voff1 and the second offset voltage Voff2 may be equal to the threshold voltage ranges dVth2 and dVth3, respectively. Since dVth3 is wider than dVth2, the second offset voltage Voff2 may be greater than the first offset voltage Voff1.

Meanwhile, the first program voltage, that is, the first program voltage Vpgm1 is applied such that at least some of the memory cells, for example, memory cells having a relatively fast program speed among the memory cells are included in the target distribution TP of the target state Pn. It may be a preset voltage. In an embodiment, the first program voltage Vpgm1 may be a preset voltage so that the uppermost cell group of the one-shot distribution, eg, memory cells of the first cell group MCG1 are included in the target distribution TP.

6 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure. A method of programming memory cells into one of a plurality of program states according to an operating method of a memory device according to an exemplary embodiment of the present disclosure will be described with reference to FIGS. 5A, 5B, and 6 .

Referring to FIG. 6 , memory cells may be programmed based on the first program voltage (S110). The primary program voltage includes the first program voltage Vpgm1. The first program is performed by applying the first program voltage Vpgm1 to the memory cells in the previous state Pn−1 (or erase state). Some of the memory cells, memory cells having a high program speed, may be included in the target distribution TP.

For example, when the memory cells are programmed into the first program state, a preset first program voltage corresponding to the first program state, that is, the first program voltage Vpgm1 may be applied to the memory cells. Accordingly, the memory cells may be roughly programmed into the first program state. Some of the memory cells, for example, some of the memory cells having a relatively high programming speed may be included in the target distribution of the first program state.

Memory cells subjected to the first program may be verified and read, and the memory cells may be divided into a plurality of cell groups according to program speeds based on threshold voltages of the memory cells (S120). For example, memory cells may be divided into at least three cell groups.

According to the execution of the first program, a one-shot distribution of memory cells is formed, and the memory cells can be verified and read to be divided into a plurality of cell groups. 5A shows that memory cells are divided into three cell groups, but is not limited thereto. Memory cells may be divided into a larger number of cell groups.

When the memory cells are multi-level cells storing 2-bit data, the memory cells may be divided into three cell groups. In another embodiment, when a memory cell is a triple-level cell storing 3-bit data, the memory cells may be divided into five cell groups. However, it is not limited thereto, and the number of cell groups may be determined according to the width of the target distribution of the program state. For example, the number of cell groups when the target distribution width of the program state is narrow may be greater than the number of cell groups when the target distribution width of the program state is wide.

Meanwhile, in step S120, threshold voltage ranges of a plurality of cell groups may be set differently. For example, a threshold voltage range of a cell group corresponding to a middle region of a distribution of memory cells among a plurality of cell groups may be set to be relatively narrower than that of other cell groups. Also, threshold voltage ranges of cell groups corresponding to an upper region or a lower region of the distribution of memory cells may be set to be relatively wider than those of other memory cells.

For example, as shown in FIG. 5A , the threshold voltage range dVth2 of the second cell group MCG2 corresponding to the middle region of the distribution of memory cells among the first to third cell groups MCG1 , MCG2 , and MCG3 may be set to be relatively narrower than the threshold voltage ranges dVth1 and dVth3 of the first cell group MCG1 or the third cell group MCG3 corresponding to the edge region of the distribution.

Meanwhile, the memory cells may be classified into a plurality of cell groups by performing a verification read based on a preset verification voltage. In this case, the verification voltage may be set so that the plurality of cell groups have different threshold voltage ranges. The verification voltage is the program state of memory cells according to the one-shot program (eg, distribution range of one-shot distribution, position of distribution, etc.) and a plurality of It can be set based on the threshold voltage ranges of the cell group.

For example, the memory cells may be divided into a plurality of cell groups by verifying and reading the memory cells based on the first and second verifying voltages Vrf1 and Vrf2 . A voltage difference between the first verifying voltage Vrf1 and the second verifying voltage Vrf2 may be proportional to the threshold voltage range dVth2 of the second cell group MCG2.

In an embodiment, memory cells may be divided into three cell groups through one verify read operation by sensing memory cells twice at different times based on one verify voltage. This may be referred to as a double sensing operation. In this case, the time interval between the first sensing time and the second sensing time may be set based on the threshold voltage range dVth2 of the second cell group MCG2. For example, the time interval when the threshold voltage range of the second cell group MCG2 is 1V (volt) may be set to be smaller than the time interval when the threshold voltage range is 0.8V.

Thereafter, at least some of the plurality of cell groups are generated based on the second program voltage, for example, the second program voltage Vpgm2 and the third program voltage Vpgm3, the voltage levels of which are set based on the difference in threshold voltages of the plurality of cell groups. The cell group can be reprogrammed (S130). In other words, among the plurality of cell groups, cell groups other than the cell group included in the target distribution (TP) may be reprogrammed. For example, when the first cell group MCG1 is included in the target distribution TP and the other cell groups MCG2 and MCG3 deviate from the target distribution TP, the first cell group included in the target distribution TP The second cell group MCG2 and the third cell group MCG3 excluding the cell group MCG1 may be reprogrammed to a target state. The second cell group MCG2 and the third cell group MCG3 may be reprogrammed based on a plurality of secondary program voltages, that is, the second program voltage Vgpm2 and the third program voltage Vpgm3. The second program voltage Vpgm2, the voltage level of which is increased by the first offset voltage Voff1 from the first program voltage Vpgm1, may be applied to the second cell group MCG2 and the third cell group MCG3. Accordingly, the memory cells of the second cell group MCG2 may be included in the target distribution TP. Next, the third program voltage Vpgm3 whose voltage level is increased by the second offset voltage Voff2 from the second program voltage Vpgm2 may be applied to the third cell group MVG3. Accordingly, the memory cells of the third cell group MCG3 may be included in the target distribution TP.

In an embodiment, the voltage level of the second cell group MCG2 and the third cell group MCG3 is equal to the sum of the first offset voltage Voff1 and the second offset voltage Voff2 from the first program voltage Vpgm1. By applying the increased second program voltage Vpgm2, the second program can be performed. In this case, the programming speed of the second cell group MCG2 may be slowed down by applying a forcing voltage to the bit lines of the memory cells of the second cell group MCG2 . A voltage level of the forcing voltage may be equal to a level of the second offset voltage Voff2. Accordingly, memory cells of the second cell group MCG2 and the third cell group MCG3 may be included in the target distribution TP.

7A and 7B are graphs illustrating distribution of memory cells according to setting threshold voltage ranges of cell groups. FIG. 7A shows a case in which the threshold voltage ranges of cell groups are identically set, and FIG. 7B shows a case in which the threshold voltage ranges of cell groups are set differently according to an embodiment of the present disclosure.

Referring to FIG. 7A , for example, when memory cells are programmed using an incremental step pulse programming (ISPP) method, the memory cells may be divided into a plurality of cell groups having the same threshold voltage range. Since the voltage pulse increases at a constant level according to each program step, threshold voltage ranges (or spread widths) of cell groups programmed to a target program state in each program step may also be the same. At this time, the number of memory cells in the second cell group MCG2 is greater than the number of memory cells in the first cell group MCG1 or the third cell group MCG3. Accordingly, the final distribution threshold voltage range dVthF2 of the second cell group MCG2 may be wider than the final distribution threshold voltage range dVthF1 of the first cell group MCG1 and the third cell group MCG3. As such, when memory cells are divided into a plurality of cell groups having the same threshold voltage range and programmed, the final threshold distribution of the cell groups may have different threshold voltage ranges. The final threshold distribution of cell groups should be included in the target distribution of target program state. Accordingly, the number of programs may be increased to match the final distribution of the cell group having the widest distribution among the cell groups to the target distribution.

However, as shown in FIG. 7B , according to an embodiment of the present disclosure, memory cells are divided into a plurality of cell groups with different threshold voltage ranges, but the threshold voltage of each cell group is in inverse proportion to the number of unit cells in each cell group. When the range is set, a difference in the number of memory cells included in each cell group may not be large.

When a plurality of cell groups are programmed based on program voltages whose voltage levels are set according to the threshold voltage range, the final distribution threshold voltage range dVthF3 of each cell group may be similar to each other. Compared to the case of programming by the programming method of FIG. 7A , the maximum value (dVthF3) of the final distribution threshold voltage range of each cell group may be narrower than the maximum value (dVthF2) of the final distribution of each cell group of FIG. 7A . Therefore, if programming is performed by setting different threshold voltage ranges of cell groups according to the programming method according to an embodiment of the present disclosure, the number of times of programming or the width of the threshold voltage distribution of programmed memory cells may be reduced. .

8(a) to (d) are graphs showing an example of a program method step by step according to an embodiment of the present disclosure. FIG. 9 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG. 8 .

Referring to FIGS. 8A and 9 , a first program voltage, that is, a first program voltage Vpgm1 is applied to memory cells in an erase state E. Accordingly, a one-shot distribution of memory cells according to the first program voltage Vpgm1 is formed. The one-shot distribution may have a Gaussian shape. An upper region of the one-shot distribution (a region to the right of the one-shot distribution) may be included in the target distribution TP1 of the first program state P1. In other words, in the one-shot distribution of memory cells, the threshold voltages of the upper portion of memory cells may be included within the threshold voltage range dVT of the target distribution TP1.

Referring to FIG. 8B , memory cells are classified into three cell groups G1 , G2 , and G3 according to program speeds based on threshold voltages of the memory cells. Through the verification read, memory cells may be divided into three cell groups. In an exemplary embodiment, the memory cells may be divided into three cell groups by verifying and reading the memory cells based on the first verifying voltage Vrf1 and the second verifying voltage Vrf2. In an embodiment, a voltage difference between the first verifying voltage Vrf1 and the second verifying voltage Vrf2 may be the same as the threshold voltage range dVth2 of the second cell group G2. In an embodiment, the first verification voltage Vrf1 may be the same as the verification read voltage Vv1 for the first program state for verifying whether the memory cells are normally programmed into the first program state.

The threshold voltage ranges dVth1 , dVTh2 , and dVth3 of the cell groups G1 , G2 , and G3 may be set based on the unit threshold voltage range of the corresponding cell group. For example, the threshold voltage ranges dVth1, dVth2, and dVth3 may be set in inverse proportion to the number of memory cells included in the unit threshold voltage range of each cell group (hereinafter referred to as the number of unit cells). The threshold voltage range dVth2 of the second cell group G2 may be narrower than the threshold voltage range dVth1 of the first cell group G1 or the threshold voltage range dVth3 of the second cell group G3.

As the second program voltage Vpgm2 among the plurality of secondary program voltages is applied to the memory cells of the second cell group G2 and the third cell group G3, the distribution of the memory cells is shown in FIG. 8(c). change as bar The voltage level of the second program voltage Vpgm2 is a value obtained by adding the first offset voltage Voff1 to the voltage level of the first program voltage Vpgm1. The first offset voltage Voff1 may be equal to the threshold voltage range dVth2 of the second cell group G2.

The second program voltage Vpgm2 is applied to the memory cells of the second cell group G2 and the third cell group G3, except for the first cell group G1 already included in the target distribution TP1, so that the second program voltage Vpgm2 is applied. The threshold voltage distributions of the second cell group G2 and the third cell group G3 shift to the right, and the second cell group G2 may be included in the target distribution TP1.

Then, as shown in FIG. 8(d), the third program voltage Vpgm3 among the secondary program voltages is applied to the memory cells of the third cell group G3. The voltage level of the third program voltage Vpgm3 is a value obtained by adding the second offset voltage Voff2 to the voltage level of the second program voltage Vpgm2. The second offset voltage Voff1 may be equal to the threshold voltage range dVth3 of the third cell group G3. Accordingly, the threshold voltage distribution of the third cell group G3 shifts to the right, and the third cell group G3 may be included in the target distribution TP1. As a result, the memory cells may be programmed to the first program state P1.

In the above, the case of programming the memory cells to the first program state P1 has been described step by step with reference to FIGS. 8 and 9 . The above-described method may be applied even when memory cells are programmed in a different program state.

10 is a diagram illustrating a program method according to an embodiment of the present disclosure in more detail. 10 illustrates the program method according to FIGS. 8 and 9 in more detail, and the contents described with reference to FIGS. 8 and 9 may be applied to the embodiment of FIG. 10 .

Referring to FIG. 10 , a first program may be performed by applying a first program voltage to a word line to which memory cells are connected (S210). A distribution of a portion of memory cells, that is, a distribution of an upper region of the one-shot distribution of memory cells may be included in the target distribution of the target program state.

Based on the threshold voltages of the memory cells, the memory cells are divided into three cell groups according to the program speed (S220). The first programmed memory cells may be verified and read based on a preset verification voltage, and the memory cells may be divided into three cell groups according to threshold voltages. In this case, the cell group having a relatively high threshold voltage, for example, the first cell group includes fast cells having a high program speed, and the cell group having a relatively low threshold voltage, for example, the third cell group includes slow cells having a slow program speed. include Accordingly, memory cells may be divided into three cell groups according to program speed. At this time, the threshold voltage range of the cell group corresponding to the middle region of the distribution of memory cells among the three cell groups, eg, the second cell group, is higher than that of the other cell groups, eg, the first cell group and the second cell group. can be narrowly set.

After memory cells are divided into three cell groups, a second programming step ( S230 ) and a third programming step ( S240 ) may be performed.

First, an inhibit voltage is applied to the bit lines of the memory cells of the first cell group (S231). The distribution of the first cell group may be included in the target distribution of the target program state. Accordingly, the program for the first cell group does not proceed any further. An inhibit voltage may be applied to bit lines of memory cells of the first cell group to prevent the program from being performed on the first cell group.

Thereafter, a second program voltage may be applied to the word line (S232). The second program voltage is a voltage obtained by increasing a voltage level by the first offset voltage from the first program voltage, and the first offset voltage may be set based on a threshold voltage range of the second cell group. According to the second program S230, the distribution of the second cell group may be included in the target distribution of the target program state.

Since the distribution of the first cell group and the second cell group are included in the target distribution, the third program (S240) may be executed for the third cell group thereafter.

An inhibit voltage is applied to the bit lines of the memory cells of the first cell group and the second cell group (S241), and a third program voltage is applied to the word line (S242). The third program voltage is a voltage obtained by increasing the voltage level by the second offset voltage from the second program voltage, and the second offset voltage may be set based on a threshold voltage range of the third cell group. According to the third program (S240), the distribution of the third cell group may be included in the target distribution. In this way, the program for one program state can be completed.

Meanwhile, although not shown, in one embodiment, after step S240 , a verification read step of determining whether memory cells are normally programmed to a target program state may be performed. When the number of memory cells exceeding the threshold exceeds the target distribution of target program states, additional programming may be performed on the memory cells. Alternatively, a page including the memory cells may be processed as a fail.

11 (a) to (c) are graphs showing an example of a program method step by step according to an embodiment of the present disclosure. FIG. 12 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG. 11 .

11(a) and 12, a first program voltage, that is, a first program voltage Vpgm1 is applied to memory cells in an erase state E, and the first program PGM1 is performed on the memory cells. can Referring to FIG. 11( b ) , memory cells are classified into three cell groups G1 , G2 , and G3 according to program speeds based on threshold voltages of the memory cells. The steps of FIGS. 11(a) and 11(b) are the same as those of FIGS. 8(a) and (b), and detailed description thereof will be omitted.

As the second program voltage Vpgm2 is applied to the memory cells of the second cell group G2 and the third cell group G3, the second program PGM2 may be performed. The distribution of memory cells is changed as shown in Fig. 11(c). The voltage level of the second program voltage Vpgm2 is a value obtained by adding the offset voltage Voff to the voltage level of the first program voltage Vpgm1. The offset voltage Voff may be equal to the threshold voltage range dVth2 of the second cell group G2 and the threshold voltage range dVth3 of the third cell group G3. The second program voltage Vpgm2 is applied to the memory cells of the second cell group G2 and the third cell group G3, except for the first cell group G1 already included in the target distribution TP1, so that the second program voltage Vpgm2 is applied. The threshold voltage distributions of the second cell group G2 and the third cell group G3 may shift to the right. Meanwhile, when the second program voltage Vpgm2 is applied to the memory cells of the second cell group G3, the second cell group G3 may be overprogrammed. The distribution threshold voltage of the memory cells of the second cell group G3 may be higher than the threshold voltage of the target distribution TP1. To prevent this, the programming speed of the second cell group G2 may be slowed down by applying the forcing voltage VBLF to the bit lines of the memory cells of the second cell group G2. For example, the level of the forcing voltage VBLF may be lower than the level of the inhibit voltage. For example, the level of the forcing voltage VBLF may correspond to the threshold voltage range dVth3 of the third cell group G3. Accordingly, as the second program PGM2 is performed based on the second program voltage Vpgm2 and the forcing voltage VBLF, the target distribution TP1 of the second cell group G2 and the third cell group G3 ) can be included. As a result, the memory cells may be programmed to the first program state P1.

13 is a diagram illustrating a program method according to an embodiment of the present disclosure in more detail. 13 illustrates the program method according to FIGS. 11 and 12 in more detail, and the contents described with reference to FIGS. 11 and 12 may be applied to the embodiment of FIG. 13 .

Referring to FIG. 13 , a first program is applied to the memory cells by applying a first program voltage to a word line to which the memory cells are connected (S310), and the memory cells are adjusted to a program speed based on the threshold voltages of the memory cells. It is divided into three cell groups according to (S320). Steps S310 and S320 are the same as steps S210 and S220 of FIG. 10, so detailed descriptions thereof will be omitted.

After dividing the memory cells into three cell groups, a second program (S330) may be performed.

An inhibit voltage is applied to the bit lines of the memory cells of the first cell group (S331). The distribution of the first cell group may be included in the target distribution of the target program state. Accordingly, the program for the first cell group does not proceed any further. In order to prevent reprogramming of the first cell group, an inhibit voltage may be applied to bit lines of memory cells of the first cell group.

A forcing voltage is applied to the bit lines of the memory cells of the second cell group (S332).

The distributions of the second cell group and the third cell group have different positions and ranges of distributions on the threshold voltage. In order to simultaneously program the second cell group and the third cell group to the target state, a forcing voltage is applied to bit lines of memory cells of the second cell group whose program speed is relatively high, thereby slowing down the program speed.

Then, a second program voltage is applied to the word line (S343). The second program voltage is a primary program voltage, that is, a voltage whose voltage level is increased by an offset voltage from the first program voltage, and the offset voltage is based on the threshold voltage range of the second cell group and the threshold voltage range of the third cell group. can be set by For example, the offset voltage is equal to the sum of the threshold voltage range of the second cell group and the threshold voltage range of the third cell group.

In one embodiment, the application of the inhibit voltage (S331) and the application of the forcing voltage (S332) may be performed simultaneously. Furthermore, the application of the inhibit voltage (S331), the application of the forcing voltage (S332), and the application of the second program voltage (S343) may be performed simultaneously.

14A and 14B are views illustrating an operating method of a memory device according to an exemplary embodiment of the present disclosure. 14A shows a method of classifying memory cells into five cell groups according to program speeds based on a one-shot distribution of memory cells, and FIG. 14B shows program voltages applied to a plurality of cell groups.

Referring to FIG. 14A , based on the one-shot distribution of memory cells, memory cells may be classified into five cell groups (MCG1 to MCG5) according to program speed. Threshold voltage ranges of the five cell groups (MCG1 to MCG5) may be different from each other.

For example, the threshold voltage ranges dVth1 to dVth5 may be set in inverse proportion to the number of memory cells included in the unit threshold voltage range of each cell group (hereinafter referred to as the number of unit cells). According to the illustrated one-shot distribution, the number of unit cells in the third cell group MCG3 may be relatively greater than the number of unit cells in other cell groups. Accordingly, the threshold voltage range dVth3 of the third cell group MCG3 may be set to be narrower than the threshold voltage ranges of the other cell groups. Conversely, the number of unit cells in the edge area of the one-shot distribution, eg, the first cell group MCG1 or the fifth cell group MCG5, is relatively smaller than the number of unit cells in other cell groups. Accordingly, the threshold voltage range dVth1 of the first cell group MCG1 or the threshold voltage range dVth5 of the fifth cell group MCG5 may be set wider than the threshold voltage ranges of the other cell groups.

In this way, memory cells divided into five cell groups (MCG1 MCG5) with different threshold voltage ranges are set based on the threshold voltage difference or threshold voltage ranges (dVth1 to dVth5) of the plurality of cell groups (MCG1 to MCG5). Based on the plurality of secondary program voltages Vpgm2 to Vpgm5 to be set, it can be reprogrammed to the target program state Pn.

Referring to FIG. 14B , the first program voltage Vpgm1 may be a preset voltage such that at least some of the memory cells are included in the target distribution TP of the target state Pn. In an embodiment, the first program voltage Vpgm1 may be a preset voltage so that memory cells of the uppermost cell group of the one-shot distribution, eg, the first cell group MCG1, are included in the target distribution TP.

The second to fifth program voltages Vpgm2 to Vpgm5 may be voltages whose voltage levels are sequentially increased from the first program voltage Vpgm1. Offset voltages (Voff1 to Voff4) between program voltages (Vpgm1 to Vpgm5), that is, the amount of voltage increase is based on the threshold voltage difference between the second to fifth cell groups (MCG2 to MCG5) or the threshold voltage range (dVth2 to dVth5). can be set by In an embodiment, the offset voltages Voff1 to Voff4 may be proportional to the threshold voltage range dVth2 to dVth5. In an embodiment, the offset voltages Voff1 to Voff4 may be equal to the range of threshold voltages dVth2 to dVth5, respectively. Accordingly, the second offset voltage Voff2 may be relatively small and the fourth offset voltage Voff4 may be relatively large.

15 (a) to (f) are graphs showing an example of a program method step by step according to an embodiment of the present disclosure. FIG. 16 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG. 15 .

15(a) and 16, the first program PGM1 is executed. The first program voltage Vpgm1 may be applied to the memory cells in the erased state (E). Accordingly, a one-shot distribution of memory cells according to the first program voltage Vpgm1 is formed. An upper region of the one-shot distribution (a region to the right of the one-shot distribution) may be included in the target distribution TP1 of the first program state P1.

Referring to FIG. 15(b) , memory cells are divided into five cell groups G1 to G5 according to program speeds based on threshold voltages of the memory cells. In an embodiment, memory cells may be divided into five cell groups G1 to G5 by sequentially reading memory cells based on at least four verification voltages. In another embodiment, as shown in FIG. 16 , memory cells may be divided into five cell groups G1 to G5 through at least two verification steps VF1 and VF2 .

In this embodiment, as shown in FIG. 16 , it is assumed that memory cells are divided into five cell groups G1 to G5 through at least two verification steps VF1 and VF2. In the first verification step VF1 , the memory cells may be divided into three cell groups by verifying and reading the memory cells based on the first verification voltage Vrf1 and the second verification voltage Vrf2 . The memory cells may be divided into a first cell group G1, a second cell group G2, and the remaining cell groups G3, G4, and G5.

After that, the second program (VPGM2) is executed. As the second program voltage Vpgm2 is applied to the memory cells of the second cell group G2 and the remaining cell groups G3 to G5 except for the first cell group G1 included in the target distribution TP1, the second program voltage Vpgm2 is applied to the memory cells. The distribution of cells is changed, as shown in Fig. 15(C). The voltage level of the second program voltage Vpgm2 is a value obtained by adding the first offset voltage Voff1 to the voltage level of the first program voltage Vpgm1. The first offset voltage Voff1 may be equal to the threshold voltage range dVth2 of the second cell group G2. The threshold voltage distribution of the second to fifth cell groups G2 to G5 shifts to the right, and the second cell group G2 may be included in the target distribution TP1.

Next, the third program (VPGM3) is executed. As the third program voltage Vpgm3 is applied to the memory cells of the remaining cell groups, for example, the third to fifth cell groups G3 to G5, the distribution of the memory cells is changed as shown in FIG. 15(d). The third cell group G3 may be included in the target distribution TP1. The voltage level of the third program voltage Vpgm3 is a value obtained by adding the second offset voltage Voff2 to the voltage level of the second program voltage Vpgm2. The second offset voltage Voff2 may be equal to the threshold voltage range dVth3 of the third cell group G3. The second offset voltage Voff2 may be smaller than the first offset voltage Voff1. Accordingly, the movement width of the distribution of memory cells according to the third program VPGM3 may be smaller than the movement width of the distribution of memory cells according to the second program VPGM2.

Next, a secondary verification (VF2) is performed. Memory cells may be divided into three cell groups by verifying and reading the memory cells based on the first and second verify voltages Vrf1 and Vrf2 . The memory cells may be divided into first to third cell groups G1 to G3, a fourth cell group G4, and a fifth cell group G5 included in the target distribution TP1. In an exemplary embodiment, memory cells of the remaining cell groups G3 to G5 excluding the first cell group G1 and the second cell group G2 are verified and read, thereby generating the remaining cell groups G3 to G5. The memory cells of can be divided into a third cell group G3, a fourth cell group G4, and a fifth cell group G5. In this case, power consumption according to verification read can be reduced.

After that, the fourth program (PGM4) is executed. The fourth program voltage Vpgm4 is applied to the memory cells of the fourth cell group G4 and the fifth cell group G5 excluding the first to third cell groups G1 to G3 included in the target distribution TP1. , the distribution of memory cells is changed, as shown in FIG. 15(e). The voltage level of the fourth program voltage Vpgm4 is a value obtained by adding the third offset voltage Voff3 to the voltage level of the third program voltage Vpgm3. The third offset voltage Voff3 may be equal to the threshold voltage range dVth4 of the fourth cell group G4. The threshold voltage distributions of the fourth cell group G4 and the fifth cell group G5 shift to the right, and the fourth cell group G4 may be included in the target distribution TP1.

Next, the fifth program (VPGM5) is executed. As the fifth program voltage Vpgm5 is applied to the memory cells of the remaining cell groups not included in the target distribution TP1, that is, the fifth cell group G5, the distribution of memory cells is shown in FIG. 15(f). change as bar The voltage level of the fifth program voltage Vpgm5 is a value obtained by adding the fourth offset voltage Voff4 to the voltage level of the fourth program voltage Vpgm4. The fourth offset voltage Voff4 may be equal to the threshold voltage range dVth5 of the fifth cell group G5. The fourth offset voltage Voff4 may be relatively greater than other offsets. Therefore, the movement width of the distribution of memory cells according to the 5th program VPGM5 may be relatively larger than the above-described steps of performing the 2nd to 4th programs VPGM2 to VPMG4. Accordingly, the fifth cell group G5 may be included in the target distribution TP1. As a result, the memory cells may be programmed to the first program state P1.

17 (a) to (d) are graphs showing an example of a program method step by step according to an embodiment of the present disclosure. FIG. 18 is a waveform diagram of a voltage applied to a word line connected to a memory cell programmed in FIG. 17 .

The programming method according to FIGS. 17 (a) to (d) is similar to FIG. 15 (a) to (f). However, in the program method according to the present embodiment, two cell groups may be included in the target distribution TP1 in the second program step PGM2 and the third program step PGM3. Referring to FIGS. 17(b) and 18 , in the second program step PGM2, a first forcing voltage VBF1 is applied to memory cells of the second cell group G2. , the second program voltage Vpgm2 may be applied to the memory cells of the second to fifth cell groups G2 to G5. Accordingly, the memory cells of the second cell group G2 and the third cell group G3 may be included in the target distribution TP1. In this case, the voltage level of the second program voltage Vpgm2 may be a level increased by the first offset voltage Voff1 from the first program voltage Vpgm1. The first offset voltage Voff1 may be equal to the sum of the threshold voltage range dVth2 of the second cell group G2 and the threshold voltage range dVth3 of the third cell group G3, and the first forcing voltage ( VBLF1) may be equal to the threshold voltage range dVth3 of the third cell group G3.

17(c) and 18, in the third program step PGM3, the second forcing voltage VBF2 is applied to the memory cells of the fourth cell group G4. and the third program voltage Vpgm3 may be applied to the memory cells of the fourth and fifth cell groups G4 and G5. Accordingly, the memory cells of the fourth cell group G3 and the fifth cell group G5 may be included in the target distribution TP1. In this case, the voltage level of the third program voltage Vpgm3 may be increased from the second program voltage Vpgm2 by the second offset voltage Voff2. The second offset voltage Voff2 may be equal to the sum of the threshold voltage range dVth4 of the fourth cell group G4 and the threshold voltage range dVth3 of the fifth cell group G5, and the second forcing voltage ( VBLF2) may be equal to the threshold voltage range dVth5 of the fifth cell group G5.

Accordingly, memory cells may be programmed to a target program state, for example, a first program state P1, and at this time, in the second and third program steps, at least two cell groups may be simultaneously included in the target distribution TP. By programming, the number of programming steps can be reduced.

19 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure. FIG. 19 is a diagram explaining a method of operating the memory device of FIG. 17 in more detail.

Referring to FIG. 19 , a first program is performed by applying a first program voltage, that is, a first program voltage to a word line to which memory cells are connected (S410). A distribution of a subset of memory cells may be included in the target distribution.

Thereafter, the memory cells on which the first program has been performed may be divided into three cell groups according to the program speed based on the threshold voltage (S420). For example, memory cells may be divided into first, second, and remaining cell groups. The memory cells may be divided into three cell groups by verifying the memory cells based on a preset verification voltage. For example, memory cells may be divided into three cell groups based on the first and second verification voltages Vrf1 and Vrf2. The first cell group may have the highest threshold voltage and the other cell groups may have the lowest threshold voltage. In this case, the higher the threshold voltage of the memory cells, the faster the program speed of the memory cells. Accordingly, memory cells may be divided into three cell groups according to program speed.

Thereafter, a second program may be performed on the second and remaining cell groups (S430). In this case, the first cell group, which is a cell group having the highest threshold voltage, may be included in the target distribution. Accordingly, an inhibit voltage may be applied to the bit lines of the memory cells of the first cell group to prevent the program from being performed on the first cell group (S431).

The second program may be performed by applying a first forcing voltage to the bit line of the memory cells of the second cell group (S432) and applying a second program voltage to the word line (S433). The shift width of the distribution of the second cell group should be smaller than the shift width of the distribution of the other cell groups. Accordingly, the programming speed of the second cell group may be slowed down by applying the forcing voltage to the bit lines of the memory cells of the second cell group. Accordingly, memory cells of the second cell group and some of the remaining cell groups, for example, the third cell group, may be simultaneously programmed to the target program state based on the second program voltage. In this case, the voltage level of the second program voltage may be a level increased by the first offset voltage from the first program voltage. The first offset voltage may be equal to the sum of the threshold voltage range of the second cell group and the threshold voltage range of a cell group having a relatively high threshold voltage among the remaining cell groups, for example, the third cell group. It may be the same as the threshold voltage range of the 3 cell group.

Next, memory cells may be further divided into three cell groups according to threshold voltages (S440). In an embodiment, memory cells may be divided into three cell groups based on the foregoing, eg, first and second verification voltages Vrf1 and Vrf2.

In an embodiment, the remaining cell groups may be divided into the third, fourth, and fifth cell groups by verifying and reading the remaining cell groups. In this case, memory cells of the third cell group may be included in the target distribution.

A third program may be performed on the memory cells of the fourth and fifth cell groups (S450). In order to prevent the memory cells of the first cell group, the second cell group, and the third cell group from being programmed, which are already included in the target distribution, an inhibit voltage is applied to the bit lines of the memory cells of the first to third cell groups. can be applied (S451).

A third program may be performed by applying a forcing voltage to the bit line of the memory cells of the fourth cell group (S452) and applying a third program voltage to the word line (S453). The shift width of the distribution of the fourth cell group should be smaller than the shift width of the distribution of the fifth cell group. Accordingly, the programming speed of the fourth cell group may be slowed down by applying the forcing voltage to the bit lines of the memory cells of the fourth cell group. Accordingly, memory cells of the fourth cell group and the fifth cell group may be simultaneously programmed to the target program state based on the third program voltage. In this case, the voltage level of the third program voltage may be increased from the second program voltage by the second offset voltage. The second offset voltage may be equal to the sum of the threshold voltage range of the fourth cell group and the threshold voltage range of the fifth cell group, and the second forcing voltage may be equal to the threshold voltage range of the fifth cell group.

As such, after the first program is performed on all memory cells set to be programmed in the first program state, the memory cells are divided into five cell groups according to the program speed, and cell groups other than the first cell group Reprogramming may be performed in units of two cell groups.

20 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure. 20 illustrates a program method when a memory device stores 2-bit data in each memory cell. 21 shows threshold voltage distribution of memory cells according to each program state.

Referring to FIG. 20 , the memory device ( 100 of FIG. 1 ) may perform a program operation according to an embodiment of the present disclosure when receiving multi-bit data and a program command from an external device, for example, a memory controller (S510).

The memory device may program the memory cells into a first program state based on the first program voltage set (S520). The first program voltage set may include first through nth program voltages for programming memory cells into a first program state. The first program voltage is a primary program voltage, and the second through nth program voltages are a plurality of secondary program voltages. For example, as shown in FIG. 5A , when memory cells are divided into three cell groups according to program speed and programmed, the first program voltage set may include first to third program voltages. In another embodiment, the first program voltage set may include first and second program voltages and a forcing voltage.

In this case, the first program voltage may be a preset voltage such that at least some of the memory cells are included in the target distribution of the target program state. In one embodiment, the first program voltage is set in advance so that memory cells of the highest cell group of the one-shot distribution are included in the target distribution when the memory cells are divided into a plurality of cell groups after the first program is performed. It may be a set voltage. The second through nth program voltages may be voltages set according to differences in threshold voltages between the plurality of cell groups.

When the programming for the first program state is completed, the memory device may program the memory cells to the second program state based on the second program voltage set (530). The second program voltage set may include first through nth program voltages for programming the memory cells into the second program state.

In one embodiment, the memory device may program some of the memory cells programmed in the first program state into the second program state. In another embodiment, the memory device may program memory cells different from memory cells programmed in the first program state into the second program state.

When the programming for the second program state is completed, the memory device may program the memory cells to the third program state based on the third program voltage set (S540). The third program voltage set may include first to nth program voltages for programming memory cells into a third program state.

In one embodiment, the memory device may program some of the memory cells programmed in the second program state into a third program state. In another embodiment, the memory device may program memory cells different from memory cells programmed in the first and second program states into a third program state.

Meanwhile, the voltage level of the first program voltage for each program state, that is, the first program voltage, may be set by the first program voltage of the previous program state and the program offset.

As shown in FIG. 21, when the threshold voltage difference between the second program state P2 and the first program state P1 is the second program offset VoffP2, the first program for the second program state P2 The voltage level of the voltage Vpgm12 may be set based on the first program voltage Vpgm11 and the second program offset VoffP2 for the first program state P1. Also, when the threshold voltage difference between the third program state P3 and the second program state P2 is the third program offset VoffP3, the first program voltage Vpgm13 for the third program state P3 is It may be set based on the first program voltage (Vpgm12) and the third program offset (VoffP3) for the second program state (P2).

Meanwhile, the program method according to the embodiment of the present disclosure described with reference to FIGS. 5A to 19 may be applied to each of the program steps S520, S530, and S540. In each program step, memory cells subjected to the first program according to the first program voltage, that is, the first program voltage, are divided into a plurality of cell groups according to the program speed, and the plurality of cell groups have different threshold voltages. A plurality of secondary program voltages set to correspond to the range may be applied to a memory cell group not included in the target distribution, and the program may be performed.

When programming memory cells in a plurality of program states, when programming using the ISPP method, when the threshold voltage difference between the two program states is relatively large, the number of programs is increased compared to when the threshold voltage difference between the two program states is relatively small. can However, according to the method of operating a memory device according to an exemplary embodiment of the present disclosure, program voltages corresponding to respective program states are previously set, and memory cells are programmed into respective program states based on the preset program voltages. Memory cells may be programmed according to a preset number of programs regardless of a threshold voltage difference between states.

22 is a waveform illustrating a voltage pulse applied to a word line as an example of a method of operating a memory device according to an embodiment of the present disclosure.

22 illustrates a method in which memory cells are sequentially programmed in a first programmed state P1, a second programmed state P2, and a third programmed state P3 when the memory cell is a multi-bit cell storing 2-bit data. this is shown

Referring to FIG. 22 , the program phase of the memory device may include a first program period (P1 PGM), a second program period (P2 PGM), and a third program period (P3 PGM).

When multi-bit data and a command requesting storage of the multi-bit data are received from the outside (eg, a memory controller), memory cells are programmed in a first program state in the first program period (P1 PGM), and in the second program period ( Memory cells may be programmed in the second program state in the P2 PGM, and memory cells may be programmed in the third program state in the third program period P3 PGM. Accordingly, multi-bit data may be stored in memory cells connected to one word line of the memory cell array (110 in FIG. 1), for example, a page.

Each program section, that is, each program loop, may include at least two program steps, eg, first and second program steps and a verify read step (VF). 22 shows that each program section includes two program steps and one verification read step, but is not limited thereto. Depending on how many cell groups memory cells are divided into according to program speed and whether a bit line forcing program is performed on some cell groups, the number of programs or verification reads may be further increased.

Meanwhile, the program step and the verification read step, which are performed in each program section, may be performed as described with reference to FIGS. 5A to 19 . Based on the primary program voltage, the memory cells on which the first program has been performed are divided into a plurality of cell groups according to the program speed in the verify read step (VF), and a plurality of cells are divided into cell groups not included in the target distribution. By reprogramming (eg, performing a second program and a third program) based on a plurality of secondary program voltages, for example, second and third program voltages, the voltage levels of which are set based on the threshold voltage range of the group, Cells can be programmed to be included in the target distribution of each programmed state.

Meanwhile, in each program period, voltage levels of the first program voltages Vpgm11, Vpgm12, and Vpgm13 may be determined according to the first program voltage of the previous program period and the program offset of each program state. In this case, the program offset, as shown in FIG. 21, means a threshold voltage difference between program states. For example, in the second program period P2 PGM, the voltage level of the first program voltage Vpgm12 is equal to the first program voltage Vpgm11 in the first program period P1 PGM and the second program offset VoffP2. ) may be added. The voltage level of the first program voltage Vpgm13 in the third program period P3 PGM is the value obtained by adding the third program offset VoffP3 to the first program voltage Vpgm12 in the second program period P1 PGM. can

Meanwhile, after the memory cells are programmed into the third program state, a verify read operation may be performed. It may be determined whether the memory cells are normally programmed through the verify read operation. In one embodiment, a verify read operation may be performed on the third program state. When it is determined that the memory cells are normally programmed into the third programmed state, it may be determined that other memory cells are also normally programmed into the first programmed state or the second programmed state. However, the present invention is not limited thereto, and in another embodiment, a verify read operation may be performed for each of the first to third program states.

23 is a waveform illustrating a voltage pulse applied to a word line as an example of a method of operating a memory device according to an embodiment of the present disclosure.

23 illustrates a method in which memory cells are sequentially programmed in a first programmed state P1, a second programmed state P2, and a third programmed state P3 when the memory cell is a multi-bit cell storing 2-bit data. this is shown The program method of FIG. 23 is similar to the program method shown in FIG. However, in FIG. 23, in the verify read step (VF) of the first program period (P1 PGM) for programming the memory cells to the first program state, the memory cells are divided into a plurality of cell groups according to the program speed, and the memory cells are Cell groups corresponding to each may be stored in registers. For example, if the plurality of cell groups include first to third cell groups, the first cell group is designated as fast cells, the second cell group is designated as normal cells, and the third cell group is designated as slow cells, the memory cells are fast. Information about which cell among a cell, a normal cell, and a slow cell corresponds to may be stored. For example, the information may be stored in a register provided inside the program control unit (eg, 160 of FIG. 1 ).

Accordingly, in the second program period P2 PGM and the third program period P3 PGM, after the first program voltages Vpgm12 and Vpg12 are applied, the first program period P1 PGM without a verification read step. Reprogramming may be performed by applying the second program voltages Vpgm22 and Vpgm23 to memory cells other than the first cell group, eg, memory cells classified as fast cells.

24 is a flowchart illustrating another example of a program method according to an embodiment of the present disclosure, and FIGS. 25A to 25C are graphs illustrating threshold voltage distribution of word lines according to respective steps in the flowchart of FIG. 24 . The program method of FIG. 24 shows a program method for reducing a coupling effect between adjacent word lines in the program method according to an embodiment of the present disclosure. The program method of FIG. 24 is a modified example of the program method of FIGS. 5A to 19 . Therefore, the contents described with reference to FIGS. 5A to 19 may be applied to the present embodiment.

Referring to FIG. 24 , an initial program (1st PGM) is performed on the memory cells of the n-th (n is an integer) word line WLn (S610). In this case, the initial program step (1st PGM) may include applying a first program voltage to the memory cells. Accordingly, one-shot distribution of memory cells according to the first program voltage may be formed. In this case, the first program voltage may include a plurality of first program voltages corresponding to each of a plurality of program states corresponding to multi-bit data stored in memory cells. In one embodiment, the plurality of first program voltages may be a voltage set to program less than m memory cells having a relatively high program speed among the memory cells of the nth word line to a corresponding program state. The initial programming step (1st PGM) may include sequentially applying the plurality of first program voltages to the n-th word line WLn. Accordingly, as shown in FIG. 25A , one-shot distribution of memory cells for each program state, for example, the first to third program states P1, P2, and P3 may be formed.

Thereafter, an initial program (1st PGM) is performed on the memory cells of the n+1th word line (WLn+1) (S620). The n+1 th word line WLn+1 is a word line disposed adjacent to the n th word line WLn, and may be a word line in which a program is executed later than the n th word line WLn. A plurality of corresponding first program voltages may be applied to the n+1 th word line WLn+1, and as shown in FIG. 25A for the n+1 th word line, n for each program state. A one-shot distribution of memory cells of the +1 th word line WLn+1 may be formed. In this case, as the memory cells of the n+1 th word line WLn+1 are programmed, a coupling effect may occur in the memory cells of the n th word line WLn. Accordingly, as shown in FIG. 25B , the one-shot distribution corresponding to each program state of the memory cells of the n-th word line WLn may move to the right.

Next, a secondary program (2nd PGM) is performed on the memory cells of the n-th word line WLn (S630). The latter programming step (2nd PGM) includes a step (VF) of dividing the memory cells of the n-th word line (WLn) into a plurality of cell groups having different threshold voltage distribution widths based on the program speed through a verification read; Based on a plurality of secondary program voltages set based on a difference in threshold voltage between cell groups of , excluding some cell groups among the plurality of cell groups, for example, a first cell group programmed to a target state among the plurality of cell groups. A step of reprogramming other cell groups (PGM2) may be included. In one embodiment, a first cell group having the highest threshold voltage distribution among the plurality of cell groups may include m or more than m memory cells.

In one embodiment, the latter programming step (2nd PGM) may further include a verification reading step of determining whether the memory cells of the n-th word line (WLn) are normally programmed to a corresponding programmed state.

According to this embodiment, when performing a program on the n-th word line WLn, an initial program (1st PGM) is performed on memory cells of the n+1-th word line WLn+1 before performing a later program (2nd PGM). By performing a later program (2nd PGM) on the memory cells of the n-th word line WLn based on the one-shot distribution of the memory cells of the n-th word line WLn in which the coupling effect is reflected in advance, It is possible to prevent a shift in distribution of threshold voltages of respective program states due to coupling effects between word lines.

26A and 26B are diagrams illustrating an initial programming step and a later programming step for memory cells of a word line. A case in which 2-bit data is stored in memory cells and memory cells are programmed to first through third program states will be described.

Referring to FIGS. 26A and 26B , first program voltages corresponding to first to third program states are sequentially applied to memory cells of a word line (eg, an n-th word line WLn), so that first to third program voltages are sequentially applied. Initial programs (PGM11, PGM12, PGM13) (1st PGM) corresponding to each program state may be executed.

Thereafter, a later program (2nd PGM) may be performed on the memory cells of the word line. At this time, as shown in FIG. 26A, a verification read step and a reprogramming step for each program state may be sequentially performed. For example, by performing the verify read step (VF_1) and the reprogramming step (eg, the second program step (PGM21)) for the first program state, the programming of the memory cells to be programmed in the first program state is completed, and then, By performing the verification read step (VF_2) and the reprogramming step (eg, the second program step (PGM22)) for the second program state, the programming of the memory cells to be programmed in the second program state is completed, and finally, the second program step (PGM22) is performed. By performing the verification read step (VF_3) and the reprogramming step (eg, the second program step (PGM23)) for the third program state, programming of the memory cells programmed in the third program state may be completed.

As another embodiment, as shown in FIG. 26B , in the latter program stage (2nd PGM), after all of the verification read steps (VF_1, VF2, and VF3) for each program state are performed, a readout for each program state is performed. Program steps (eg, second program steps PGM21, PGM22, and PGM3 for each program state) may be performed.

27 is a flowchart illustrating another example of a program method according to an embodiment of the present disclosure. The programming method of FIG. 27 is similar to the programming method according to FIGS. 25A to 25C. However, as shown in FIG. 14A, in the step of dividing memory cells into a plurality of cell groups according to the program speed, when the memory cells are divided into at least 5 cell groups, as shown in FIG. 27, the later programming step A plurality of verification read steps and a plurality of reprogramming steps may be included.

28 illustrates a method of programming a memory cell array according to an embodiment of the present disclosure. In one embodiment, the memory cell array may include a two-dimensional memory cell array.

Referring to FIG. 28 , the memory cell array may include a plurality of memory blocks including a plurality of word lines, for example, first to eighth word lines WL1 to WL8. In one embodiment, the first to eighth word lines WL1 to WL8 may be sequentially disposed adjacent to each other, and a program may be performed in order from the first word line WL1 to the eighth word line WL8. there is.

At this time, in order to reduce the coupling effect that occurs as a program is performed on an adjacent word line, as described above with reference to FIG. 24, when a program is performed on one word line, an adjacent After an initial program (1st PGM) is performed on a word line, a later program (2nd PGM) may be performed on the word line.

For example, initial programming (1st PGM) may be performed on the memory cells of the first word line WL1, and initial programming (1st PGM) may be performed on the memory cells of the second word line WL2. Thereafter, the programming of the memory cells of the first word line WL1 may be completed by performing a later program (2nd PGM) on the memory cells of the first word line WL1.

Next, after the initial program (1st PGM) is performed on the third word line (WL3) and the later program (2nd PGM) is performed on the second word line (WL2), the second word line (WL2) A program for memory cells may be completed.

In this way, programming may be sequentially performed on all word lines, for example, the first to eighth word lines WL1 to WL8.

29 is a graph showing program speed for each word line.

The horizontal axis represents the word line number, and the vertical axis represents the threshold voltage for each word line when a one-shot voltage pulse is applied to program memory cells to a predetermined state, for example, a preprogram state. It can be determined that the higher the threshold voltage, the faster the program speed.

As shown in FIG. 29, the program speed may differ for each word line. Also, even for the same word line, the program speed may vary depending on the program cycle. As shown in FIG. 29 , the program speed of the word line may increase as the number of program cycles, i.e., program and erase counts, increases.

If the difference in programming speed for each word line is large, a distribution width of each program state of programmed memory cells may increase. Therefore, compensation of program speed is necessary.

30 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 30 , the memory device ( 100 of FIG. 1 ) may receive multi-bit data and a program command from an external device, for example, a memory controller (S710). The memory device may detect a program speed of a word line corresponding to an address where a program is to be executed (S720).

In one embodiment, the memory device may sense a program speed of the word line by applying a pre-program voltage to a word line on which a program is to be executed and counting the number of off-cells programmed in a pre-program state.

The memory device may set the voltage levels of the program voltages by reflecting the detected program speed of the word line and compensating for the program speed of each word line (S730). For example, if the program speed of the word line is different from the reference value, a compensation voltage set corresponding to the difference between the detected program speed and the reference value may be added to the default level of the program voltages.

Meanwhile, as shown in FIG. 22, the voltage levels of the program voltages are set based on the first program voltages Vpgm11, Vpgm12, and Vpgm13 for each program state, and the first program voltage Vpgm12 for the second program state. The voltage level of ) may be set based on the primary program voltage Vpgm11 for the first program state. Accordingly, when setting the voltage level of the first program voltage Vpgm11 for the first program state, the voltage level of the program voltages compensated for the program speed for each word line may be set by reflecting the compensation voltage according to the program speed. Accordingly, a program voltage set for each program state may be set. The program voltage set may include a first program voltage and a plurality of second program voltages.

Thereafter, a program for each program state may be performed according to the voltage levels of the program voltages in which the program speed is reflected. The memory cells may be programmed into an n-th program state based on the set of n-th program voltages (S740). For example, when memory cells are programmed in first to third program states, the memory cells may be programmed in first to third program states based on first to third program voltage sets.

31 is a diagram explaining a method of detecting a program speed of a word line and compensating for a program voltage level according to an embodiment of the present disclosure.

Referring to FIG. 31 , in order to detect the program speed of the word line, the memory device may apply a one-shot pre-program voltage to the word line, thereby programming the memory cells of the word line to a pre-program state P0. . In this case, the memory device may detect the program speed of the word line by counting the number of memory cells programmed to the pre-program state P0, that is, the number of offcells for the pre-program state P0.

The pre-program state P0 may be a state located between the erase state E and the first program state P1. The pre-program state P0 is not a state corresponding to multi-bit data stored in memory cells, and may be an arbitrary state for detecting a program speed of a word line.

The counted number of offcells in the pre-program state may correspond to the program speed of the word line. The larger the number of offcells, the faster the program speed. The memory device may determine a program speed based on the number of off cells, and may apply a compensation voltage corresponding to the program speed when setting voltage levels of the program voltages.

In one embodiment, a memory device, for example, a program controller (160 in FIG. 1 ) may include a table storing compensation voltages according to the number of off cells. The memory device may select a compensation voltage according to the counted number of offcells with reference to the table, and apply the compensation voltage when setting a program voltage level.

For example, as shown in FIG. 31 , a compensation voltage may be applied when a program start voltage is set. For example, the program start voltage may be the primary program voltage Vpgm11 in the first program state. The voltage level of the primary program voltage Vpgm11 in the first program state may be set by adding the compensation voltage VoffWL according to the program speed of the word line to the program start voltage Vdf1 of the default level.

32 is a diagram illustrating a method of setting a program voltage level by reflecting a program speed of a word line according to an embodiment of the present disclosure.

Referring to FIG. 32 , in the pre-program step P0 PGM, a pre-program voltage is applied to memory cells, and the number of off-cells in a pre-program state is counted through a verification read, so that the program speed of the word line can be sensed. . Thereafter, in each program step (P1 PGM, P2 PGM, P3 PGM), the compensation voltage may be applied when setting a set of program voltages corresponding to each program step. For example, when setting the first program voltages Vpgm11, Vpgm12, and Vpgm13 in each program step, the compensation voltage may be applied.

33A to 33C are graphs illustrating threshold voltage distributions of word lines in each step of a program method according to an embodiment of the present disclosure.

The program method shown in FIGS. 33A to 33C is a modified example of the program method shown in FIG. 24 . 33A and 33B, an initial program (1st PGM) is performed on the memory cells of the n-th word line WLn, and then an initial program (1st PGM) on the memory cells of the n+1-th word line WLn. 1st PGM) may be performed. In this case, the initial program step may include a pre-program step (PGM0), a pre-read verify step (VF0), and a step of applying a primary program voltage corresponding to each program step (PGM1) to memory cells. In the pre-program step PGM0, the pre-program voltage is applied to the memory cells, and in the pre-read verify step VF0, the number of off-cells in the pre-program state is counted, thereby detecting the program speed of the word line. . A voltage level of the program voltage set for each program step may be set based on the compensation voltage according to the detected program speed of the word line. For example, a compensation voltage may be added to the voltage level of the first program voltage corresponding to each program stage. Thereafter, a one-shot distribution corresponding to each of the programmed states is formed by applying a primary program voltage according to each program stage to which a compensation voltage according to the program speed of the word line is added to the memory cells to which the pre-program voltage has been applied. can

Thereafter, as shown in FIG. 33 , programming of the memory cells of the n-th word line WLn may be completed by performing the latter program (2nd PGM) on the n-th word line WLn. The latter programming step (2nd PGM) includes a step (VF) of dividing the memory cells of the n-th word line (WLn) into a plurality of cell groups having different threshold voltage distribution widths based on the program speed through a verification read; Based on a plurality of secondary program voltages set based on a difference in threshold voltage between cell groups of , excluding some cell groups among the plurality of cell groups, for example, a first cell group programmed to a target state among the plurality of cell groups. A step of reprogramming other cell groups (PGM2) may be included. In this case, the plurality of secondary program voltages may be set based on a difference in threshold voltage between the plurality of groups and a compensation voltage according to a program speed of the word line.

34 is a flowchart illustrating a method of operating a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 34 , memory cells may be programmed to an N−1th programmed state (N is an integer greater than or equal to 2) (S810). The N−1th program state may be a program state excluding the highest program state having the highest threshold voltage among a plurality of program states.

After the memory cells are programmed to the N−1 th program state or while being programmed to the N−1 th state, the program speed of the word line may be detected (S820). In an embodiment, during a verify read operation for the N−1 th program state, the program speed may be detected by counting the number of off cells. For example, when the memory cells are divided into a plurality of cell groups after performing the first program on the memory cells, the number of memory cells of the first cell group having the highest threshold voltage level among the plurality of cell groups is counted. The program speed of the line can be detected.

A program voltage for an Nth program state, for example, a voltage level of an Nth program voltage set may be set based on the compensation voltage according to the program speed of the detected word line (S830). In other words, the compensation voltage according to the program speed of the word line corresponding to the N−1th program state may be reflected in the Nth program voltage set.

Accordingly, the memory cells may be programmed into the Nth program state based on the Nth program voltage set in which the compensation voltage according to the program speed of the word line corresponding to the N−1th program state is reflected (S840).

In one embodiment, the flowchart of FIG. 34 shows an operation method performed after step S730 of FIG. 30 .

According to steps S720 and S730 of FIG. 30 described above, before performing programming on memory cells, the program speed of the word line may be detected, and accordingly, a program voltage level compensated for the program speed of the word line may be set. Thereafter, according to steps S810 and S840 of FIG. 34 , the program speed of the word line may be detected for each program loop, and the program speed may be reflected in the program voltage of the next program loop based on the program speed.

Referring to FIG. 30 , the memory device may detect a program speed (eg, an initial program speed) of a word line before performing programming on memory cells, and adjust voltage levels of program voltages based on the program speed for each word line. . Accordingly, the program speed for each word line may be compensated. However, as the program is executed, the program speed of the word line may change and the program distribution may increase. According to the operating method according to the present embodiment, program distribution characteristics can be improved by detecting the program speed of the word line in each program loop and reflecting the compensation voltage according to the program speed to the program voltage of the next program loop.

35 is a diagram illustrating a method of detecting a program speed of a word line during program execution.

35 is a method for detecting a program speed of a word line when memory cells are divided into a plurality of cell groups according to program speeds and programmed according to the programming method according to the embodiment of the present disclosure described above with reference to FIGS. 5A to 19 . indicates

Referring to FIG. 35 , when memory cells are programmed to the first program state P1 , the first program voltage Vpgm11 may be applied to the memory cells. In this case, some of the memory cells, for example, memory cells in an upper region of the one-shot distribution may be included in the target distribution of the first program state P1.

Verification read may be performed to divide the memory cells into three cell groups. At this time, the program speed of the word line may be sensed by counting the number of offcells for the first program state P1. For example, the off-cells in the first program state P1 may be cells included in the first cell group MCG1.

Thereafter, memory cells other than the off-cells, for example, memory cells of the second cell group MCG2 and the third cell group MCG3 are reprogrammed. Accordingly, all of the memory cells are programmed to the first program state P1. Afterwards, some of the memory cells may be programmed to the second program state P2. At this time, a program voltage level for the second program state P2 may be set. The voltage level of the program voltages for the second program state P2, for example, the voltage level of the second program voltage set, may be set based on the compensation voltage according to the program speed detected during programming of the first program state P1. there is.

The first program voltage Vpgm12 of the second program state P2 may be set by adding the second program offset VoffP2 to the first program voltage Vpgm11 of the first program state P1. At this time, the program speed A compensation voltage VoffWL according to may be additionally added. Accordingly, the program speed of the word line sensed during the program execution of the first program state P1 may be reflected in the voltage levels of the program voltages of the second program state P2.

According to the above-described operating method, that is, the program method, according to an embodiment of the present disclosure, the program speed of a word line is detected in every program loop, and the detected program speed is reflected in the program voltage of the next program loop to perform a program. By doing so, the distribution characteristics of each program state can be improved.

36 illustrates an embodiment of a method of operating a memory device according to an embodiment of the present disclosure.

Referring to FIG. 36 , the program speed of the word line may be detected in every program loop. When the memory cell is a multi-level cell storing 2-bit data, the memory cell may be programmed into one of first to third program states P1, P2, and P3.

Prior to performing programming on memory cells, first program speed detection (SPD1) may be performed. Voltage levels of program voltages corresponding to the first program state P1, for example, the first program voltage ( Vpgm11) can be regulated.

Thereafter, during program execution for the first program state P1, secondary program speed detection (SPD2) is performed in the verification read (VF) step, and the program speed of the word line according to the secondary program speed detection (SPD2) is determined. Accordingly, voltage levels of program voltages corresponding to the second program state P2 may be adjusted. For example, the voltage level of the first program voltage Vpgm12 of the second program state P2 may be adjusted.

During the execution of the program for the second program state P2, in the verification read step VF, the tertiary program speed detection SPD3 may be performed. Voltage levels of program voltages corresponding to the tertiary program state P3 may be adjusted according to the program speed of the word line according to the tertiary program speed detection SPD3. For example, the voltage level of the first program voltage Vpgm13 of the third program state P3 may be adjusted.

37 is a flowchart illustrating in detail a method of operating a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 37 , first program speed detection for a word line may be performed (S910). The detection of the first program speed may be performed before programming of memory cells is performed, and a program voltage level for a first program state may be set based on the detected program speed (S920).

For example, the first compensation voltage VoffWL1 according to the program speed may be reflected in the first program voltage Vpgm11 of the first program state P1.

By applying the primary program voltage Vpgm11 of the first program state P1 to the memory cells, the memory cells may be primarily programmed with the first program state as a target (S930).

Thereafter, the memory cells may be divided into three cell groups according to the program speed based on the threshold voltages of the memory cells (S940). At this time, secondary program speed detection for the word line may be performed (S950). When the memory cells are divided into three cell groups according to the program speed, the first cell group corresponding to the highest state in the threshold voltage region may be included in the target distribution of the first program state P1. A program speed may be detected by counting the number of memory cells included in the first cell group.

Thereafter, the program for the first program state P1 is continuously performed. Reprogramming (eg, a second program or a third program) may be performed on the memory cells so that the distribution of the cell groups is included in the target distribution of the first program state P1. Accordingly, the memory cells may be programmed to the first program state P1.

After the programming of the first program state P1 is completed, voltage levels of program voltages for the second program state may be set based on the program speed of the word line according to the detection of the second program speed (S970). For example, the second compensation voltage VoffWL2 according to the program speed may be added to the first program voltage Vpgm12 of the second program state P2.

By applying the primary program voltage Vpgm12 of the second program state P2 to the memory cells, the memory cells may be primarily programmed with the second program state P2 as a target. Then, as described above, the program speed of the word line is sensed in each program step, and accordingly, the voltage levels of program voltages in the next program step may be adjusted.

38 is a block diagram illustrating an example of a program control unit according to an embodiment of the present disclosure.

In one embodiment, the program controller 160a may be included in the control logic ( 150 in FIG. 1 ). In another embodiment, the program controller 160a may be implemented as a separate functional block.

Referring to FIG. 38 , the program controller 160a may include a program control logic 160-1 and a register 160-2. The program control logic 160-1 may perform an operation of setting driving voltages for a program operation, and may store voltage levels of the set driving voltages in the register 160-2. In addition, the program control logic 160-1 may perform an operation of setting compensation voltages according to the program speed of word lines and store the set compensation voltages for each word line in the register 160-2.

In one embodiment, driving voltages and compensation voltages for each word line may be stored in the register 160-2 in the form of a table. The register 160-2 includes a first table TB1 including voltage levels of driving voltages, for example, default levels of driving voltages, and a second table TB2 including compensation voltage levels according to program speeds of word lines. can do.

In an embodiment, the program control logic 160 - 1 may set default levels of driving voltages before a write request command is received from the memory controller (eg, an initialization period of the memory device, a training period, etc.). Then, when a program command is received, the program speed of the word line to be programmed may be detected, and the level of the compensation voltage VoffWL according to the program speed may be determined.

The voltage levels of the driving voltages stored in the first table TB1 may be default levels. When a program is performed for each word line, the driving voltages may be compensated by applying the compensation voltage VoffWL to the residual driving voltages of a default level.

For example, when multi-bit data and a program command are received from the memory controller, the program controller 160 senses the program speed of the word line, and the control logic 160-1 accesses the register 160-2, Voltage levels of corresponding driving voltages may be set based on the driving voltages of the first table TB1 and the compensating voltage according to the program speed of the second table TB2. Also, according to an embodiment of the present disclosure, the program control unit 160 detects the program speed of the word line during program execution, and based on the detected program speed, a compensation voltage according to the program speed of the second table TB2. , driving voltages for the next program state, for example, voltage levels of the program voltages may be set. In addition, a program control signal (CTRL_PGM) indicating the voltage level of the driving voltage may be generated and provided to the voltage generator (140 in FIG. 1).

The configuration and functions of the program control unit included in the memory device have been described above with reference to FIG. 38 . However, the above description is only an example, and the technical spirit of the present disclosure is not limited thereto. The driving voltages and compensation voltages stored in the register 160-2 may have various forms. Also, the program control unit may perform more various functions of controlling the memory device so that a program may be performed on the memory cell array according to the program method according to example embodiments.

39 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

The memory system 1000 includes a computer, a laptop, a cellular phone, a smart phone, an MP3 player, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital It can be mounted on electronic devices such as TVs, digital cameras, portable game consoles, and the like.

Referring to FIG. 39 , a memory system 1000 may include a memory device 100 and a memory controller 200 . The memory device 100 may include a memory cell array 110 , a control logic 150 and a program controller 160 .

The memory cell array 110 may include a plurality of memory cell blocks and may store data received from a memory controller.

The control logic 150 may generally control various operations within the memory device 100 based on the command CMD, address ADDR, and control signal CTRL received from the memory controller 200 . For example, the control logic 150 may output various control signals for writing data to or reading data from the memory cell array 110 .

The program controller 160 may control the memory device 100 to store multi-bit data in the memory cell array 110 . The program control unit 160 divides memory cells set to be programmed in one program state into at least three cell groups according to program speeds, and applies different program voltages or program numbers to each cell group to determine the memory cells. The memory device 100 may be controlled so that cells may be programmed. The program control unit 160 may also detect a program speed for each word line and adjust voltage levels of program voltages of each program state applied to the word line based on a compensation voltage according to the program speed. The program controller 160 may detect a program speed in each program loop and adjust voltage levels of program voltages for the next program loop based on a compensation voltage according to the detected program speed. In addition, when performing a program on one word line, the program control unit 160 performs a program to perform an initial program on the word line, an initial program on an adjacent word line, and then a later program on the word line. By setting the sequence, coupling effects between adjacent word lines can be reduced. In addition, the program control unit 160 controls each component of the memory device 100, for example, to execute a program according to the programming method of the memory device according to an embodiment of the present disclosure described with reference to FIGS. 5A to 38 . Row decoders, input/output circuits, voltage generators, etc. can be controlled.

The memory controller 200 may control the memory device 100 to read data stored in the memory device 100 or write data to the memory device 100 in response to a read/write request from the host HOST. there is. Specifically, the memory controller 200 provides an address ADDR, a command CMD, and a control signal CTRL to the memory device 100 to program (or write), read, and erase the memory device 100 . You can control the action. The memory controller 200 may transmit data DATA for a program operation to the memory device 100 . The memory controller 200 provides data DATA having a size corresponding to a program unit of the memory device 100, an address ADDR where the data is stored, and a command CMD indicating a write request to the memory device 100. can do.

Although not shown, the memory controller 200 may include RAM, a processing unit, a host interface, and a memory interface. The RAM may be used as an operating memory of the processing unit, and the processing unit may control the operation of the memory controller 200 . The host interface may include a protocol for exchanging data between the host and the memory controller 200 . For example, the memory controller 200 uses various interface protocols such as USB, MMC, PCI-E, ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI, ESDI, and IDE (Integrated Drive Electronics). It may be configured to communicate with the outside (HOST) through at least one of them.

Meanwhile, in another embodiment, some functions of the program controller 160 may be performed by the memory controller 200 . For example, the memory controller 200 may control a program operation of the memory cell array 110 of the memory device 100 . In an embodiment, the memory controller 200 may also determine a sequence to which the program method according to embodiments of the present disclosure is applied, and provide a control signal CTRL indicating the sequence to the memory device 100. can

For example, a control signal CTRL for controlling setting of driving voltages for a program operation may be provided to the memory device 100 . In addition, the memory controller 200 may determine distribution characteristics of the memory cell array 110 and, based on the determination result, determine how many cell groups to classify memory cells into according to program speed during program execution. For example, when it is determined that distribution characteristics are poor due to deterioration of memory cells in a portion of the memory cell array 110, when a program operation is performed on the memory cells in the area, the number of cell groups classified according to the program speed. By increasing , it is possible to improve the distribution characteristics of the program state.

As such, the memory controller 200 may control the memory device 100 to improve the programming speed of the memory device 100 or the distribution characteristics of memory cells in a programmed state.

40 is a block diagram illustrating a memory card system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 40 , a memory card system 2000 may include a host 2100 and a memory card 2200 . The host 2100 may include a host controller 2110 and a host connection unit 2120 . The memory card 2200 may include a card connector 2210 , a card controller 2220 and a memory device 2220 .

The host 2100 may write data to the memory card 2200 or read data stored in the memory card 2200 . The host controller 2110 may transmit a command CMD, a clock signal CLK generated from a clock generator (not shown) in the host 2100, and data DATA to the memory card 2200 through the host interface 2120. there is.

The card controller 2220 may store data in the memory device 2220 in synchronization with a clock signal generated by a clock generator (not shown) in the card controller 2220 in response to a command received through the card connector 2210. there is. The memory device 2220 may store data transmitted from the host 2100 . The memory device 2220 may include the memory device 100 of FIG. 1 described above with reference to FIG. 1 , and the memory device 2220 may include a program according to an embodiment of the present disclosure described with reference to FIGS. 5A to 38 . Data DATA received from the card controller 2110 may be stored in a memory cell array according to a method or operation method. The time to program data can be shortened, and the operating speed of the memory card 2200 and the memory card system 2000 can be improved as program distribution characteristics are improved.

The memory card 2220 includes a compact flash card (CFC), a microdrive, a smart media card (SMC), a multimedia card (MMC), and a security digital card (SDC). Card), memory stick, and USB flash memory driver.

41 is a block diagram illustrating a computing system according to an embodiment of the present disclosure.

Referring to FIG. 41 , a computing system 3000 may include a memory system 3100, a processor 3200, a RAM 3300, an input/output device 3400, and a power supply 3500. Meanwhile, although not shown in FIG. 19 , the computing system 3000 may further include ports capable of communicating with video cards, sound cards, memory cards, USB devices, etc., or with other electronic devices. . The computing system 3000 may be implemented as a personal computer or as a portable electronic device such as a notebook computer, a mobile phone, a personal digital assistant (PDA), and a camera.

Processor 3200 may perform certain calculations or tasks. Depending on the embodiment, the processor 3200 may be a micro-processor or a central processing unit (CPU). The processor 3200 communicates with the RAM 3300, the input/output device 3400, and the memory system 3100 through a bus 3600 such as an address bus, a control bus, and a data bus. communication can be performed. According to an embodiment, the processor 3200 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

The memory system 3100 may communicate with the processor 3200 , the RAM 3300 , and the input/output device 3500 through the bus 3600 . The memory system 3100 may store received data or provide stored data to the processor 3200, the RAM 3300, or the input/output device 3400 according to a request of the processor 3200. Meanwhile, the memory system 1000 described with reference to FIG. 39 may be applied to the memory system 3100 . Alternatively, the memory system 3100 may include the memory device 100 described with reference to FIG. 1 , and the memory device 3110 may include a program method or operation according to embodiments of the present disclosure described with reference to FIGS. 5A to 38 . Depending on the method, data DATA received from the memory controller 3120 may be stored in the memory cell array. Accordingly, the time to program data can be shortened, and program distribution characteristics can be improved, so that the operating speed of the memory system 3100 and the computing system 3000 can be improved.

The RAM 3300 may store data necessary for the operation of the computing system 3000 . For example, the RAM 3300 may be implemented as DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and/or MRAM. .

The input/output device 3400 may include input means such as a keyboard, keypad, and mouse, and output means such as a printer and a display. The power supply 3500 may supply an operating voltage necessary for the operation of the computing system 2000 .

42 is a block diagram illustrating an SSD system according to an embodiment of the present disclosure.

Referring to FIG. 42 , an SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector and receives power through a power connector.

The SSD 4200 may include an SSD controller 4210, an auxiliary power supply 4220, and a plurality of memory devices 4230, 4240, and 4250. The plurality of memory devices 4230, 4240, and 4250 may be vertically stacked NAND flash memory devices. At least one of the plurality of memory devices 4230 , 4240 , and 4250 may include the memory device 100 described with reference to FIG. 1 . Specifically, at least one of the plurality of memory devices 4230, 4240, and 4250 is received from the SSD controller 4210 according to the program method or operation method according to the embodiment of the present disclosure described with reference to FIGS. 5A to 38 The data DATA may be stored in the memory cell array. Accordingly, the time to program data may be shortened, and program distribution characteristics may be improved, thereby improving operating characteristics of the SSD 4200 .

43 is a block diagram illustrating a uiversal flash storage (UFS) according to an embodiment of the present disclosure.

Referring to FIG. 43 , a UFS system 5000 may include a UFS host 5100, UFS devices 5200 and 5300, an embedded UFS device 5400, and a removable UFS card 5500. The UFS host 5100 may be an application processor of a mobile device. Each of the UFS host 5100, the UFS devices 5200 and 5300, the embedded UFS device 5400, and the removable UFS card 5500 may communicate with external devices through the UFS protocol. At least one of the UFS devices 5200 and 5300 , the embedded UFS device 5400 , and the removable UFS card 5500 may include the memory device 100 shown in FIG. 1 . In addition, at least one of the UFS devices 5200 and 5300, the embedded UFS device 5400, and the removable UFS card 5500 may be applied with the program method according to the embodiments of the present disclosure described with reference to FIGS. 5A to 38. can Accordingly, the operating speed of the UFS system 5000 can be improved.

Meanwhile, the embedded UFS device 5400 and the removable UFS card 5500 may communicate by a protocol other than the UFS protocol. The UFS host 5100 and the removable UFS card 5500 can communicate through various card protocols (eg, UFDs, MMC, SD, mini SD, Micro SD, etc.).

A memory card, a non-volatile memory device, and a card controller according to embodiments of the present disclosure may be mounted using various types of packages. For example, a flash memory device and/or memory controller according to the present disclosure may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package ( WSP), etc. can be mounted using packages such as

Although the present disclosure has been described with reference to the embodiments shown in the drawings, this is only exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

1000: memory system
100: memory device
200: memory controller
160: program control unit

Claims (10)

A method of programming a non-volatile memory device including memory cells storing multi-bit data, the method comprising:
programming memory cells of an n-th word line based on a plurality of primary program voltages corresponding to the n-th word line;
After programming the memory cells of the n-th word line, memory cells of the n+1-th word line adjacent to the n-th word line are programmed based on a plurality of primary program voltages corresponding to the n+1-th word line. programming; and
After programming the memory cells of the n+1 th word line, the memory cells of the n th word line are divided into a plurality of cell groups according to program speed based on threshold voltage distribution, and reprogramming memory cells of the n-th word line based on a plurality of secondary program voltages set based on a threshold voltage difference;
Reprogramming the memory cells of the n-th word line may include:
and programming memory cells of cell groups other than the cell group corresponding to the uppermost region of a threshold voltage distribution among the plurality of cell groups of the n-th word line based on the plurality of secondary program voltages. How to program a memory device. According to claim 1,
The plurality of primary program voltages corresponding to the n-th word line are set corresponding to each of a plurality of program states corresponding to the multi-bit data;
The step of programming the memory cells of the n-th word line based on the plurality of primary program voltages,
and sequentially applying the plurality of primary program voltages to memory cells of the n-th word line. 3. The method of claim 2, wherein the plurality of program states include first to third program states,
The program method of a nonvolatile memory device, wherein the plurality of primary program voltages are set corresponding to each of the first to third program states. 3. The method of claim 2, wherein programming the memory cells of the n-th word line based on the plurality of primary program voltages comprises:
applying a first primary program voltage corresponding to a first program state among the plurality of primary program voltages to the n-th word line; and
and applying a second primary program voltage corresponding to a second program state among the plurality of primary program voltages to the n-th word line. The method of claim 1 , wherein the reprogramming of the memory cells of the n-th word line comprises:
dividing memory cells of the n-th word line into a plurality of cell groups corresponding to a plurality of program states corresponding to the multi-bit data; and
Based on the plurality of secondary program voltages for each of the plurality of program states, which is set based on a difference in threshold voltage between the plurality of cell groups for each of the plurality of program states, memory cells of the nth word line are A method of programming a non-volatile memory device comprising the step of reprogramming. The method of claim 5, wherein the dividing into a plurality of cell groups comprises:
classifying memory cells of the n-th word line to which a first program voltage corresponding to a first program state is applied, among memory cells of the n-th word line, into a plurality of cell groups corresponding to the first program state;
and dividing memory cells of the n-th word line to which a second primary program voltage corresponding to a second program state is applied, among memory cells of the n-th word line, into a plurality of cell groups for the second program state. A method of programming a non-volatile memory device to be used. The method of claim 1 , wherein the reprogramming of the memory cells of the n-th word line comprises:
Among the memory cells of the n-th word line, first memory cells to which a first primary program voltage corresponding to a first program state is applied are divided into a plurality of first cell groups, and based on the first secondary program voltage reprogramming memory cells of the remaining cell groups except for the cell group corresponding to the uppermost region of the threshold voltage distribution among the plurality of first cell groups with; and
Among the memory cells of the n-th word line, second memory cells to which a second primary program voltage corresponding to a second program state is applied are divided into a plurality of second cell groups, based on the second secondary program voltage. and reprogramming memory cells of a cell group other than a cell group corresponding to an uppermost region of a threshold voltage distribution among the plurality of second cell groups with the method. According to claim 2,
When the plurality of primary program voltages corresponding to the n-th word line are set to program less than m memory cells having a relatively high program speed among the memory cells of the n-th word line, respectively, to a corresponding target state. ,
A first cell group having the highest threshold voltage among the plurality of cell groups of the n-th word line includes m memory cells. According to claim 1,
detecting an initial program speed of the n-th word line; and
and adjusting a voltage level of the plurality of primary program voltages corresponding to each of a plurality of program states corresponding to the multi-bit data based on the initial program speed. 10. The method of claim 9, wherein the detecting of the initial program speed of the n-th word line comprises:
applying a preprogram voltage to the nth word line; and
A method of programming a non-volatile memory device, comprising counting the number of memory cells detected as off-cells in a pre-program state.

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