KR20230041582A - Storage device, non-volatile memory, and operating mehtod of non-volatile memory - Google Patents

Abstract

A nonvolatile memory device, a storage device including the same, and a program operating method of the nonvolatile memory are disclosed. The program operating method of a nonvolatile memory according to the technical idea of the present disclosure includes the steps of: performing a first program loop, wherein the first program loop applies a first program voltage; sensing a first sensing value corresponding to an output based on a first verification voltage; and counting the number of on-cells based on the first sensing value, determining whether the first program state passes according to a result of comparing the first count value and the reference value, and setting a second program voltage in a second program loop.

Description

Storage device, non-volatile memory, program operation method of non-volatile memory

The technical idea of the present disclosure relates to an electronic device, a storage device, a non-volatile memory, and a program operating method of the non-volatile memory.

Semiconductor memory devices may be classified into volatile memories such as DRAM and SRAM and non-volatile memories such as EEPROM, FRAM, PRAM, MRAM, and flash memories. A volatile memory device loses stored data when power supply is cut off, whereas a non-volatile memory device retains stored data even when power is cut off.

Devices using non-volatile memory include, for example, an MP3 player, a digital camera, a mobile phone, a camcorder, a flash card, and a solid state disk (SSD). As the number of devices using non-volatile memory as a storage device increases, the capacity of the non-volatile memory is also rapidly increasing.

As a program method, a program operation based on an increment step pulse program (ISPP) method may be used, and after a program voltage pulse is applied to memory cells, a program state of memory cells may be verified using a verification voltage. Accordingly, research to reduce the total program time is increasing.

The technical spirit of the present disclosure provides a storage device, a non-volatile memory, and a program operation method of the non-volatile memory for improving the speed of a program operation.

A program operation method of a nonvolatile memory according to the technical idea of the present disclosure includes performing at least one program loop on a plurality of memory cells, and a first program loop of the at least one program loop applies a first program voltage. Step, a verification step of sensing a first sensing value corresponding to an output based on a first verification voltage, and counting the number of on cells based on the first sensing value, and measuring the first count value and at least one reference and a pass checking step of comparing the values, determining whether the first program state has passed according to the comparison result, and setting a second program voltage in a second program loop after the first program loop.

In addition, a nonvolatile memory according to the technical concept of the present disclosure is connected to the memory cell array through a memory cell array including a plurality of memory cells, a plurality of word lines, and applies a voltage to a selected word line among the plurality of word lines. A voltage generator connected to the memory cell array through a plurality of bit lines, a page buffer circuit configured to sense a sensed value through each bit line, and a control logic configured to perform at least one program loop on the plurality of memory cells. wherein the control logic performs a first program loop of the at least one program loop, controls the voltage generator to apply a first program voltage in the first program loop, and performs a first verification in the first program loop. Control a voltage generator to apply voltage, control a page buffer circuit to sense a first sensed value corresponding to an output based on a first verification voltage, and count the number of on cells based on the first sensed value and compares the first count value with at least one reference value stored in advance, determines whether the first program state passes or not according to the comparison result, and sets a second program voltage in a second program loop after the first program loop. do.

In addition, a program operating method of a nonvolatile memory according to the technical idea of the present disclosure performs a first program loop on a plurality of single-level cells, and the first program loop generates a first program voltage. A program step of applying, a verification step of sensing a first sensing value corresponding to an output based on the first verification voltage, and counting the number of on cells based on the first sensing value, and calculating the first count value and a plurality of and a pass confirmation step of comparing reference ranges of , determining whether the program state passes according to the comparison result, and setting a second program voltage in a second program loop after the first program loop.

In addition, a storage device according to the technical idea of the present disclosure includes a memory controller and a non-volatile memory, and the non-volatile memory is connected to the memory cell array through a memory cell array including a plurality of memory cells and a plurality of word lines. , a voltage generator for providing a voltage to a selected word line among a plurality of word lines, a page buffer circuit connected to the memory cell array through a plurality of bit lines and sensing a sensed value through each bit line, and a plurality of memory cells. and control logic configured to perform at least one program loop for the voltage generator to perform a first program loop of the at least one program loop and to apply a first program voltage in the first program loop. Controls the voltage generator to apply a first verification voltage in the first program loop, controls the page buffer circuit to sense a first sensing value corresponding to an output based on the first verification voltage, and controls the first sensing The number of on-cells is counted based on the value, the first count value is compared with at least one reference value stored in advance, and whether or not the first program state passes is determined according to the comparison result, and after the first program loop Set the second program voltage in the second program loop of

According to the technical idea of the present disclosure, there is an effect of improving the speed of program operation.

Effects obtainable from the embodiments of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned above can be obtained from the following description to those of ordinary skill in the art to which the embodiments of the present disclosure belong. can be clearly derived and understood. That is, unintended effects according to the implementation of the embodiments of the present disclosure may also be derived by those skilled in the art from the embodiments of the present disclosure.

1 is a diagram for explaining a storage device according to an exemplary embodiment of the present disclosure.
2 is a diagram for explaining a non-volatile memory according to an embodiment of the present disclosure.
3 is a circuit diagram illustrating a memory block according to an exemplary embodiment of the present disclosure.
4 is a circuit diagram illustrating a memory block according to another exemplary embodiment of the present disclosure.
FIG. 5 is a perspective view illustrating a memory block according to the circuit diagram of FIG. 4 .
6 is a timing diagram illustrating a method of applying a program voltage in a program operation according to an embodiment of the present disclosure.
7 is a timing diagram illustrating a method of applying a verification voltage in a program operation according to an embodiment of the present disclosure.
8A, 8B, and 8C are diagrams illustrating threshold voltage distributions of memory cells according to an exemplary embodiment of the present disclosure.
9 is a flowchart illustrating a method of operating a program in a first program loop according to an embodiment of the present disclosure.
10 is a flowchart for specifically explaining a program operation method according to another embodiment of the present disclosure.
11 is a diagram for explaining a method of counting on-cells according to an embodiment of the present disclosure.
12 is a diagram for explaining an embodiment of a method of operating a program for a single-level cell.
13 is a diagram for explaining another embodiment of a method of operating a program for a single-level cell.
14 is a diagram for explaining another embodiment of a method of operating a program for a single-level cell.
15 is a block diagram illustrating a computing system according to an embodiment of the present disclosure.
16 is a block diagram illustrating a solid state device of a computing system according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a diagram for explaining a storage device 100 according to an embodiment of the present disclosure.

Referring to FIG. 1 , a storage device 100 may include a memory controller 110 and a non-volatile memory 120 .

The memory controller 110 reads data DATA stored in the non-volatile memory 120 in response to a write/read request from the host, or writes (or programs) the data DATA into the non-volatile memory 120. The non-volatile memory 120 may be controlled to Specifically, the memory controller 110 controls program, read, and erase operations of the nonvolatile memory 120 by providing a command/address (CMD/ADD) and a control signal (CTRL) to the nonvolatile memory 120 . can do. Also, data to be written and read data may be transmitted and received between the memory controller 110 and the nonvolatile memory 120 .

The memory controller 110 may communicate with an external host through various standard interfaces. For example, the memory controller 110 includes an interface circuit (not shown), and the interface circuit may provide various standard interfaces between a host and the memory controller 110 . Standard interfaces include advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI-E (PCI express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi media card), eMMC (embedded multi media card), universal flash storage (UFS), CF (compact flash) It may include various interface methods such as a card interface.

The non-volatile memory 120 may be a flash memory device including flash memory cells. However, it is not limited thereto. In describing embodiments of the present disclosure below, it is assumed that the non-volatile memory 120 is a flash memory device including flash memory cells. A flash memory cell may be referred to as a memory cell.

The non-volatile memory 120 may include a memory cell array. The memory cell array may include a plurality of memory cells disposed in regions where a plurality of word lines and a plurality of bit lines intersect. Memory cells may have multiple threshold voltage distributions according to programmed data. For example, when memory cells are single-level cells (hereinafter referred to as SLCs) storing one bit per memory cell, the memory cells may have two threshold voltage distributions according to a program state. For another example, if the memory cells are multi-level cells (hereinafter referred to as MLCs) storing two bits per memory cell, the memory cells may have four threshold voltage distributions according to program states. As another example, when a memory cell stores three or more bits per memory cell, the memory cells may have eight or more threshold voltage distributions according to a program state.

When the nonvolatile memory 120 performs a program operation on a plurality of memory cells, a plurality of program loops may be performed. When each program loop is performed, an operation of applying a program voltage may be performed to have a plurality of memory cells have a specific program state in each program loop. In each program loop, an operation of sensing outputs of a plurality of memory cells may be performed to determine whether the program state passes. Also, in each program loop, an operation of determining whether a program state has passed may be performed using a sensing value.

In one embodiment, when each memory cell is an SLC, the threshold voltage distribution may have an erase state or a first program state. When a sensing operation is performed on memory cells to be programmed in the first program state, a precharge operation is selectively performed on only bit lines connected to memory cells to be programmed in the first program state among bit lines connected to a plurality of memory cells. can be performed

The memory controller 110 and the nonvolatile memory 120 may be integrated into a single semiconductor device. For example, the memory controller 110 and the nonvolatile memory 120 may be integrated into a single semiconductor device to form a memory card. For example, the non-volatile memory 120 and the memory controller 110 are integrated into a single semiconductor device and can be used for PC cards, compact flash cards, smart media cards, memory sticks, multimedia cards, SD cards, universal flash storage devices, and the like. can be configured. For another example, the memory controller 110 and the nonvolatile memory 120 may be integrated into a single semiconductor device to form a Solid State Disk/Drive (SSD).

2 is a diagram for explaining a nonvolatile memory 200 according to an embodiment of the present disclosure.

Referring to FIG. 2 , the nonvolatile memory 200 may include a memory cell array 210, a control logic 220, a voltage generator 230, a row decoder 240, and a page buffer circuit 250. In another embodiment, the nonvolatile memory 200 may further include a data input/output circuit or an input/output interface.

The memory cell array 210 includes a plurality of memory cells, and includes word lines (WL), string selection lines (SSL), ground selection lines (GSL), and a plurality of It may be connected to the bit lines (bit line, BL) of. Specifically, the memory cell array 210 is connected to the row decoder 240 through word lines WL, string select lines SSL, and ground select lines GSL, and includes a plurality of bit lines BL. ) to the page buffer circuit 250.

The memory cell array 210 may include a plurality of blocks BLK1 to BLKz. For example, each of the plurality of blocks BLK1 to BLKz may have a 3D structure (or vertical structure). Specifically, each block includes structures extending along the first to third directions. For example, each block includes a plurality of NAND strings (hereinafter referred to as 'strings') extending along the third direction. At this time, a plurality of strings may be provided spaced apart by a specific distance along the first and second directions. Blocks BLK1 to BLKz may be selected by the row decoder 240 . For example, the row decoder 240 may select a block corresponding to a block address from among the blocks BLK1 to BLKz.

Each of the memory cells included in the memory cell array 210 may store at least one bit. For example, a memory cell may be an SLC that stores 1 bit of data. For another example, the memory cell may be an MLC that stores 2-bit data. As another example, the memory cell may be a triple level cell (hereinafter referred to as TLC) that stores 3-bit data. For another example, the memory cell may be a quad-level cell (or quadruple-level cell, hereinafter referred to as QLC) that stores 4-bit data. However, the present disclosure is not limited thereto.

The plurality of memory blocks BLK1 to BLKi include at least one of a single-level cell block including SLCs, a multi-level cell block including MLCs, a triple-level cell block including TLCs, and a quad-level cell block including QLCs. can include Some of the plurality of memory blocks included in the memory cell array 210 may be single-level cell blocks, and other blocks may be multi-level cell blocks or triple-level cell blocks.

When an erase voltage is applied to the memory cell array 210, a plurality of memory cells may be in an erase state, and when a program voltage is applied to the memory cell array 210, a plurality of memory cells may be in a program state. In this case, each memory cell may have an erase state and at least one program state classified according to a threshold voltage.

The control logic 220 may overall control various operations within the nonvolatile memory 200 . For example, the control logic 220 transmits data DATA to the memory cell array 210 based on the command CMD, address ADDR, and control signal CTRL received from the memory controller 210 . Various control signals for writing or reading data DATA from the memory cell array 210 may be output. In one embodiment, when a plurality of memory cells are programmed, the control logic 220 may generally control various operations in the nonvolatile memory 200 so that at least one program loop is sequentially performed. In this case, when the memory cells are SLC, only the first program loop may be performed.

Various control signals output from the control logic 220 may be provided to the voltage generator 230 , the row decoder 240 and the page buffer circuit 250 . The control logic 220 may provide the voltage control signal CTRL_vol to the voltage generator 230 . In an embodiment, the control logic 220 may generate a voltage control signal CTRL_vol for controlling generation of a program voltage and a verify voltage provided to the memory cell array 210 in a program operation.

In one embodiment, control logic 220 may control voltage generator 230 such that voltage generator 230 generates at least one verify voltage and at least one program voltage in each program loop, and control logic 220 ) may control the voltage generator 230 to generate a program voltage whose level is changed as the number of program loops increases. For example, as the number of program loops increases, the control logic 220 may control the voltage generator 230 to generate a program voltage having a level increased by the step voltage.

In another embodiment, the control logic 220 may perform a first program loop on a plurality of memory cells. The control logic 220 may control the voltage generator 230 to apply the first program voltage in the first program loop. Also, the control logic 220 may control the voltage generator 230 to apply the first verification voltage in the first program loop. The control logic 220 may control the page buffer circuit 250 to sense a first sensed value corresponding to an output based on the first verification voltage. The control logic 220 may count the number of on cells based on the first sensing value. Here, the on-cell may be a memory cell having a threshold voltage lower than the first verification voltage. An on-cell may be referred to as a slow cell. Meanwhile, the control logic 220 compares the first count value with at least one reference value stored in advance, determines whether or not the first program state passes according to the comparison result, and determines whether the first program state passes or not in the second program loop after the first program loop. A second program voltage may be set. A detailed description thereof will be described later with reference to FIGS. 9, 10, and 12 . At least one reference value may be stored in the control logic 220 using an eFuse method.

The voltage generator 230 may be connected to the memory cell array 210 through a plurality of word lines WL. The voltage generator 230 may generate various types of voltages for performing program, read, and erase operations on the memory cell array 210 based on the voltage control signal CTRL_vol. The voltage generator 230 may generate a word line voltage VWL, eg, a program voltage and a verify voltage.

In an embodiment, the voltage generator 230 may generate a program voltage and a verification voltage whose levels change as the number of program loops increases based on the voltage control signal CTRL_vol. When the program loop is performed, the program method according to an embodiment may be performed in an incremental step pulse programming (ISPP) method, and the voltage generator 230 generates a voltage equal to a step voltage higher than the previous program voltage each time the program loop is performed. A program voltage whose level increases may be generated.

In another embodiment, the voltage generator 230 may generate a second program voltage in the second program loop that is set based on the first count value sensed in the first program loop.

The program voltage, verify voltage, etc. generated by the voltage generator 230 may be provided to a selected word line among the plurality of word lines WL. The selected word line may be at least one word line selected by the row address X-ADDR.

The row decoder 240 may select a specific word line among the word lines WL in response to the row address X-ADDR received from the control logic 220 . Specifically, during a program operation, the row decoder 240 may provide a program voltage to a selected word line. In addition, the row decoder 240 selects some of the string selection lines SSL or some of the ground selection lines GSL in response to the row address X-ARRD received from the control logic 220. line can be selected.

The page buffer circuit 250 may be connected to the memory cell array 210 through a plurality of bit lines BL. The page buffer circuit 250 may select some bit lines from among the plurality of bit lines BL in response to the column address Y-ADDR received from the control logic 220 . During a program operation or a read operation, the page buffer circuit 250 may operate as a sense amplifier to sense data DATA stored in the memory cell array 210 . Meanwhile, during a program operation, the page buffer circuit 250 operates as a write driver to input data DATA to be stored into the memory cell array 210 .

The page buffer circuit 250 may store data DATA read from the memory cell array 210 or data DATA to be written in the memory cell array 210 . The page buffer circuit 250 may sense a first sensing value corresponding to an output based on the verification voltage under the control of the control logic 220 . When the verification voltage is applied, the page buffer circuit 250 may temporarily store the sensed value. The stored sensing value may be a count value corresponding to the number of on-cells.

During a program operation, when the row decoder 240 applies a program voltage to a selected word line, the page buffer circuit 250 inhibits programming to the plurality of bit lines BL according to the programming speed of the memory cell. A bit line voltage such as voltage and program voltage may be applied.

The page buffer circuit 250 may include a plurality of page buffers respectively connected to a plurality of bit lines BL. A plurality of page buffers may be disposed corresponding to each bit line, and each page buffer may include a plurality of latches. Hereinafter, a page buffer circuit will be defined as including a page buffer connected to each bit line. However, in the embodiments of the present disclosure, the term may be defined differently, and as an example, a unit of configuration in which one page buffer is provided corresponding to a plurality of bit lines and disposed corresponding to each bit line It could also be defined as a page buffer unit.

3 is a circuit diagram illustrating a memory block according to an exemplary embodiment of the present disclosure.

Referring to FIG. 3 , the memory block BLKa may be a NAND flash memory having a horizontal structure. The memory block BLKa may include, for example, d (d is an integer greater than or equal to 2) strings STRs in which 8 memory cells are connected in series. Each string STR may include a string select transistor SST and a ground select transistor GST respectively connected to both ends of the memory cells MC connected in series. Here, the number of strings STR, the number of word lines WL, and the number of bit lines BL may be variously changed according to embodiments.

In a NAND flash memory device including a memory block having the structure shown in FIG. 3 , erasing may be performed in units of memory blocks, and programming may be performed in units of pages corresponding to word lines WL1 to WL8 . In one example, when the memory cell MC is an SLC, one page (PAGE) may correspond to each word line. In another example, when the memory cell MC is MLC, TLC, or QLC, a plurality of pages PAGE may correspond to each word line. For example, when the memory cell MC is a QLC, each word line may correspond to an LSB page, an ESB page, a USB page, and an MSB page.

In one embodiment, the first program voltage in the first program loop may be set differently according to each word line WL1 to WL8. For example, the magnitude of the first program voltage to be applied to the first word line WL1 may be different from the magnitude of the first program voltage to be applied to the second word line WL2. Setting the first program voltage differently for each word line in the first program loop may be referred to as IDC (Individual Die Core). This operation may be performed by the control logic 220 shown in FIG. 2 .

In another embodiment, the IDC may be set differently according to the nonvolatile memory 200 shown in FIG. 2 . That is, the first program voltage in the first program loop may be set differently according to the nonvolatile memory.

4 is a circuit diagram illustrating a memory block according to another exemplary embodiment of the present disclosure.

Referring to FIG. 4 , the memory block BLKb may be a NAND flash memory having a vertical structure. The memory block BLKb includes a plurality of NAND strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, and ground select lines GSL1, GSL2, and GSL3. , a plurality of string select lines SSL1 to SSL3 and a common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may be variously changed according to embodiments.

NAND strings NS11, NS21, and NS31 are provided between the first bit line BL1 and the common source line CSL, and the NAND strings are provided between the second bit line BL2 and the common source line CSL. NS12, NS22, and NS32 are provided, and NAND strings NS13, NS23, and NS33 are provided between the third bit line BL3 and the common source line CSL. Each NAND string (eg, NS11) may include a string select transistor SST, a plurality of memory cells MC1 to MC8, and a ground select transistor GST connected in series. Hereinafter, for convenience, a NAND string will be referred to as a string.

Strings commonly connected to one bit line constitute one column. For example, the strings NS11, NS21, and NS31 commonly connected to the first bit line BL1 correspond to the first column, and the strings NS12, NS22, and NS22 are commonly connected to the second bit line BL2. NS32) may correspond to the second column, and strings NS13, NS23, and NS33 commonly connected to the third bit line BL3 may correspond to the third column.

Strings connected to one string selection line constitute one row. For example, the strings NS11, NS12, and NS13 connected to the first string selection line SSL1 correspond to the first row, and the strings NS21, NS22, and NS23 connected to the second string selection line SSL2 corresponds to the second row, and the strings NS31, NS32, and NS33 connected to the third string selection line SSL3 may correspond to the third row.

The string select transistor SST is connected to the string select lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 are connected to corresponding word lines WL1 to WL8, respectively. The ground select transistor GST is connected to the ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST is connected to the corresponding bit line BL, and the ground select transistor GST is connected to the common source line CSL.

Word lines (eg, WL1) of the same height are commonly connected, and string select lines SSL1 to SSL3 are separated from each other. For example, when programming memory cells connected to the first word line WL1 and belonging to the strings NS11, NS12, and NS13, the first word line WL1 and the first string select line SSL1 can be selected. In one embodiment, as shown in FIG. 4 , the ground select lines GSL1 , GSL2 , and GSL3 may be separated from each other. In another embodiment, the ground selection lines GSL1 , GSL2 , and GSL3 may be connected to each other.

In one embodiment, the first program voltage in the first program loop may be set differently according to each word line WL1 to WL8. In another embodiment, the first program voltage in the first program loop may be set differently according to the nonvolatile memory 200 shown in FIG. 2 .

FIG. 5 is a perspective view illustrating a memory block according to the circuit diagram of FIG. 4 .

Referring to FIG. 5 , the memory block BLKb is formed in a direction perpendicular to the substrate SUB. The substrate SUB has a first conductivity type (eg, p-type), extends on the substrate SUB in a first direction (eg, x direction), and has a second conductivity type (eg, x direction). , n-type) impurities may be doped with the common source line CSL. The common source line CSL may function as a source region supplying current to vertical memory cells. On a region of the substrate SUB between two adjacent common source lines CSL, a plurality of insulating layers IL extending along a second direction (eg, y direction) are formed in a third direction (eg, y direction). z direction), and the plurality of insulating layers IL are spaced apart by a specific distance along the third direction. For example, the plurality of insulating layers IL may include an insulating material such as silicon oxide.

Channel holes sequentially disposed along the first direction and penetrating the plurality of insulating layers IL along the third direction may be formed on a region of the substrate SUB between two adjacent common source lines CSL. can The channel hole may be formed in a cup shape (or a cylinder shape with a closed bottom) extending in a vertical direction. Alternatively, the channel hole may be formed in a pillar shape as shown. Hereinafter, channel holes will be referred to as pillars. The plurality of pillars P may contact the substrate SUB by penetrating the plurality of insulating layers IL. Specifically, the surface layer (S) of each pillar (P) may include a first type silicon material and may function as a channel region. Meanwhile, the inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

In a region between two adjacent common source lines CSL, a charge storage layer CS is provided along the insulating layers IL, the pillars P, and the exposed surface of the substrate SUB. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, a gate electrode GE may be provided on an exposed surface of the charge storage layer CS in a region between two adjacent common source lines CSL.

Drains or drain contacts DR are respectively provided on the plurality of pillars P. For example, the drains or drain contacts DR may include a silicon material doped with impurities of the second conductivity type. Bit lines BL extending in the second direction (eg, y direction) and spaced apart by a specific distance along the first direction may be provided on the drains or drain contacts DR. An exemplary embodiment of a memory block has been described with reference to FIG. 4 . However, it is not limited thereto and the structure of the memory block may be variously modified.

6 is a timing diagram illustrating a method of applying a program voltage in a program operation according to an embodiment of the present disclosure.

Referring to FIG. 6 , an initialization voltage may be applied to each of the word lines in the first period t1 . For example, an initialization voltage may be applied to each of the selected word line (Selected WL) and the unselected word lines (Unselected WL). However, it is not limited thereto.

In the second period t2 , the pass voltage Vpass may be applied to the selected word line (Selected WL) and the unselected word lines (Unselected WL). The selected word line (Selected WL) and the unselected word lines (Unselected WL) may be turned on by the pass voltage (Vpass).

In the third period t3 , the program voltage Vpgm may be applied to the selected word line Selected WL, and the pass voltage Vpass may be applied to the unselected word lines Unselected WL.

In the fourth period t4 , the pass voltage Vpass applied to the selected word line (Selected WL) and unselected word lines (Unselected WL) may be applied.

In the fifth period t5 , an initialization voltage may be applied to the selected word line (Selected WL) and the unselected word lines (Unselected WL).

7 is a timing diagram illustrating a method of applying a verification voltage in a program operation according to an embodiment of the present disclosure.

In the first period t1, the unselected read voltage Vus may be applied to the unselected word lines Unselected WL. An initialization voltage may be applied to the selected word line Selected WL.

In the second period t2 , a verification voltage may be applied to the selected word line Selected WL.

In the third period t3 , an initialization voltage may be applied to the selected word line (Selected WL) and unselected word lines (Unselected WL).

8A, 8B, and 8C are diagrams illustrating threshold voltage distributions of memory cells according to an exemplary embodiment of the present disclosure. Specifically, FIG. 8A is a diagram showing a threshold voltage distribution of SLC, FIG. 8B is a diagram showing a threshold voltage distribution of MLC, and FIG. 8C is a diagram showing a threshold voltage distribution of TLC.

Referring to FIG. 8A , when a program operation is performed on the SLCs, the SLCs may have various threshold voltage distributions 800 , 801 , and 810 . That is, the SLCs may have a threshold voltage belonging to a threshold voltage distribution corresponding to any one of the erase state (E) and the first program state (P1). Before a program operation is performed, SLCs may have a threshold voltage distribution 800 corresponding to an erase state (E). During the program operation, the SLCs may have a threshold voltage distribution 801 . In the second threshold voltage distribution 801, when the first voltage Vp1 is applied as a verification voltage, current flows in SLCs having threshold voltages lower than or equal to the first voltage Vp1 and higher than the first voltage Vp1. Current may not flow in SLCs with a high threshold voltage. As such, when the first voltage Vp1 is the verification voltage, SLCs having a threshold voltage lower than or equal to the verification voltage may be referred to as on-cells, and SLCs having a threshold voltage higher than the verification voltage are turned off. may be referred to as a cell. The first program state P1 may be a state of SLCs after a program operation is performed. When the programming is completed, the SLCs may have threshold voltage distributions 810 corresponding to the first program state P1.

Referring to FIG. 8B, when a program operation is performed on the MLCs, the MLCs have an erase state E and a threshold voltage distribution corresponding to one of the first to third program states P1, P2, and P3 ( 800, 810, 820 or 830). As the step of applying the program voltage proceeds, the step of verifying each of the first to third program states P1, P2, and P3 sequentially from the first program state P1 to the third program state P3 proceeds. can be performed Verification of the first program state P1 may be an operation of determining whether threshold voltages of the selected MLCs reach the threshold voltage corresponding to the first program state P1. The first voltage Vp1 may be used, for example, as a verification voltage for verifying MLCs having threshold voltage distributions 810 corresponding to the first program state P1. Among the MLCs to be programmed to the first program state P1 , MLCs having voltages higher than the first voltage Vp1 may be off cells. Among the memory cells to be programmed to the first program state P1 , memory cells lower than or equal to the first voltage Vp1 may be on-cells. Verification of each of the second and third program states P2 and P3 may include a threshold voltage corresponding to each of the second and third program states P2 and P3, for example, the second and third voltages ( It may be an operation to determine whether each of Vp2 and Vp3) has been reached.

Referring to FIG. 8C , when a program operation is performed on the TLC, the TLC is in an erase state E and one of the first to seventh program states P1, P2, P3, P4, P5, P6, and P7. It may have a threshold voltage belonging to a threshold voltage distribution (800, 810, 820, 830, 840, 850, 860, or 870) corresponding to the state. As the process of applying the program voltage proceeds, a verification process for each of the first to seventh program states P1 , P2 , P3 , P4 , P5 , P6 , and P7 may be sequentially performed. Each of the first to seventh voltages Vp1, Vp2, Vp3, Vp4, Vp5, Vp6, and Vp7 is, for example, the first to seventh program states P1, P2, P3, P4, P5, P6, P7) may be used as a verification voltage for verifying TLCs having threshold voltage distributions 810, 820, 830, 840, 850, 860, or 870 respectively.

9 is a flowchart illustrating a method of operating a program in a first program loop according to an embodiment of the present disclosure.

Referring to FIG. 9 , in step S910 , a program voltage is applied to the selected word line. Specifically, the control logic 220 sets a first program voltage in the first program loop and the voltage generator 230 applies the first program voltage to the selected word line. Step S910 may be referred to as a program step.

In step S920, a verification voltage is applied to the selected word line and the selected bit line is sensed. That is, after the first program voltage is applied in the first program loop, the first sensed value is sensed. Here, the first sensing value may correspond to an output based on the first verification voltage set in the first program loop. Specifically, the control logic 220 sets the first verify voltage in the first program loop, the voltage generator 230 applies the first verify voltage to the select word line, and the page buffer circuit 250 selects the select bit. The first sensing value is sensed through the line. Step S920 may be referred to as a verification step.

In step S930, whether or not the program state passes is determined based on the number of on-cells, and the magnitude of the program voltage in the next program loop (eg, the second program loop) is set. Specifically, the control logic 220 counts the number of on cells based on the first sensing value, compares the first count value with at least one reference value, and determines the first program state according to the comparison result. Pass or not is determined and a second program voltage is set. Step S930 may be referred to as a pass confirmation step.

As described above, by completing the program operation early, the performance of the program operation can be increased.

10 is a flowchart for specifically explaining a program operation method according to another embodiment of the present disclosure. It is assumed that the program operation method according to another embodiment of the present disclosure is performed for a single-level cell.

Referring to FIG. 10 , in step S1010, a program loop (hereinafter, PL) is set to 1. In step S1011, a first program voltage is applied to the selected word line. In step S1012, a first verification voltage is applied to the selected word line and a first sensing operation is performed. The first sensing operation may be an operation in which the page buffer circuit 250 senses the first sensing value by the first verification voltage. In step S1013, on-cells are counted. In detail, the control logic 220 may obtain a count value corresponding to the number of on-cells. In step S1014, it may be determined whether the first count value (hereinafter, CNT1) is less than or equal to a first reference value (hereinafter, Th1). Specifically, the control logic 220 determines whether CNT1 is less than or equal to Th1. If CNT1 is equal to or less than Th1 (S1014, Yes), the control logic 220 determines that the first program state is pass, ends the first program loop, and completes the program operation. At this time, since it is determined that the first program state has passed, execution of the second program loop may be omitted. Accordingly, the control logic 220 may omit setting the second program voltage. If CNT1 is greater than Th1 (S1014, No), in step S1015, a second program voltage is set based on CNT1. If CNT1 is greater than Th1, it means that there are relatively many on-cells, and a threshold voltage distribution corresponding to the first program state may not be generated. In this case, the control logic 220 may determine the first program state as a fail and set the level of the second program voltage (or the amount of increase in the program voltage) based on CNT1. In one embodiment, the second program voltage may be equal to the sum of increments of the program voltage from the first program voltage. Steps S1010 to S1014 may be included in the first program loop. As will be described later, since the control logic 220 can determine whether CNT1 is included between Th1 and the second reference value (hereinafter referred to as Th2) or whether CNT1 is greater than or equal to Th2, step S1016 is also included in the first program loop. can be included Th2 may have a greater value than Th1.

In step S1020, PL is set from 1 to 2. That is, a second program loop, which is a program loop following the first program loop, is executed. In step S1021, a second program voltage is applied to the selected word line. In detail, the control logic 220 may control the voltage generator 230 to apply the second program voltage by performing the second program loop. The voltage generator 230 applies the second program voltage to the selected word line. Since the second program voltage is appropriately set, it can be expected that the single-level cell reaches the first program state by the second program voltage. Step S1021 may be referred to as a program step. In step S1016, it is determined whether CNT1 is greater than Th1 and less than or equal to Th2. In one embodiment, step S1016 may be an operation performed together with step S1014. If CNT1 is greater than Th1 and less than or equal to Th2 (S1016, Yes), the control logic 220 determines that the first program state is pass and ends the program operation. If CNT1 is greater than Th2 (S1016, No), in step S1022, a second verification voltage is applied to the selected word line and a second sensing operation is performed. The second verification voltage may be a verification voltage set in the second program loop. In one embodiment, the second verification voltage may be the same as the first verification voltage. The second sensing operation may be an operation in which the page buffer circuit 250 senses a second sensed value by the second verification voltage. Step S1022 may be referred to as a verification step. Steps S1020, S1021, and S1022 may be included in the second program loop.

In step S1030, PL is set from 2 to 3. That is, a third program loop, which is a program loop following the second program loop, is executed. In step S1031, a third program voltage is applied to the selected word line, and whether the program passes is detected based on a second count value (hereinafter referred to as CNT2) obtained by counting on-cells. Specifically, the control logic 220 sets a third program voltage higher than the second program voltage. In an embodiment, the control logic 220 may set, as the magnitude of the third program voltage, a value obtained by adding the magnitude of the second program voltage to the increment preset according to the ISPP. The voltage generator 230 applies the third program voltage to the selected word line. The control logic 220 obtains CNT2 based on the second sensing value sensed in the second program loop, and compares CNT2 with Th1 and Th2 to detect whether the program passes for the first program state. If CNT2 is less than or equal to Th1, it may be determined that the first program state has passed. When the first program state passes, the program operation may be completed. In one embodiment, an operation of applying the third program voltage to the selected word line and an operation of determining whether to pass the program based on CNT2 may be performed together. Steps S1030 and S1031 may be included in the third program loop.

In another embodiment, the determination operations in steps S1014 and S1016 may be an operation of comparing CNT1 with a plurality of reference ranges composed of Th1 and Th2. The plurality of reference ranges composed of Th1 and Th2 may include, for example, first to third reference ranges. The first reference range may be greater than or equal to 0 and less than or equal to Th1, the second reference range may be greater than Th1 and less than or equal to Th2, and the third reference range may be greater than Th2. However, it is not limited thereto. For example, if CNT1 is included in the first reference range of Th1 or less, the control logic 220 determines that the first program state is PASS, skips setting the second program voltage, and terminates the first program loop. and complete the program operation. For another example, when CNT1 is included in the second reference range between Th1 and Th2, the control logic 220 executes the second program loop, sets the second program voltage, and sets the voltage generator to apply the second program voltage. 230 is controlled, it is determined that the first program state is pass, and the second program loop is terminated and the program operation is completed. For another example, if CNT1 is included in the third reference range greater than Th2, the program step and the verify step in the second program loop are performed, and the third program voltage in the third program loop Then, an operation of determining whether or not the first program state passes based on CNT2 may be performed. When the first program state passes, the third program loop ends and the program operation is complete.

As described above, the program operation for the single-level cell can be completed in the first program loop, and thus the speed of the program operation can be improved.

11 is a diagram for explaining a method of counting on-cells according to an embodiment of the present disclosure.

Referring to FIG. 11 , a threshold voltage distribution 1110 higher than the first voltage Vp1 may correspond to the first program state P1. In one embodiment, a voltage Vp0 lower than the first voltage Vp1 may be used as the verification voltage. In this case, with respect to the threshold voltage distribution 1100 generated when the program voltage is applied, memory cells having a threshold voltage lower than the voltage Vp0 may be sensed as on-cells. As described above, there is an advantage in that the program voltage in the second program loop can be more accurately set by using the voltage Vp0 lower than the first voltage Vp1.

12 is a diagram for explaining an embodiment of a method of operating a program for a single-level cell. Specifically, FIG. 12 exemplarily illustrates a program operation method when a first count value obtained in a first program loop (Program loop 1) is equal to or less than a first reference value.

Referring to FIGS. 1 and 10 to 12 , the nonvolatile memory 120 may start a program operation in response to control of the memory controller 110 (PGM START).

In the first program loop (Program loop 1), the program phase (PGM), verification phase (VFY), and pass verification phase (PF) may be sequentially performed. In the program step (PGM), a first program voltage is applied, and the first program voltage is a characteristic of the nonvolatile memory 120 and/or a selected word among a plurality of word lines WL included in the nonvolatile memory 120. It can be set differently depending on the line. In the verification step (VFY), a verification voltage may be applied and a sensed value may be detected. This sensing value may correspond to the number of on-cells. In this case, the verification voltage may be a voltage Vp0 lower than the first voltage Vp1 as shown in FIG. 11 . The pass confirmation step (PF) determines whether the first program state has passed by using a count value corresponding to the number of on-cells and at least one reference value stored in advance in the control logic (eg, 220 shown in FIG. 2). can be confirmed If the first count value is less than or equal to the first reference value in the pass checking step (PF), the operation of setting the second program voltage may be omitted and the first program loop (Program loop 1) may end.

When the first program loop (Program loop 1) ends, the nonvolatile memory 120 may complete the program operation (PGM END).

As described above, the performance of the program operation for the single-level cell can be improved by reducing the program completion time at which the first program loop (Program loop 1) starts and ends.

13 is a diagram for explaining another embodiment of a method of operating a program for a single-level cell. Specifically, FIG. 13 exemplarily illustrates a program operation method when a first count value obtained in a first program loop (Program loop 1) is greater than a first reference value and less than or equal to a second reference value.

1, 10, 11, and 13, a program step (PGM), a verification step (VFY), and a pass check step (PF) are sequentially performed in a first program loop (Program loop 1). can The program step (PGM) and verification step (VFY) are as described above with reference to FIG. 12 . In the pass confirmation step (PF), the first count value may be greater than the first reference value and less than or equal to the second reference value. In this case, the second program voltage may be set according to the first count value.

A second program loop (Program loop 2) is performed, and a program step (PGM) may be performed in the second program loop (Program loop 2). A difference (ΔV1) between the first program voltage in the first program loop (Program loop 1) and the second program voltage in the second program loop (Program loop 2) may be proportional to the first count value. When the program step (PGM) in the second program loop (Program loop 2) is performed, since it is expected that the memory cell has the first program state, the second program loop (Program loop 2) is finished and the program operation is completed. can (PGM END). Although the program completion time shown in FIG. 13 is slightly increased than the program completion time shown in FIG. 12, as the program operation for the single-level cell is completed within the second program loop, the single-level There is an effect of improving the speed of the program operation for the cell.

14 is a diagram for explaining another embodiment of a method of operating a program for a single-level cell. Specifically, FIG. 13 exemplarily illustrates a program operation method when a first count value obtained in a first program loop (Program loop 1) is greater than a second reference value.

Referring to FIGS. 1, 10, 11, and 14, a program step (PGM), a verification step (VFY), and a pass check step (PF) are sequentially performed in a first program loop (Program loop 1). can The program step (PGM) and verification step (VFY) are as described above with reference to FIG. 12 . In the pass confirmation step (PF), the first count value may be greater than the second reference value.

Unlike shown in FIG. 13 , since the first count value is greater than the second reference value, the program step (PGM) and the verification step (VFY) may be sequentially performed in the second program loop (Program loop 2). In the verification step VFY, a second verification voltage may be used, and the second verification voltage may be the same as the first verification voltage. The second count value may be obtained through the verification step (VFY).

A third program loop (Program loop 3) is performed, and in the third program loop (Program loop 3), the program step (PGM) and the pass check step (PF) may be performed together. In the program phase PGM, a third program voltage may be applied. A difference (ΔV2) between the second program voltage in the second program loop (Program loop 2) and the first program voltage in the third program loop (Program loop 3) may be determined according to ISPP. In the pass checking step PF, whether the first program state passes may be checked by comparing the second count value with the first and second reference values. The second count value may be obtained through the verification step (VFY) included in the second program loop (Program loop 2) and temporarily stored in the control logic 220.

Although the program completion time shown in FIG. 14 is somewhat increased than the program completion time shown in FIG. 13, as the program operation for the single-level cell is completed within at least the third program loop, the single There is an effect of improving the speed of the program operation for the level cell.

15 is a block diagram illustrating a computing system according to an embodiment of the present disclosure.

Referring to FIG. 15 , a computing system 1500 includes a processor 1510, a memory controller 1520, input devices 1530, output devices 1540, a nonvolatile memory device 1550, and a main memory device ( 1560). In the drawing, a solid line represents a system bus through which data or commands move.

The memory controller 1520 and the nonvolatile memory device 1550 may form a memory card. Also, the processor 1510, the input devices 1530, the output devices 1540, and the main memory device 1560 may configure a host that uses a memory card as a memory device.

The computing system 1500 according to the present invention receives data from the outside through the input devices 1530 (keyboard, camera, etc.). The input data may be a command by a user or multimedia data such as video data by a camera or the like. The input data is stored in the nonvolatile memory device 1550 or the main memory device 1560 .

A processing result by the processor 1510 is stored in the nonvolatile memory device 1550 or the main memory device 1560 . The output devices 1540 output data stored in the nonvolatile memory device 1550 or the main memory device 1560 . The output devices 1540 output digital data in a human-sensible form. For example, the output device 1540 includes a display or a speaker. The program method according to the present invention will be applied to the nonvolatile memory device 1550 . As the reliability of the nonvolatile memory device 1550 is improved, the reliability of the computing system 1500 will also be improved in proportion thereto.

The nonvolatile memory device 1550 and/or the memory controller 1520 may be mounted using various types of packages. For example, the nonvolatile memory device 1550 and/or the controller 1520 may include Package on Package (PoP), Ball Grid Arrays (BGAs), Chip Scale Packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) , Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) ), and Wafer-Level Processed Stack Package (WSP).

The computing system 1500 may include a power supply for supplying power necessary for the operation of the computing system 1500 . In another embodiment, when the computing system 1500 is a mobile device, the computing system 1500 may further include a battery for supplying operating power to the computing system 1500 .

16 is a block diagram illustrating a solid state device of a computing system according to an embodiment of the present disclosure.

Referring to FIG. 16 , an SSD system 1600 includes an SSD controller 1610 and nonvolatile memory devices 1620 to 323 .

The nonvolatile memory device according to the present invention may also be applied to a solid state drive (SSD). Recently, SSD products, which are expected to replace hard disk drives (HDD), are in the limelight in the next-generation memory market. An SSD is a data storage device using memory chips such as flash memory to store data instead of a rotating plate used in a general hard disk drive. Compared to mechanically moving hard disk drives, SSDs are faster, more resistant to external shocks, and have lower power consumption.

The central processing unit 1611 receives a command from the host and determines and controls whether to store data from the host in the nonvolatile memory device or to read and transmit data stored in the nonvolatile memory device to the host.

The ATA interface 1612 exchanges data with the host under the control of the aforementioned CPU 1611. The ATA interface 1612 fetches commands and addresses from the host side and transfers them to the CPU 1611 through the CPU bus. Data input from the host through the ATA interface 1612 or data to be transmitted to the host are transferred through the SRAM cache 1613 without passing through the CPU bus under the control of the CPU 1611 . The ATA interface 212 includes a serial ATA (S-ATA) standard and a parallel ATA (P-ATA) standard.

The SRAM cache 1613 temporarily stores movement data between the host and the nonvolatile memory devices 1620 to 323. Also, the SRAM cache 1613 is used to store programs to be operated by the central processing unit 1611. The SRAM cache 1613 can be regarded as a kind of buffer memory, and does not necessarily need to be composed of SRAM. The flash interface 1614 exchanges data with nonvolatile memories used as storage devices. The flash interface 1614 may be configured to support NAND flash memory, one-NAND flash memory, or multi-level flash memory.

The semiconductor memory system according to the present invention can be used as a portable storage device. Therefore, it can be used as a storage device for MP3, digital camera, PDA, and e-Book. Also, it can be used as a storage device such as a digital TV or computer.

It is obvious to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is believed that the present invention covers this invention and its modifications and variations provided that such modifications and variations fall within the scope of the following claims and equivalents.

As above, exemplary embodiments have been disclosed in the drawings and specifications. Although the embodiments have been described using specific terms in this specification, they are only used for the purpose of explaining the technical idea of the present disclosure, and are not used to limit the scope of the present disclosure described in the claims. . Therefore, those of ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims.

Claims (20)

A program operating method of a non-volatile memory that performs at least one program loop on a plurality of memory cells, comprising:
The first program loop of the at least one program loop,
a programming step of applying a first program voltage;
a verification step of sensing a first sensed value corresponding to an output based on the first verification voltage; and
The number of on-cells is counted based on the first sensing value, the first count value is compared with at least one reference value, and whether or not the first program state passes is determined according to the comparison result, and the first A method of operating a program of a non-volatile memory comprising: a pass checking step of setting a second program voltage in a second program loop after the program loop. According to claim 1,
The at least one reference value,
A first reference value and a second reference value greater than the first reference value,
The first count value is,
Less than or equal to the first reference value,
The pass confirmation step,
The program operating method of a non-volatile memory, characterized in that determining that the first program state is pass and omitting the setting of the second program voltage. According to claim 2,
The plurality of memory cells are single-level cells,
The method of operating a program of a non-volatile memory, characterized in that the method of operating the program of the non-volatile memory is completed after the first program loop. According to claim 1,
The at least one reference value,
A first reference value and a second reference value greater than the first reference value,
The first count value is,
greater than the first reference value,
The pass confirmation step,
The method of claim 1 , wherein the first program state is determined to be a fail and the size of the second program voltage is set based on the first count value. According to claim 4,
The first count value is,
Less than or equal to the second reference value,
The second program loop,
A program operation method of a non-volatile memory comprising a programming step of applying the second program voltage. According to claim 5,
The plurality of memory cells are single-level cells,
The method of operating a program of a non-volatile memory, characterized in that the method of operating the program of the non-volatile memory is completed after the second program loop. According to claim 4,
The first count value is,
greater than the second reference value,
The second program loop,
a programming step of applying the second program voltage; and
A verification step of sensing a second sensed value corresponding to an output based on the second verification voltage;
The third program loop after the second program loop,
A third program voltage higher than the second program voltage is applied, the number of on-cells is counted based on the second sensed value, and the second count value is compared with the first reference value and the second reference value to obtain the A method of operating a program in a non-volatile memory comprising determining whether a first program state has passed. According to claim 7,
The plurality of memory cells are single-level cells,
The first program state is determined to be pass,
The method of operating a program of a non-volatile memory, characterized in that the method of operating the program of the non-volatile memory is completed after the third program loop. According to claim 1,
The first program voltage is
A program operation method of a non-volatile memory, characterized in that it is set differently according to word lines connected to the plurality of memory cells. a memory cell array including a plurality of memory cells;
a voltage generator connected to the memory cell array through a plurality of word lines and providing a voltage to a selected word line among the plurality of word lines;
a page buffer circuit connected to the memory cell array through a plurality of bit lines and sensing a sensed value through each bit line; and
control logic configured to perform at least one program loop for the plurality of memory cells;
The control logic,
performing a first program loop of the at least one program loop;
Controlling the voltage generator to apply a first program voltage in the first program loop;
Controlling the voltage generator to apply a first verification voltage in the first program loop;
Control the page buffer circuit to sense a first sensing value corresponding to an output based on the first verification voltage;
The number of on-cells is counted based on the first sensing value, the first count value is compared with at least one reference value stored in advance, and whether or not the first program state passes is determined according to the comparison result. A non-volatile memory characterized by setting a second program voltage in a second program loop after the first program loop. According to claim 10,
The at least one reference value,
Including a first reference value;
The control logic,
determining whether the first count value is less than or equal to the first reference value;
If the first count value is less than or equal to the first reference value, determining that the first program state is Pass and omitting the setting of the second program voltage;
When the first count value is greater than the first reference value, the first program state is determined to be a fail, and the second program voltage is set based on the first count value. volatile memory. According to claim 11,
The plurality of memory cells are single-level cells,
The control logic,
When the first program state is determined to be Pass, the first program loop is terminated and a program operation is completed. According to claim 11,
The at least one reference value,
Further comprising a second reference value greater than the first reference value,
The control logic,
When the first count value is greater than the first reference value and less than or equal to the second reference value, the voltage generator is controlled to apply the second program voltage by performing the second program loop. Memory. According to claim 11,
The at least one reference value,
Further comprising a second reference value greater than the first reference value,
The control logic,
If the first count value is greater than the second reference value, the second program loop is performed, the voltage generator is controlled to apply the second program voltage, and the second verify voltage is applied in the second program loop. controlling the voltage generator to sense a second sensing value corresponding to an output based on the second verification voltage;
controlling the voltage generator to apply a third program voltage higher than the second program voltage by performing a third program loop after the second program loop, and counting the number of on-cells based on the second sensed value; and determining whether the first program state passes by comparing a second count value with the first reference value and the second reference value. According to claim 10,
The control logic,
and setting the first program voltage differently according to the selected word line. A program operation method of a non-volatile memory in which a first program loop is performed on a plurality of single-level cells, the method comprising:
The first program loop,
a programming step of applying a first program voltage;
a verification step of sensing a first sensed value corresponding to an output based on the first verification voltage; and
The number of on cells is counted based on the first sensing value, the first count value is compared with a plurality of reference ranges, and whether or not the program state passes is determined based on the comparison result, and after the first program loop A method of operating a program of a non-volatile memory comprising a pass checking step of setting a second program voltage in a second program loop of According to claim 16,
The first count value is,
Included in a first reference range less than or equal to a first reference value among the plurality of reference ranges,
The pass confirmation step,
determining that the program state is pass, and omitting setting the second program voltage;
The method of operating a program of a non-volatile memory, characterized in that the method of operating the program of the non-volatile memory is completed after the first program loop. According to claim 16,
The first count value is,
Included in a second reference range between a first reference value and a second reference value among the plurality of reference ranges,
The pass confirmation step,
determining that the program state is a fail, and setting the magnitude of the second program voltage according to the first count value;
The second program loop,
A programming step of applying the second program voltage;
The method of operating a program of a non-volatile memory, characterized in that the method of operating the program of the non-volatile memory is completed after the second program loop. According to claim 16,
The first count value is,
Included in a third reference range equal to or greater than a second reference value greater than the first reference value among the plurality of reference ranges,
The pass confirmation step,
determining that the program state is a fail, and setting the magnitude of the second program voltage according to the first count value;
The second program loop,
a programming step of applying the second program voltage; and
A verification step of sensing a second sensed value corresponding to an output based on the second verification voltage;
The third program loop after the second program loop,
A third program voltage higher than the second program voltage is applied, the number of on-cells is counted based on the second sensed value, and the second count value is compared with the first reference value and the second reference value to obtain the A method of operating a program in a non-volatile memory comprising determining whether a program state has passed. According to claim 19,
The program state is determined to be pass,
The method of operating a program of a non-volatile memory, characterized in that the method of operating the program of the non-volatile memory is completed after the third program loop.

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