KR102501396B1 - Display device, gate driver and method for driving controller - Google Patents

Abstract

The present embodiments relate to a display device and a method for driving a gate driver and a controller included in the display device. In the present embodiments, a plurality of gate driver integrated circuits included in a controller and a gate driver are connected through a plurality of wires, so that clock signals input to the plurality of gate driver integrated circuits can be distributed and input in both directions. In addition, considering the difference in the load of each wire, the clock signal input to the wire with a large load is adjusted to have an advanced phase compared to the clock signal input to the wire with a small load, thereby reducing the distortion of the gate signal input to the gate line. and prevent luminance deviation due to distortion of the gate signal from occurring.

Description

Driving method of display device, gate driver and controller {DISPLAY DEVICE, GATE DRIVER AND METHOD FOR DRIVING CONTROLLER}

The present embodiments relate to a method for driving a display device, a gate driver included in the display device, and a controller.

As the information society develops, demands for display devices for displaying images are increasing in various forms. Accordingly, in recent years, various types of display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display device (OLED) are being used. there is.

Such a display device includes a display panel in which a plurality of gate lines and a plurality of data lines are disposed and a plurality of pixels defined in an area where the gate lines and the data lines intersect are disposed. It may also include a gate driver driving the plurality of gate lines, a data driver supplying data voltages to the plurality of data lines, and a controller controlling driving of the gate driver and the data driver.

The gate driver outputs a gate signal at the time of driving each gate line so that the data voltage output by the data driver can be transferred to each pixel through the data line.

The gate signal output by the gate driver is sequentially output using a clock signal output from the controller, and the clock signal may have the same phase and width.

At this time, even if the clock signal has the same phase and width and is input to the gate driver, a delay may occur in the gate signal output by the gate driver due to a load in the display panel.

Distortion of the signal due to the delay of the gate signal does not sufficiently secure a time for supplying the data voltage to each pixel, causing a luminance deviation to occur depending on the position of the display panel.

An object of the present embodiments is to provide a gate driver that prevents delay and distortion of a gate signal output by the gate driver, a controller, and a display device including the same.

An object of the present embodiments is to provide a gate driver, a controller, and a display device including the gate driver and controller that prevent a luminance deviation according to a position of a display panel.

In one aspect, the present embodiments include a gate driver for outputting gate signals to a plurality of gate lines disposed on a display panel, connected to a plurality of gate driver integrated circuits, and a plurality of gate driver integrated circuits. A display device including a controller outputting a clock signal may be provided.

Such a display device may include a first wire connecting some of the gate driver integrated circuits adjacent to the controller and the controller, and a second wire connecting the remaining gate driver integrated circuits and the controller.

Here, the first wire may be disposed on one side of the gate driver integrated circuit, and the second wire may be disposed on the other side of the gate driver integrated circuit.

Alternatively, the second wire may be disposed in an area where the first wire is not disposed between the other side of the gate driver integrated circuit and one side of the gate driver integrated circuit.

In this case, among the clock signals output from the controller, a clock signal output through the first wire and a clock signal output through the second wire may be out of phase with each other.

For example, the phase of the clock signal output through the second wire may be advanced compared to the phase of the clock signal output through the first wire.

Here, the phase of the clock signal output through the second wire is advanced based on the signal delay value according to the difference between the load for the clock signal output through the first wire and the load for the clock signal output through the second wire. It can be a phase.

Alternatively, the phase of the clock signal output through the second wire may be advanced based on a signal delay value according to a difference between the length of the first wire and the length of the second wire.

In another aspect, in the present embodiments, a plurality of gate driver integrated circuits are disposed, and the plurality of gate driver integrated circuits include a first group including some gate driver integrated circuits adjacent to a controller and the remaining gate driver integrated circuits. The gate driver is composed of a second group and includes a first wire connecting the controller and the gate driver integrated circuit included in the first group, and a second wire connecting the controller and the gate driver integrated circuit included in the second group. can provide.

In another aspect, the present embodiments provide a method for driving a controller that outputs a clock signal to a plurality of gate driver integrated circuits arranged in a gate driver, wherein the first clock signal has a phase different from that of the first clock signal. Generating a second clock signal, outputting a first clock signal through a first wire connected to some gate driver integrated circuits adjacent to the controller among the plurality of gate driver integrated circuits, and outputting the first clock signal through the remaining gate driver integrated circuits. A method of driving a controller may include outputting a second clock signal through a second wire connected to the gate driver integrated circuit.

According to the present embodiments, a clock signal is output through a first wire and a second wire to a plurality of gate driver integrated circuits arranged in a gate driver, so that the clock signal can be input in both directions.

According to the present embodiments, clock signals output to a plurality of gate driver integrated circuits are input in both directions, thereby reducing the load on the clock signals and preventing signal distortion.

According to the present embodiments, by adjusting the phase of the clock signal input in both directions, the delay of the clock signal generated along the wiring to which the clock signal is input is prevented and the luminance deviation due to the delay of the clock signal is prevented from occurring. .

1 is a diagram showing a schematic configuration of a display device according to the present embodiments.
2 is a diagram illustrating an example of outputting a gate signal in a display device according to the present embodiments.
3 is a diagram illustrating an example of delay of a gate signal caused by a load of a display device.
4 and 5 are diagrams illustrating an example of a connection structure between a controller and a gate driver integrated circuit in a display device according to the present embodiments.
6 is a diagram illustrating an example of adjusting a phase of a clock signal according to a wire to which the clock signal is input in the display device according to the present embodiments.
7 is a diagram illustrating an example of outputting a gate signal whose phase is adjusted in the display device according to the present embodiments.
8 is a diagram illustrating a process of a method of driving a controller according to the present embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention are described in detail below with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the component from other components, and the nature, sequence, order, or number of the corresponding component is not limited by the term. When an element is described as being “connected,” “coupled to,” or “connected” to another element, that element is or may be directly connected to that other element, but intervenes between each element. It will be understood that may be "interposed", or each component may be "connected", "coupled" or "connected" through other components.

1 is a diagram showing a schematic configuration of a display device 100 according to the present embodiments.

Referring to FIG. 1 , in the display device 100 according to the present embodiments, a plurality of gate lines GL and a plurality of data lines DL are disposed and the gate lines GL and the data lines DL cross each other. A data voltage is supplied to the display panel 110 including the plurality of pixels 200 disposed in the area where the data voltage is formed, the gate driver 120 driving the plurality of gate lines GL, and the plurality of data lines DL. and a controller 140 that controls driving of the data driver 130, the gate driver 120, and the data driver 130.

The gate driver 120 sequentially drives the plurality of gate lines GL by sequentially supplying scan signals (gate signals) to the plurality of gate lines GL.

The data driver 130 drives the plurality of data lines DL by supplying data voltages to the plurality of data lines DL.

The controller 140 controls the gate driver 120 and the data driver 130 by supplying various control signals to the gate driver 120 and the data driver 130 .

The controller 140 starts scanning according to the timing implemented in each frame, converts input image data input from the outside to suit the data signal format used by the data driver 130, and outputs the converted image data. , data drive is controlled at an appropriate time according to the scan.

The gate driver 120 sequentially supplies a gate signal of an on voltage or an off voltage to the plurality of gate lines GL under the control of the controller 140 to operate the plurality of gate lines GL. run sequentially.

The gate driver 120 may be located on only one side of the display panel 110 or on both sides of the display panel 110 depending on the driving method.

In addition, the gate driver 120 may include one or more gate driver integrated circuits.

Each gate driver integrated circuit is connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method, or by a GIP ( Gate In Panel) type and can be directly disposed on the display panel 110 . In addition, it may be integrated and disposed on the display panel 110 or may be implemented in a chip on film (COF) method mounted on a film connected to the display panel 110 .

When a specific gate line GL is opened, the data driver 130 converts the image data received from the controller 140 into an analog data voltage and supplies it to the plurality of data lines DL, thereby reducing the number of data lines DL. drive

The data driver 130 may include at least one source driver integrated circuit to drive a plurality of data lines DL.

Each source driver integrated circuit is connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method, or It may be directly disposed on 110 or may be integrated and disposed on display panel 110 .

In addition, each source driver integrated circuit may be implemented in a Chip On Film (COF) method. In this case, one end of each source driver integrated circuit is bonded to at least one source printed circuit board, and the other end is bonded to the display panel 110 .

The controller 140 generates various timing signals including a vertical sync signal (Vsync), a horizontal sync signal (Hsync), an input data enable (DE) signal, and a clock signal (CLK) together with the input image data. Receive from outside (e.g. host system).

The controller 140 converts the input video data input from the outside to suit the data signal format used by the data driver 130 and outputs the converted video data, as well as the gate driver 120 and the data driver 130. In order to control the gate driver ( 120) and the data driver 130.

For example, in order to control the gate driver 120, the controller 140 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE: It outputs various gate control signals (GCS: Gate Control Signal) including Gate Output Enable) and the like.

Here, the gate start pulse GSP controls the operation start timing of one or more gate driver integrated circuits constituting the gate driver 120 . The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits, and controls the shift timing of the gate signal. The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits.

In addition, the controller 140, in order to control the data driver 130, a source start pulse (SSP: Source Start Pulse), a source sampling clock (SSC: Source Sampling Clock), a source output enable signal (SOE: Source Output It outputs various data control signals (DCS) including Enable) and the like.

Here, the source start pulse SSP controls data sampling start timing of one or more source driver integrated circuits constituting the data driver 130 . The source sampling clock (SSC) is a clock signal that controls sampling timing of data in each source driver integrated circuit. The source output enable signal SOE controls output timing of the data driver 130 .

The controller 140 is a source printed circuit board to which the source driver integrated circuit is bonded and a control printed circuit board connected through a connection medium such as a flexible flat cable (FFC) or a flexible printed circuit (FPC). (Control Printed Circuit Board).

On this control printed circuit board, a power controller (not shown) is further disposed to supply various voltages or currents to the display panel 110, gate driver 120, and data driver 130 or to control various voltages or currents to be supplied. It can be. Such a power controller is also referred to as a power management IC.

The plurality of pixels 200 are disposed in an area where the gate line GL and the data line DL intersect, and data is output from the data driver 130 when a gate signal is output by the gate driver 120. It receives voltage and displays an image.

That is, each pixel 200 displays an image by the data voltage supplied between the time when the gate line GL is turned on and off by the gate signal.

FIG. 2 shows gate signals output to a plurality of gate driver integrated circuits 121, 122, 123, and 124 disposed in the gate driver 120 of the display device 100 according to the present embodiments and the gate line GL. example was shown.

Referring to FIG. 2 , a plurality of gate driver integrated circuits 121 , 122 , 123 , and 124 may be disposed in the gate driver 120 .

The plurality of gate driver integrated circuits 121 , 122 , 123 , and 124 are connected to the controller 140 and receive the clock signal CLK output from the controller 140 .

As shown in FIG. 2, the plurality of gate driver integrated circuits 121, 122, 123, and 124 are connected to the controller 140 through a single wire, so that the clock signal CLK output from the controller 140 is unidirectionally input. It can be.

Each of the gate driver ICs 121, 122, 123, and 124 has a gate line GL connected to the gate driver ICs 121, 122, 123, and 124 according to the clock signal CLK input from the controller 140. outputs a gate signal.

2 shows that one gate line GL is connected to one gate driver integrated circuit 121, 122, 123, 124, but a plurality of gate driver integrated circuits 121, 122, 123, 124 are connected to one gate line GL. A gate line GL may be connected.

Gate signals output from each of the gate driver integrated circuits 121, 122, 123, and 124 have the same phase and width, and gate signals shifted at regular intervals for each gate line GL are input.

Specifically, the controller 140 outputs the clock signal CLK to each of the gate driver integrated circuits 121, 122, 123, and 124 and sends a gate start pulse GSP to the first gate driver integrated circuit 121. print out

When receiving the gate start pulse GSP, the first gate driver integrated circuit 121 sequentially outputs gate signals shifted at regular intervals to each gate line GL using the clock signal CLK.

When a gate signal is output to all gate lines GL connected to the first gate driver IC 121, the first gate driver IC 121 sends a gate start pulse (GSP) to the second gate driver IC 122. send

When receiving the gate start pulse GSP, the second gate driver integrated circuit 122 outputs a gate signal to each gate line GL connected to the second gate driver integrated circuit 122 .

In this way, gate signals are sequentially output to each of the gate lines GL connected to the plurality of gate driver integrated circuits 121 , 122 , 123 , and 124 disposed on the gate driver 120 .

At this time, the gate signal output to each gate line GL is generated using the clock signal CLK having the same phase and width, but the wire to which the clock signal CLK is applied and the load in the display panel 110 ( A delay may occur in a gate signal input to the gate line GL by a load or the like.

3 illustrates an example of a case where a delay occurs in the clock signal CLK in a structure in which the clock signal CLK is unidirectionally input.

Referring to FIG. 3 , assuming that N gate lines GL are disposed on the display panel 110, 301 represents a waveform of a gate signal input to the first gate line GL and 302 represents the N th gate line. It shows the waveform of the gate signal input to the line GL.

The controller 140 inputs the clock signal CLK having the same phase and width to the gate driver integrated circuits 121, 122, 123, and 124, and uses it to generate the gate driver integrated circuits 121, 122, 123, and 124. Even if a gate signal is output from , a delay may occur in a gate signal input to the N-th gate line GL by a load in the display panel 110 .

The delay of the gate signal causes the waveform of the gate signal to be distorted, and in this case, the time for supplying the data voltage is reduced by the delayed time, thereby reducing the luminance of the pixel 200 driven by the corresponding gate signal.

This has a problem of causing a luminance deviation for each position of the display panel 110 .

The present embodiments provide a structure and method for inputting a clock signal CLK to prevent distortion and luminance deviation of the gate signal.

4 illustrates a connection structure between a controller 140 and gate driver integrated circuits 121, 122, 123, and 124 in the display device 100 according to the present embodiments, in which a clock signal CLK is input in both directions. shows the structure.

Referring to FIG. 4 , a plurality of gate driver integrated circuits 121 , 122 , 123 , and 124 disposed in the gate driver 120 are connected to the controller 140 through two wires 150 and 160 .

For example, among the plurality of gate driver integrated circuits 121, 122, 123, and 124, the gate driver integrated circuits 121 and 122 located in an area adjacent to the controller 140 are connected to the controller ( 140) is connected.

In addition, the remaining gate driver ICs 123 and 124 not connected to the first wiring 150 among the plurality of gate driver ICs 121, 122, 123, and 124 are connected to the controller 140 through the second wiring 160. ) is connected to

Here, the first wire 150 may be disposed on one side of the plurality of gate driver integrated circuits 121, 122, 123, and 124, and the second wire 160 may be disposed on one side of the plurality of gate driver integrated circuits 121, 122, 123, 124) may be disposed on the other side.

That is, the first wiring 150 and the second wiring 160 may be disposed on both sides of the gate driver integrated circuits 121, 122, 123, and 124, respectively.

The controller 140 outputs the first clock signal CLK1 to the gate driver integrated circuits 121 and 122 connected to the first wire 150 through the first wire 150 .

In addition, the controller 140 outputs the second clock signal CLK2 to the gate driver integrated circuits 123 and 124 connected to the second wire 150 through the second wire 160 .

The controller 140 outputs a gate start pulse (GSP) to the first gate driver integrated circuit 121 connected to the first wire 150, and receives the gate start pulse (GSP) to the first gate driver integrated circuit ( 121) sequentially outputs gate signals to each connected gate line GL.

When the output of the gate signal is completed, the first gate driver integrated circuit 121 transmits a gate start pulse (GSP) to the second gate driver integrated circuit 122 so that the second gate driver integrated circuit 122 sequentially transmits the gate signal. to be output as

The last gate driver integrated circuit connected to the first wire 150 and the first gate driver integrated circuit connected to the second wire 160 are connected to each other so that the gate start pulse GSP can be transmitted.

That is, the gate start pulse GSP output from the controller 140 is output through the first wire 150 and then sequentially transferred to the gate driver integrated circuits 121, 122, 123, and 124, and the clock signal CLK ) is distributed to the first wiring 150 and the second wiring 160 and input to the respective gate driver integrated circuits 121, 122, 123, and 124.

Therefore, compared to a structure in which the controller 140 and all the gate driver integrated circuits 121, 122, 123, and 124 are connected through a single wire and the clock signal CLK is unidirectionally input, the clock output from the controller 140 By distributing the signal CLK to two wires, a delay of the clock signal CLK due to a load of the wires can be reduced.

5 illustrates another example of a connection structure between the controller 140 and the gate driver integrated circuits 121, 122, 123, and 124 in the display device 100 according to the present exemplary embodiments.

Referring to FIG. 5 , the controller 140 includes gate driver ICs 121 and 122 adjacent to the controller 140 among a plurality of gate driver ICs 121 , 122 , 123 , and 124 disposed on the gate driver 120 . and is connected through the first wire 150.

The controller 140 connects the remaining gate driver integrated circuits 123 and 124 and the second wire 160 that are not connected through the first wire 150 among the plurality of gate driver integrated circuits 121 , 122 , 123 and 124 . connected through

In this case, the first wiring 150 may be disposed on one side of the plurality of gate driver integrated circuits 121 , 122 , 123 , and 124 .

Further, the second wiring 160 may be disposed on the other side of the plurality of gate driver integrated circuits 121, 122, 123, and 124, and on one side of the plurality of gate driver integrated circuits 121, 122, 123, and 124. It may be disposed in an area where the first wiring 150 is not disposed.

That is, as shown in FIG. 5, the second wire 160 is disposed on the other side of the plurality of gate driver integrated circuits 121, 122, 123, and 124 on which the first wire 150 is not disposed, and the last gate Passing through the lower portion of the driver IC 124, it may be disposed in the plurality of gate driver ICs 121, 122, 123, and 124.

A portion of the second wiring 160 disposed on one side of the plurality of gate driver integrated circuits 121 , 122 , 123 , and 124 may be connected to each of the gate driver integrated circuits 123 and 124 .

Therefore, two wires connecting the controller 140 and the gate driver integrated circuits 121, 122, 123, and 124 are placed in the gate driver 120, but the gate driver integrated circuits 121, 122, 123, and 124 The connected portion may be located on the same side of the gate driver integrated circuits 121, 122, 123, and 124.

The portion where the first wire 150 and the second wire 160 are connected to the gate driver integrated circuits 121, 122, 123, and 124 is located on the same side of the gate driver integrated circuits 121, 122, 123, and 124. By doing so, it is possible to minimize an increase in the width of the region where the gate driver 120 is disposed even when two wires are disposed.

Meanwhile, by distributing and inputting the clock signal CLK through the first wiring 150 and the second wiring 160, the delay of the gate signal can be reduced compared to the input structure using a single wiring, but the first wiring 150 ) and the load of the second wire 160, a delay may occur in the clock signal CLK.

That is, compared to the first wiring 150 for inputting the clock signal CLK to the gate driver integrated circuits 121 and 122 close to the controller 140, the gate driver integrated circuits 123 and 124 far from the controller 140 A load of the second wire 160 inputting the clock signal CLK may be greater.

Therefore, the clock signal CLK input through the second wire 160 may be delayed compared to the clock signal CLK input through the first wire 150 .

The present embodiments adjust the phase of the clock signal CLK in a structure in which the clock signal CLK is bidirectionally input to the plurality of gate driver integrated circuits 121, 122, 123, and 124, thereby increasing the clock signal CLK. to prevent waveform distortion.

6 illustrates an example of a waveform of a clock signal CLK input through the first wire 150 and the second wire 160 in the display device 100 according to the present exemplary embodiments.

Referring to FIG. 6 , the waveform of the first clock signal CLK1 input to the first wire 150 may be represented as 601 .

The first wiring 150 is a wiring connecting the controller 140 and the gate driver integrated circuits 121 and 122 adjacent to each other, and the delay of the clock signal CLK is not large because the load is not large.

Accordingly, the controller 140 outputs the first clock signal CLK1 having the same phase and width as 601 to the gate driver integrated circuits 121 and 122 connected to the first wiring 150 .

Since the load of the second wiring 160 connecting the gate driver integrated circuits 123 and 124 that are not adjacent to the controller 140 is greater than that of the first wiring 150, the first clock signal CLK1 and When the second clock signal CLK2 having the same phase and width is input, a delay may occur as in step 602 .

This delay causes distortion of the gate signal output through the corresponding gate driver integrated circuits 123 and 124, and due to the distortion of the gate signal, a sufficient time for supplying the data voltage may not be secured.

Accordingly, the controller 140 may adjust the phase of the second clock signal CLK2 input to the gate driver integrated circuits 123 and 124 connected to the second wire 160 as shown in 603 and output the same.

That is, the controller 140 advances the phase of the second clock signal CLK2 output through the second wire 160 having a greater load than the first wire 150 than the phase of the first clock signal CLK1. can be printed out.

Here, the adjusted phase of the second clock signal CLK2 is based on the delay value of the gate signal output by the gate driver integrated circuits 123 and 124 receiving the clock signal CLK through the second wire 160. so it can be advanced.

For example, by advancing the phase of the clock signal CLK by a corresponding delay value based on the delay value of the gate signal output by the gate driver integrated circuit 124, the data voltage is supplied even if the gate signal is distorted. to ensure that this is sufficient.

Therefore, according to the present embodiments, the clock signal CLK output from the controller 140 is distributed through two wires and output to the gate driver integrated circuits 121, 122, 123, and 124, so that a single wire is used. It allows the load to be reduced compared to the case of

In addition, the second clock signal CLK2 input to the second wire 160 having a higher load than the first wire 150 causes a load of the first wire 150 and the second wire 160. By outputting the signal with an advanced phase based on the signal delay value according to the difference in , luminance deviation does not occur despite the delay of the gate signal according to the second clock signal CLK2 input to the second wire 160.

7 illustrates an example of a gate signal output in a structure in which clock signals CLK having different phases are input in both directions in the display device 100 according to the present exemplary embodiments.

Referring to FIG. 7 , the controller 140 is connected to a plurality of gate driver integrated circuits 121 , 122 , 123 , and 124 through a first wire 150 and a second wire 160 .

The controller 140 outputs the first clock signal CLK1 having the same phase and width to the first wire 150 connected to the gate driver integrated circuits 121 and 122 positioned adjacent to the controller 140 .

Accordingly, as shown in FIG. 7 , gate signals having the same phase and width are output from the gate driver integrated circuits 121 and 122 connected to the first wiring 150 .

The controller 140 outputs the second clock signal CLK2 having an advanced phase compared to the first clock signal CLK1 to the gate driver integrated circuits 123 and 124 connected to the second wire 160 .

The gate driver integrated circuits 123 and 124 connected to the second wiring 160 output gate signals based on the second clock signal CLK2 having an advanced phase.

Therefore, as shown in FIG. 7 , gate signals output from the gate driver integrated circuits 123 and 124 connected to the second wire 160 and the gate driver integrated circuits 121 and 122 connected to the first wire 150 A gate signal having an advanced phase is output.

Since a gate signal having an advanced phase is output from the gate driver integrated circuits 123 and 124 connected to the second wiring 160, sufficient time for supplying the data voltage is secured even if the waveform of the gate signal is distorted due to the delay of the gate signal. make it possible

8 illustrates a process of a method of driving the controller 140 outputting the clock signal CLK in the display device 100 according to the present embodiments.

Referring to FIG. 8 , the controller 140 generates the first clock signal CLK1 having the same phase and width (S800).

The controller 140 generates a second clock signal CLK2 having a phase advanced than that of the first clock signal CLK1 (S820).

The controller 140 outputs the first clock signal CLK1 to the first wiring 150 connected to the gate driver integrated circuits 121 and 122 disposed adjacent to the controller 140 (S840), and then outputs the remaining gate drivers. The second clock signal CLK2 is output to the second wire 160 connected to the integrated circuits 123 and 124 (S860).

Therefore, by bidirectionally inputting the clock signal CLK output to the plurality of gate driver integrated circuits 121, 122, 123, and 124, the load is reduced compared to a structure in which the clock signal CLK is input through a single wire. enable it to be reduced.

In addition, the phase of the second clock signal CLK2 output through the second wire 160 having a higher load than the first wire 150 is determined by considering the difference in the load of each wire. By outputting ahead of the first clock signal CLK1, it is possible to compensate for a signal delay due to a difference in load of the wiring.

Through this, distortion of the gate signal output to each gate line GL is reduced, and luminance deviation by position of the display panel 110 due to distortion of the gate signal is prevented from occurring.

The above description is merely an example of the technical idea of the present invention, and various modifications and variations can be made to those skilled in the art without departing from the essential characteristics of the present invention. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain, so the scope of the technical idea of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device 110: display panel
120: gate driver
121, 122, 123, 124: gate driver integrated circuit
130: data driver 140: controller
150: first wiring 160: second wiring

Claims (13)

a gate driver having a plurality of gate driver integrated circuits disposed thereon, connected to the gate driver integrated circuits, and outputting gate signals to a plurality of gate lines disposed on a display panel;
a controller outputting clock signals to the plurality of gate driver integrated circuits;
a first wiring connecting the controller and some gate driver integrated circuits adjacent to the controller among the plurality of gate driver integrated circuits; and
A second wiring connecting the controller and the remaining gate driver integrated circuits among the plurality of gate driver integrated circuits.
including,
The phase of the clock signal output from the controller through the second wire is advanced by a value greater than 0 degrees and smaller than 180 degrees compared to the phase of the clock signal output from the controller through the first wire.
According to claim 1,
The first wire is disposed on one side of the gate driver integrated circuit, and the second wire is disposed on the other side of the gate driver integrated circuit.
According to claim 2,
The second wire is disposed in an area where the first wire is not disposed between the other side of the gate driver integrated circuit and one side of the gate driver integrated circuit.
delete delete According to claim 1,
The phase of the clock signal output from the controller through the second wire is a signal delay value according to the difference between the load for the clock signal output through the first wire and the load for the clock signal output through the second wire. A display device calibrated based on
According to claim 1,
A phase of a clock signal output from the controller through the second wire is adjusted based on a signal delay value according to a difference between a length of the first wire and a length of the second wire.
A plurality of gate driver integrated circuits are disposed, and the plurality of gate driver integrated circuits are composed of a first group including some gate driver integrated circuits adjacent to the controller and a second group including the remaining gate driver integrated circuits,
a first wiring connecting the controller and gate driver integrated circuits included in the first group; and
A second wire connecting the controller and the gate driver IC included in the second group
including,
The phase of the clock signal output from the controller through the second wire is advanced by a value greater than 0 degrees and smaller than 180 degrees compared to the phase of the clock signal output from the controller through the first wire.
According to claim 8,
The first wire is disposed on one side of the gate driver integrated circuit, and the second wire is disposed on the other side of the gate driver integrated circuit.
delete According to claim 8,
The phase of the clock signal input from the controller through the second wire is based on the signal delay value according to the difference between the loads of the first wire and the second wire, and the clock signal input from the controller through the first wire Gate driver advanced relative to the phase of .
A method for driving a controller that outputs a clock signal to a plurality of gate driver integrated circuits arranged in a gate driver,
generating a second clock signal having a phase different from that of the first clock signal by advancing the first clock signal and a phase of the first clock signal by a value greater than 0 degrees and less than 180 degrees;
outputting the first clock signal through a first wire connected to some gate driver integrated circuits adjacent to the controller among the plurality of gate driver integrated circuits; and
and outputting the second clock signal through a second wire connected to the remaining gate driver integrated circuits among the plurality of gate driver integrated circuits.
According to claim 12,
Generating the first clock signal and a second clock signal having a phase different from that of the first clock signal,
and generating the second clock signal having a phase advanced from that of the first clock signal based on a signal delay value according to a difference between a load of the first wire and a load of the second wire.

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