KR102493107B1 - Frame grabber system and method of storing control signal related information for peripheral device with image frame, computer program and computer-readable recording medium - Google Patents

Abstract

The present invention relates to a frame grabber system, comprising: a frame grabber including a frame information field; and a processor for outputting a control signal for controlling a peripheral device based on a synchronization signal, synchronizing with the synchronization signal and adding the image frame captured by the camera module to storing information on the control signal in the frame information field. do. In this way, it is possible to improve the quality of an image captured by the camera by controlling lighting under optimal conditions.

Description

Frame grabber system and method for storing information on control signals of peripheral devices together with image frames, computer program and computer readable recording medium computer program and computer-readable recording medium}

The present invention relates to a frame grabber system and a control method thereof, and more particularly, to a frame grabber system and a control method thereof for storing information on a control signal of a peripheral device together with an image frame.

In order to quickly obtain accurate images in high-speed shooting, camera inspection, and speed enforcement of automobiles, a camera with a high shooting speed is required. For this reason, camera manufacturers are constantly improving their sensors and improving their interfaces. However, just because the shooting speed of the camera is fast does not solve all problems.

The high photographing speed of the camera means that the time taken to photograph an image once, that is, the shutter exposure time is shortened. The shorter the shutter exposure time, the lower the amount of light input, and the darker the image is captured. In order to obtain an image with the same brightness even if the shutter exposure time is shortened, the amount of light of the light or the sensitivity of the camera sensor must be increased.

For example, when inspecting a camera, conventionally, in a state where the amount of light is fixed, the gain value of the camera sensor is adjusted through I2C communication, and the exposure value (shutter exposure time) is calculated using software (SW) and The comparison was repeated. However, this conventional method has a low operation rate (UPH), the operator must know detailed information about the gain prior to software operation, and the tact time and CPU occupancy are high due to the algorithm for controlling the gain on the software. In addition, since the light must be continuously turned on brightly, there are problems of consuming a lot of power and shortening the lifespan of the light. In addition, there is a limit to adjusting the gain of the camera sensor, and there is also a limit to increasing the amount of light.

Therefore, there is a need for a technique capable of improving the quality of an image captured by a camera by controlling lighting under optimal conditions.

KR 2076203 B1 KR 2017-0108392 A

Accordingly, an object of the present invention is to provide a frame grabber system and its control method capable of improving the quality of an image captured by a camera by controlling lighting under optimal conditions.

Another object of the present invention is to provide a frame grabber system and method for controlling the same that enable more accurate automatic control of peripheral devices by storing information on control signals of peripheral devices together with video frames.

Another object of the present invention is to provide a frame grabber system and a control method thereof that enable realization of a lighting control technology that reacts in synchronization with a trigger signal of a camera precisely.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

The above object is, according to the first aspect of the present invention,

a frame grabber including a frame information field; and

A processor for outputting a control signal for controlling a peripheral device based on a synchronization signal, synchronizing with the synchronization signal, and storing information on the control signal in the frame information field by adding it to an image frame captured by the camera module. , which is achieved by a frame grabber system.

At this time, the image frame is composed of a plurality of horizontal lines,

The frame information field includes information on the video frame and information on the control signal for each line of the video frame, and the information on the control signal includes control for controlling a peripheral device based on the synchronization signal. These may be factors used to determine whether or not to output a signal.

In particular, when the peripheral device is a lighting device and the control signal is a signal for controlling on/off of the lighting device, information on the control signal is factors used to determine the on/off timing of the lighting device. .

Meanwhile, the synchronization signal may be output from the frame grabber receiving the image frame from the camera module or may be output from the processor.

Furthermore, the processor

an input signal trigger unit that checks whether the synchronization signal is input;

an internal logic state determination unit determining whether to operate in synchronization with the synchronization signal;

a timing counting unit counting to determine timing of the control signal to be output based on the synchronization signal; and

A signal output unit configured to output the control signal in synchronization with the synchronization signal may be included.

The above object is also according to the second aspect of the present invention,

In the control method executed in the frame grabber system,

outputting a control signal for controlling a peripheral device based on the synchronization signal; and

and storing information on the control signal in the frame information field in addition to an image frame captured by a camera module in synchronization with the synchronization signal.

The above object is also according to the third aspect of the present invention,

This is achieved by a computer readable recording medium recording a program for performing the above method.

Furthermore, the above object is also according to the fourth aspect of the present invention,

It is achieved by a computer program stored in a medium for executing the above method through combination with hardware.

According to the frame grabber system and its control method of the present invention as described above, there is an advantage in that the quality of an image captured by a camera can be improved by controlling lighting under optimal conditions.

In addition, the frame grabber system and method for controlling the same according to the present invention have the advantage of enabling more accurate automatic control of peripheral devices by storing information on control signals of peripheral devices together with video frames.

In addition, according to the frame grabber system and its control method of the present invention, there is an advantage in that it is possible to implement a lighting control technology that reacts in synchronization with a trigger signal of a camera precisely.

1 is a schematic functional block diagram of a frame grabber system according to the present invention.
2 is a detailed functional block diagram of a frame grabber system according to an embodiment of the present invention.
FIG. 3 is a schematic diagram illustrating the operation of the frame grabber system according to an embodiment of the present invention of FIG. 2 .
4 is an example of a flowchart schematically illustrating the operation of the input signal triggering unit 201 of FIG. 2 .
FIG. 5 is an example of a flowchart schematically illustrating an operation of the internal logic state determination unit 202 of FIG. 2 .
6 and 7 are examples of flowcharts schematically illustrating the operation of the timing counting unit 203 of FIG. 2 .
8 is an example of a flowchart schematically illustrating the operation of the signal output unit 206 of FIG. 2 .
9 is an example of a flowchart schematically illustrating an operation of the calibration unit 205 of FIG. 2 .
10 is a diagram showing a timing diagram according to an automatic adjustment operation according to an embodiment of the present invention.
Each of FIGS. 11, 12 and 13 is a schematic diagram showing an example of the frame information field 100 of FIG. 1 .

Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the contents described in the accompanying drawings. However, the present invention is not limited or limited by exemplary embodiments. The same reference numerals presented in each figure indicate members performing substantially the same function.

Terms including ordinal numbers, such as first and second, may be used to describe various components, but the components are not limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, a first element may be termed a second element, and similarly, a second element may also be termed a first element, without departing from the scope of the present invention. Terms used in this application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly dictates otherwise.

The terms used in the present invention have been selected from general terms that are currently widely used as much as possible while considering the functions in the present invention, but these may vary depending on the intention of a person skilled in the art or precedent, the emergence of new technologies, and the like. In addition, in a specific case, there is also a term arbitrarily selected by the applicant, and in this case, the meaning will be described in detail in the description of the invention. Therefore, the term used in the present invention should be defined based on the meaning of the term and the overall content of the present invention, not simply the name of the term.

When it is said that a certain part "includes" a certain component throughout the specification, it means that it may further include other components without excluding other components unless otherwise stated.

1 is a schematic functional block diagram of a frame grabber system according to the present invention.

Referring to the drawings, a frame grabber system 1 of the present invention includes a frame grabber 10 including a frame information field 100; and outputting a control signal for controlling the peripheral device 30 based on the synchronization signal, synchronizing with the synchronization signal and adding the information to the image frame captured by the camera module 40 to frame information on the control signal. and the processor 20 to store in the field 100.

This frame grabber system can be built on an FPGA, a type of programmable non-memory semiconductor.

A frame grabber digitizes an analog video signal, which is generally displayed through video media such as TVs and CCD cameras, into a signal that can be processed by a computing device, such as a smartphone or PC, by digitizing it with a defined bit per sample. As a video equipment that changes, it is also called an image board. In the present invention, any device may be used as long as it is a device that collects images and stores the collected images in a storage device in a computer or a special storage location for storing images.

The frame grabber 10 of the present invention stores image data, that is, an image frame, input from a camera module like a conventional frame grabber, but furthermore, information about the environment at the time the image frame is captured, for example, an image frame Information on operation control of peripheral devices that can affect color and/or luminance values of constituent pixels is stored in the frame information field 100 . Information on this environment is not excluded from being stored in a frame information field separated from the image frame, but may be attached to the corresponding image frame in a dummy form and stored together with the image frame.

The processor 20 generates a control signal capable of controlling the operation of the peripheral device as described above and outputs the control signal to the peripheral device to create an environment at the time the image frame is captured. The information on the control signal corresponding to the factors used to generate is transferred to the frame grabber 10 so that it can be stored.

An image frame to be captured by the camera module 40 and a control signal output from the processor 20 are synchronized by a synchronization signal, in which the synchronization signal received from the camera module 40 is output to the processor 20. or may be generated by the processor 20 itself and output internally. In the case where the synchronization signal is received from the camera module 40 and output to the processor 20, the synchronization signal may be a vertical synchronization signal Vsync received by a frame grabber collecting existing image frames. On the other hand, for example, in the case of a test mode in which a control signal capable of controlling the operation of a peripheral device can be output even when the camera module 40 is not present, a synchronization signal can be generated by the processor 20 itself. there is.

2 is a detailed functional block diagram of a frame grabber system according to an embodiment of the present invention, and FIG. 3 is a schematic diagram showing the operation of the frame grabber system of FIG. 2 according to an embodiment of the present invention. In particular, FIGS. 2 and 3 illustrate cases in which a peripheral device whose operation is to be controlled is a lighting device in the present invention.

Referring to FIG. 2 , a frame grabber system 1 according to an embodiment of the present invention includes a frame grabber 10 and a processor 20. The processor 20 includes an input signal trigger unit 201, It includes an internal logic state determination unit 202, a timing counting unit 203, an internal vertical synchronization generator 204, a calibration unit 205, a signal output unit 206, and an output signal information return unit 207. .

Referring back to the drawing, the frame grabber 10 initializes the camera module 40 to output image data corresponding to an image frame, and receives image data of the image frame from the camera module 40 . The frame grabber 10 may include a frame information field 100 containing information on an image frame to be captured and control signals to control lighting and other devices, that is, information on output signals. A detailed description of the frame information field 100 will be described later.

The processor 20 outputs a control signal to the lighting controller 50 so that the lighting controller 50 controls the lighting device 30 . To this end, the processor 20 includes an input signal trigger unit 201, an internal logic state determination unit 202, a timing counting unit 203, an internal vertical synchronization generator 204, a calibration unit 205, and a signal output unit. 206, and an output signal information return unit 207.

The input signal trigger unit 201 is a vertical synchronization (Vsync) detection unit, and functions to check whether a vertical synchronization (Vsync) signal of an image frame is input from the camera module 40 through the frame grabber 10.

4 is an example of a flowchart schematically illustrating the operation of the input signal triggering unit 201 of FIG. 2 .

As shown in FIG. 4, ① the input signal trigger unit 201 determines whether to detect a rising edge or a falling edge, that is, as a way to prevent an error in which erroneous data enters the buffer, the edge mode It changes the initial value of the vertical synchronization (Vsync) buffer according to

② The input signal triggering unit 201 checks whether the condition to trigger the vertical sync (Vsync) signal is met, and ③ stacks the vertical sync (Vsync) signal in the buffer when the condition to be triggered is met.

④ The input signal triggering unit 201 detects the edge of the vertical synchronization (Vsync) signal according to the state of the buffer.

The internal logic state determination unit 202 functions to determine whether to operate the processor 20 (active condition) or not (idle condition) according to a vertical synchronization (Vsync) signal.

FIG. 5 is an example of a flowchart schematically illustrating an operation of the internal logic state determination unit 202 of FIG. 2 .

As shown in FIG. 5 , the internal logic state determination unit 202 determines whether to operate the internal logic (active condition) or not operate (idle condition) according to conditions of signals involved in the operation of the internal logic. If the internal logic is determined to be in an operable condition, the internal logic state becomes active (②), then the internal logic is in an operable state, otherwise, the internal logic state becomes idle (①), and then The internal logic of is in an inoperable state.

The timing counting unit 203 performs counting to determine the waveform and timing of the control signal to be output based on the vertical synchronization (Vsync) signal.

6 and 7 are examples of flowcharts schematically illustrating the operation of the timing counting unit 203 of FIG. 2 .

As shown in FIG. 6 , the timing counting unit 203 may determine other internal operation modes according to user input values, for example, ON_PERIOD, OFF_PERIOD, and REPEAT_NUM. At this time, ON_PERIOD is the light-on period in which the light is turned on n times, OFF_PERIOD is the light-off period in which the light is turned off n times, REPEAT_NUM is the light ON/OFF period n times. It may be repeated as many times as times.

As shown in FIG. 7, the timing counting unit 203 determines conditions for outputting signals according to timing counting. That is, the timing of the output signal is controlled. When the counting condition is reached, counting starts according to the user input value, for example ON_PERIOD, OFF_PERIOD, and the condition for outputting the signal is determined according to the counting value.

The internal vertical synchronization generator 204 functions to output a vertical synchronization (Vsync) signal for testing even when the camera module 40 is not present. That is, a vertical synchronization (Vsync) signal is generated internally without external input.

The signal output unit 206 outputs a control signal based on an internal logic state and counting condition. Here, the number of output signals may be two or more, for example, when there are many types of peripheral devices whose operations are to be controlled, or when the number is plural.

8 is an example of a flowchart schematically illustrating the operation of the signal output unit 206 of FIG. 2 .

As shown in FIG. 8, the signal output unit 206 checks whether it is in an active state (①), and if it is in an active state, whether to turn the output signal on/off (ON/OFF) or bypass it according to the condition of the external input (bypass)

In the ON/OFF condition, an ON signal or an OFF signal is output according to the counting condition based on the delay and pulse width values (①).

In the bypass condition, the vertical synchronization (Vsync) signal is output as it is (②).

The calibration unit 205 functions to automatically adjust the timing of the output signal inside the Field Programmable Gate Array (FPGA) without external input.

9 is an example of a flowchart schematically illustrating an operation of the calibration unit 205 of FIG. 2 .

As shown in FIG. 9 , the calibration unit 205 checks whether the number of frames per second (FPS) is normal when an auto-calibration enable signal (Calibration_en==True) is input from the user. The calibration unit 205 sequentially adjusts a start timing and a pulse width value based on frames per second (FPS). When the adjustment is completed, the operation is terminated.

10 is a diagram showing a timing diagram according to an automatic adjustment operation according to an embodiment of the present invention.

Referring to FIG. 10, (1) continuously changing the start timing of an output signal is repeated, and video frames are continuously captured in synchronization with a vertical synchronization (Vsync) signal. At this time, for example, output signal 2 indicates a time later than output signal 1, and output signal 3 indicates a time later than output signal 2. Next, ② is changed to a pulse width of an output signal different from the pulse width of the output signal of ①, and ① is repeated. Repeat ② continuously. Here, the degree of changing the start timing and the degree of changing the pulse width depend on the number of frames per second (FPS) of the camera sensor.

Accordingly, by using the frame grabber system according to an embodiment of the present invention having an automatic adjustment function, information on a control signal of a peripheral device can be stored together with a plurality of image frames for each image frame. do.

Next, a series of image processing is performed on each of the continuously captured image frames to derive an average value, and an image frame closest to the target value is found by comparing the average value with the target value. At this time, information on the control signal of the peripheral device is read from the frame information field of the corresponding image frame, and the control signal is set equal to the information value of the corresponding control signal.

Returning to FIG. 2 again, the output signal information returning unit 207 returns information on the output signal to the frame grabber 10.

On the other hand, the operation of the frame grabber system 1 can be controlled through software (application, app) while the user checks the image using the computer (PC, 60) and the monitor 70. Through a software program, a user may set how to output a control signal - for example, by inputting decision factors - and process the captured image frame.

An operation of the frame grabber system 1 according to an embodiment of the present invention will be described with reference to FIG. 3 which is a schematic diagram showing the operation of the frame grabber system according to an embodiment of the present invention in FIG. 2 .

First, the camera module is initialized so that the camera module 40 can output image data corresponding to the video frame (S200), and through a software program, the user determines how to output a control signal - for example, how much delay and how much to increase the pulse width - is determined and input (S210).

Next, it is checked whether the vertical synchronization (Vsync) signal of the image frame is input from the camera module 40 through the frame grabber 10 (S201), and if the vertical synchronization (Vsync) signal is input, the processor ( 20) to operate (active condition) or not to operate (idle condition), the internal logic state is determined (S202). In step S210, the user may manually set the input to correspond to the active or idle condition, or the input may be set automatically by a pre-coded program.

When the vertical synchronization (Vsync) signal is input, counting is performed to determine the waveform and timing of the control signal to be output accordingly (S203), and the control signal is output based on the internal logic state and counting condition (206). The control signal is output to the lighting controller 50 corresponding to the control unit for controlling the lighting device 30 to control the lighting (S500), and at the same time synchronized with the vertical synchronization (Vsync) signal, the image corresponding to the video frame is transferred to the camera. It is captured by the module (S209).

At this time, information on the control signal of the lighting device is returned (S207) and stored in the frame grabber 10 together with the captured image frame. In particular, a certain area where the control signal is stored is referred to as the frame information field 100.

In this way, with the frame grabber system according to an embodiment of the present invention, information on control signals of peripheral devices can be stored as well as image frames.

Subsequent steps S600 and S700 are simply exemplified for how to set the environment so that an optimal image frame can be captured by the camera module using the frame grabber system of the present invention.

A user may use a software program installed in a PC to change settings for factors capable of changing the output of the lighting device until the average value of the captured image frames satisfies a target value, which the user considers optimal. For example, the user may input delay and pulse width values of the control signal. In this case, if an environment is set with information about a control signal of an image frame in which an average value of captured image frames satisfies a target value, an optimal image frame can be captured by the corresponding camera module.

Although FIG. 3 shows that the information on the control signal is manually set by the user, it can be automatically adjusted as in the calibration unit 205 of FIG. 2 , of course.

Each of FIGS. 11, 12 and 13 is a schematic diagram showing an example of the frame information field 100 of FIG. 1 .

Referring to FIGS. 11 to 13, the frame information field 100 may be stored together with image data (represented as raw data in the drawing) corresponding to the video frame, although this drawing is not necessarily limited thereto. , it is shown that 32 bytes of data are added to the end of each horizontal data.

Referring to FIG. 11, for example, when the image size is 128 x 128 pixels and the RAW10 format is used, 32,768 bytes are required to store the entire data of the image. In addition, the frame information field proposed by the present invention stores It can be seen that an additional 32 bytes are required for each line for information and 4,096 bytes for one frame.

Referring to FIGS. 12 and 13, for example, if the image size is 5344 x 4016 pixels and the RAW10 format is selected, a selected part of the image starts at (1280, 2) and ends at (2560, 1282). Even when a 1280 x 1280 image is saved as one ROI frame, 32 bytes for each line and 40,960 bytes for one ROI frame are additionally required.

FIG. 13 shows information on the image frame (see FIG. 13(a)) and information on the control signal (see FIG. (b) reference), and the type and size of each information is illustrated. Of course, the present invention is not necessarily limited to the type and size of each piece of information shown in the drawings.

For example, the information on the video frame for each line may include the size (or location) of the frame of interest, the size (or position) of the current frame of interest, and the like of the entire frame, and the information on the control signal for each line may include lighting on. A period, a light-off period, the number of repetitions of lighting on/off, a delay, and a pulse width may be included.

The frame grabber system 1 according to embodiments may have an aspect of being entirely hardware, entirely software, or partly hardware and partly software. For example, the system may collectively refer to hardware equipped with data processing capability and operating software for driving the hardware. In this specification, terms such as "unit", "module", "device", or "system" are intended to refer to a combination of hardware and software driven by the hardware. For example, the hardware may be a data processing computing device including a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), or another processor. Also, software may refer to a running process, an object, an executable file, a thread of execution, a program, and the like.

Meanwhile, the methods according to the embodiments of the present invention may be at least partially implemented in the form of program instructions and recorded on a computer-readable recording medium. For example, implemented together with a program product consisting of a computer-readable medium containing program code, which may be executed by a processor to perform any or all steps, operations, or processes described.

The computer may be any device that may be integrated into or may be a computing device such as a desktop computer, laptop computer, notebook, smart phone, or the like. A computer is a device that has one or more alternative and special purpose processors, memory, storage, and networking components (whether wireless or wired). The computer may run, for example, an operating system compatible with Microsoft's Windows, Apple's OS X or iOS, a Linux distribution, or an operating system such as Google's Android OS.

The program instruction form may be collectively referred to as software, which may include a computer program, code, instruction, or a combination of one or more of them, and may cause a processing device to operate as desired. It can configure or command processing units independently or collectively. Software and/or data may be any tangible machine, component, physical device, virtual equipment, computer storage medium or device, intended to be interpreted by or to provide instructions or data to a processing device. may be permanently or temporarily embodied in Software may be distributed on networked computing devices and stored or executed in a distributed manner. Software and data may be stored on one or more computer readable media.

The computer readable recording medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the medium may be specially designed and configured for the embodiment, or may be known and usable to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. - includes hardware devices specially configured to store and execute program instructions, such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of program instructions include high-level language codes that can be executed by a computer using an interpreter, as well as machine language codes such as those produced by a compiler. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

In general, the terms used herein are generally intended to be "open-ended" terms, especially in the claims (e.g., the body of a claim) (e.g., "comprising" means "including but not limited to" , "has" should be construed as "has at least more", and "includes" as "including, but not limited to") If a specific number is intended for an introduced claim statement, such intent It is understood that as expressly recited in the claims, in the absence of such recitation, such intent is not present.

While only certain features of the present invention have been shown and described herein, various modifications and changes may occur to those skilled in the art. It is understood, therefore, that the claims are intended to cover such changes and modifications as fall within the spirit of the present invention.

1: frame grabber system 10: frame grabber
20: processor 30: lighting device
40: camera module 50: lighting controller
60: PC 70: monitor

Claims (12)

In the frame grabber system,
a frame grabber including a frame information field; and
A control signal for controlling peripheral devices is output based on the synchronization signal, and information on the control signal at the time of capturing the image frame is added to the image frame captured by the camera module in synchronization with the synchronization signal in the frame information field. Including the processor to store in,
The image frame is composed of a plurality of horizontal lines,
The frame information field includes information on the captured image frame for each line of the image frame and information on the control signal at the time of capturing the image frame, wherein the information on the control signal includes the synchronization signal Based on the factors used to determine whether to output a control signal for controlling the peripheral device, the frame grabber system. According to claim 1,
When the peripheral device is a lighting device and the control signal is a signal for controlling on/off of the lighting device, information on the control signal is factors used to determine on/off timing of the lighting device. At least one of an on period, a lighting off period, an on/off repetition number, a delay, and a pulse width, a frame grabber system. According to claim 2,
The synchronization signal is output from the frame grabber receiving the image frame from the camera module, or output from the processor. According to claim 3,
The processor
an input signal trigger unit that checks whether the synchronization signal is input;
an internal logic state determination unit determining whether to operate in synchronization with the synchronization signal;
a timing counting unit counting to determine timing of the control signal to be output based on the synchronization signal; and
A frame grabber system comprising a signal output unit for outputting the control signal in synchronization with the synchronization signal. A control method executed in a frame grabber system including a frame information field,
outputting a control signal for controlling a peripheral device based on the synchronization signal; and
storing information on the control signal at the time of capturing the image frame in the frame information field in addition to the image frame captured by the camera module in synchronization with the synchronization signal;
The image frame is composed of a plurality of horizontal lines,
The frame information field includes information on the captured image frame for each line of the image frame and information on the control signal at the time of capturing the image frame, wherein the information on the control signal includes the synchronization signal Factors used to determine whether to output a control signal for controlling a peripheral device based on, a control method. According to claim 5,
When the peripheral device is a lighting device and the control signal is a signal for controlling on/off of the lighting device, information on the control signal is factors used to determine on/off timing of the lighting device. At least one of an on period, a lighting off period, an on/off repetition number, a delay, and a pulse width, a control method. According to claim 6,
The synchronization signal is output from the frame grabber receiving the image frame from the camera module, or output from the processor. According to claim 7,
check whether the synchronization signal is input;
determine whether to operate in synchronization with the synchronization signal;
counting to determine timing of the control signal to output based on the synchronization signal;
and outputting the control signal in synchronization with the synchronization signal. A computer-readable recording medium recording a program for performing the method of any one of claims 5 to 8. A computer program stored in a medium for executing the method of any one of claims 5 to 8 through combination with hardware. delete delete

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