KR102490350B1 - Low-flicker-noise digital phase-locked loop using a proportional- and integral-gain co-optimization - Google Patents

Abstract

A digital phase-locked loop circuit with low flicker noise characteristics using proportional and integral gain joint optimization and its operating method are presented. The digital phase-locked loop circuit having low flicker noise characteristics using proportional and integral gain co-optimization proposed in the present invention is an OS TDC (Optimally- Spaced Time-to-Digital Converter), loop proportional path gain (K _P ) and integral path gain (K _I ) to reduce output jitter by removing flicker noise and thermal noise by receiving quantized timing error from OS TDC Including PICO (Proportional and integral gain Co-Optimization; PICO) that simultaneously adjusts PICO and a digitally controlled oscillator that controls the output frequency using the proportional path gain (K _P ) and integral path gain (K _I ) adjusted by PICO. do.

Description

Low-flicker-noise digital phase-locked loop using a proportional- and integral-gain co-optimization}

The present invention relates to a digital phase locked loop with low flicker noise characteristics using proportional and integral gain joint optimization.

Digital Phase-Locked Loops (DPLLs) based on Ring-type Digitally-Controlled Oscillators (RDCOs) offer high area efficiency, scalability to new CMOS processes, and loop characteristic correction. It offers many advantages over analog products, such as ease of use [1]. A key challenge to achieving low jitter performance in RDCO DPLLs is how to detect and correct the DCO's timing errors. To quantize this timing error, a time-to-digital converter (TDC) is most commonly used in DPLL design. The higher the resolution of the TDC, the lower the quantization error. A brute-force approach to minimizing the quantization error is to unconditionally reduce the interval between the time thresholds of the TDC to a level at which the amount of jitter is distinguishable. However, it requires a large number of time thresholds to sufficiently cover a wide dynamic range, greatly increasing power consumption [2].

1 is a diagram illustrating an RDCO-based DPLL using proportional gain optimization according to the prior art.

를 갖는다.

들 간의 최적의 간격을 유지하고(무조건적으로 줄이는 대신) K_P를 보정함으로써 [5]의 RDCO DPLL은 지터를 크게 줄이는 데 성공했다. 이러한 성과에도 불구하고 이전 DPLL [2]-[5]은 RDCO의 지터가 플리커 노이즈(flicker noise)를 무시하고 순전히 "백색" 가우시안이라는 잘못된 가정을 기반으로 K_P 만 최적화하기 때문에 지터를 최소화하는 데 근본적인 한계가 있다. 하지만 열 노이즈(thermal noise)와는 달리 플리커 노이즈의 에너지는 DC 근처의 저주파 오프셋에 집중되고 그 효과는 시간에 따른 RDCO 주파수의 랜덤 드리프트(random drift)로 나타난다[6]. 따라서, 플리커 노이즈를 억제하고 전체 지터를 더욱 줄이려면, K_P 뿐만 아니라 적분 경로의 이득 K_I 및 의 이득을 조정하여 플리커-유도 주파수 드리프트(f_D)를 보정해야 한다.In order to avoid this tradeoff between output jitter performance and power consumption in high-resolution TDC design, the prior art [2]-[4] uses a Bang-Bang Phase Detector (BBPD) as shown in FIG. We present a jitter minimization technique using background optimization of the loop's proportional gain K _P . This approach is very effective for low-power designs, but has limitations in reducing output jitter because the timing error information obtained from BBPD is too small for binary values. To overcome this limitation and reduce the output jitter, [5] presented a jitter minimization technique using three parallel BBPDs, each with a different time threshold,

have

By maintaining the optimal spacing between them (instead of reducing them unconditionally) and correcting K _P , the RDCO DPLL in [5] succeeded in significantly reducing the jitter. Despite these achievements, previous DPLLs [2]-[5] have struggled to minimize jitter because the jitter of _RDCO ignores flicker noise and only optimizes KP based on the false assumption that it is purely a "white" Gaussian. There are fundamental limitations. However, unlike thermal noise, the energy of flicker noise is concentrated in the low-frequency offset near DC, and the effect appears as a random drift of the RDCO frequency with time [6]. Therefore, to suppress the flicker noise and further reduce the overall jitter, the flicker-induced frequency drift (f _D ) must be corrected by adjusting the gain of K _P as well as the gain of K _I and the integral path.

A technical problem to be achieved by the present invention proposes an RDCO DPLL capable of achieving ultra-low jitter performance even at a high output frequency with severe flicker noise. In order to overcome the limitations of conventional DPLLs that optimize only the proportional path gain based on the erroneous assumption that the jitter of RDCO is white thermal noise, the present invention proposes a PICO that simultaneously optimizes the proportional path gain and the integral path gain.

In one aspect, a digital phase-locked loop circuit having low flicker noise characteristics using proportional and integral gain co-optimization proposed in the present invention acquires timing error information for flicker noise removal through a phase detector and quantizes the timing error. OS TDC (Optimally-Spaced Time-to-Digital Converter), the proportional path gain (K _P ) and integral path of the loop to reduce output jitter by receiving the quantized timing error from the OS TDC and removing flicker noise and thermal noise PICO (Proportional and integral gain Co-Optimization; PICO) that simultaneously adjusts the gain (K _I ) and controls the output frequency using the proportional path gain (K _P ) and integral path gain (K _I ) adjusted by PICO It includes a digitally controlled oscillator.

The OS TDC includes multiple BBPDs (Bang-Bang Phase Detectors) to avoid the tradeoff between output jitter performance and power consumption, and output jitter is determined using binary values of timing error information obtained from the multiple BBPDs. To reduce, each of the plurality of BBPDs has a different time threshold.

PICO reduces output jitter by avoiding jitter peaking caused by loop stability deterioration, and the proportional path gain of the loop (K _P ) and the integral path gain of the loop (K _I to achieve phase margin to reduce phase noise). ) to control.

To suppress the effects of white thermal noise, PICO optimizes the proportional path gain (K _P ) of the loop so that the timing errors detected in the current cycle and the next cycle of the loop are not correlated, resulting in a proportional path gain. Generates a digital code (D _KP ) that determines (K _P ).

To suppress the effects of flicker noise, PICO adjusts the integral path gain (K _I ) of the loop so that flicker-induced frequency drifts in the current cycle do not correlate with timing errors detected in the next cycle. Optimize to generate a digital code (D _KI ) that determines the integral path gain (K _I ).

The OS TDC quantizes the timing error between the reference signal and the feedback signal of the loop and provides the quantized signal to a digital loop filter (DLF) composed of a proportional path of the loop and an integral path of the loop.

After the DLF, PICO separately supplies the proportional and integral path delays to the digitally controlled oscillator to eliminate the additional loop delay caused by the digital summation of the proportional and integral paths, and eliminates the effect of output jitter due to the additional loop delay. Generates a digital code (D _KP ) that determines the proportional path gain (K _P ) and a digital code (D _KI ) that determines the integral path gain (K _I ) to suppress.

In PICO, the bandwidth of the loop for calibrating the integral path gain is set smaller than the bandwidth of the loop for calibrating the proportional path gain to ensure convergence of the digital code for determining the proportional path gain and the digital code for determining the integral path gain. , using an additional frequency acquisition path with a limiter to limit the bandwidth of the integration path to a smaller size.

In another aspect, a method of operating a digital phase-locked loop circuit having low flicker noise characteristics using proportional and integral gain co-optimization proposed in the present invention is an OS TDC (Optimally-Spaced Time-to-Digital Converter) phase Acquiring timing error information for flicker noise removal through a detector and quantizing the timing error, receiving the quantized timing error from the OS TDC through PICO (Proportional and integral gain Co-Optimization; PICO) to obtain flicker noise and thermal noise simultaneously adjusting the proportional path gain (K _{P )} and integral path gain (K _I ) of the loop to reduce output jitter by eliminating and controlling the output frequency using the path gain (K _I ).

Ultra-low jitter performance can be achieved even at a high output frequency with severe flicker noise through the RDCO DPLL according to embodiments of the present invention. In order to overcome the limitations of conventional DPLLs that optimize only the proportional path gain based on the erroneous assumption that the jitter of RDCO is white thermal noise, the present invention proposes a PICO that simultaneously optimizes the proportional path gain and the integral path gain. The proposed RDCO DPLL can effectively remove flicker noise and thermal noise through PICO.

의 변화를 나타내는 도면이다.
도 8은 본 발명의 일 실시예에 따른 비례 및 적분 이득 공동 최적화를 갖는 RDCO 기반 DPLL 회로의 동작 방법을 설명하기 위한 흐름도이다.
도 9는 본 발명의 일 실시예에 따른 RDCO DPLL의 다이 현미경 사진 및 전력 소비를 나타내는 도면이다.
도 10은 본 발명의 일 실시예에 따른 측정된 위상 노이즈 및 출력 스펙트럼을 나타내는 도면이다.
도 11은 본 발명의 일 실시예에 따른 출력 신호의 측정된 스펙트럼 및 위상 노이즈를 나타내는 도면이다.
도 12는 본 발명의 일 실시예에 따른 최첨단 링 오실레이터 기반 주파수 합성기와의 성능 비교를 나타내는 도면이다.1 is a diagram illustrating an RDCO-based DPLL using proportional gain optimization according to the prior art.
2 is a diagram illustrating a RDCO based DPLL circuit with proportional and integral gain joint optimization according to one embodiment of the present invention.
3 is a diagram for explaining phase noise suppression of RDCOs having different KIs according to an embodiment of the present invention.
4 is a diagram illustrating two loop gain optimization principles used in PICO in which KI and KP are optimally set according to an embodiment of the present invention.
5 is a block diagram for explaining a PICO path in which K _I and K _P are optimally set according to an embodiment of the present invention.
6 is a diagram showing the entire architecture of DPLL and PICO according to an embodiment of the present invention.
7 is a minimum achievable RMS jitter using NTDC according to an embodiment of the present invention.

It is a diagram showing the change of
8 is a flowchart illustrating an operating method of an RDCO-based DPLL circuit with proportional and integral gain joint optimization according to an embodiment of the present invention.
9 is a diagram showing a die micrograph and power consumption of an RDCO DPLL according to an embodiment of the present invention.
10 is a diagram showing measured phase noise and output spectrum according to an embodiment of the present invention.
11 is a diagram showing measured spectrum and phase noise of an output signal according to an embodiment of the present invention.
12 is a diagram showing performance comparison with a state-of-the-art ring oscillator-based frequency synthesizer according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a RDCO based DPLL circuit with proportional and integral gain joint optimization according to one embodiment of the present invention.

The proposed DPLL based on RDCO with proportional and integral gain co-optimization includes OS Optimally-Spaced Time-to-Digital Converter (TDC), Proportional and integral gain Co-Optimization (PICO) and digitally controlled oscillator. A digitally controlled oscillator according to an embodiment of the present invention may be a ring-type digitally-controlled oscillator (RDCO).

The OS TDC obtains timing error information for flicker noise removal through a phase detector and quantizes the timing error. The OS TDC includes multiple BBPDs (Bang-Bang Phase Detectors) to avoid the tradeoff between output jitter performance and power consumption, and output jitter is determined using binary values of timing error information obtained from the multiple BBPDs. To reduce, each of the plurality of BBPDs has a different time threshold.

PICO receives the quantized timing error from the OS TDC and simultaneously adjusts the proportional path gain (K _P ) and integral path gain (K _I ) of the loop to reduce output jitter by removing flicker noise and thermal noise.

PICO reduces output jitter by avoiding jitter peaking caused by loop stability deterioration, and the proportional path gain of the loop (K _P ) and the integral path gain of the loop (K _I to achieve phase margin to reduce phase noise). ) to control.

To suppress the effects of white thermal noise, PICO optimizes the proportional path gain (K _P ) of the loop so that the timing errors detected in the current cycle and the next cycle of the loop are not correlated, resulting in a proportional path gain. Generates a digital code (D _KP ) that determines (K _P ).

To suppress the effects of flicker noise, PICO adjusts the integral path gain (K _I ) of the loop so that flicker-induced frequency drifts in the current cycle do not correlate with timing errors detected in the next cycle. Optimize to generate a digital code (D _KI ) that determines the integral path gain (K _I ).

The OS TDC quantizes the timing error between the reference signal and the feedback signal of the loop and provides the quantized signal to a digital loop filter (DLF) composed of a proportional path of the loop and an integral path of the loop. At this time, PICO separately supplies the proportional path delay and the integral path delay to the digital control oscillator in order to eliminate the additional loop delay caused by the digital summation of the proportional path and the integral path after the DLF, and reduces the output jitter caused by the additional loop delay. A digital code (D _KP ) for determining the proportional path gain (K _P ) and a digital code (D _KI ) for determining the integral path gain (K _I ) are generated to suppress the influence.

PICO sets the bandwidth of the loop for calibrating the integral path gain to be smaller than the bandwidth of the loop for calibrating the proportional path gain to ensure convergence of the digital code for determining the proportional path gain and the digital code for determining the integral path gain. , using an additional frequency acquisition path with a limiter to limit the bandwidth of the integration path to a smaller size.

RDCO controls the output frequency using the proportional path gain (K _P ) and integral path gain (K _I ) adjusted by PICO. Hereinafter, the proposed RDCO-based DPLL with joint optimization of proportional and integral gains will be described in more detail with reference to FIGS. 2 to 8 .

간의 모든 간격은

교정기에 의해 제어되는 DTC(Digital-to-Time Converters)를 사용하여 백그라운드에서 최적화된다. According to an embodiment of the present invention, an ultra-low-jitter RDCO DPLL capable of removing flicker and thermal noise by simultaneously optimizing K _P and K _I as shown in FIG. 2 is proposed. In order to obtain more accurate information about the timing error for flicker noise cancellation, 7 BBPDs are used for optimally spaced Optimally-Spaced Time-to-Digital Converter (TDC) [5], i.e., N _TDC = 7 (how the value of N _TDC is selected is described below).

All intervals between

It is optimized in the background using digital-to-time converters (DTCs) controlled by the calibrator.

3 is a diagram for explaining phase noise suppression of _RDCOs having different KIs according to an embodiment of the present invention.

Figure 3 shows different RDCO phase-noise (PN) suppression mechanisms in the loop of type- _II DPLL for different values of KI. In the simulation, K _P is set to achieve a wide loop bandwidth of about 40 MHz by considering flicker noise with a corner frequency of 20 MHz (ie, 1/f corner frequency) in the noise profile of RDCO. Even if the bandwidth is the same, the DPLL's ability to suppress the PN of RDCO varies greatly with changes in K _I . When the K _I value is very small (since the zero of the loop gain of 310 in Fig. 3 appears at too low frequencies, the 40dB/dec-PN reduction performance is only effective at low frequency offsets. In this case, flicker noise can be suppressed at mid-frequency offsets. saturates the DPLL's in-band PN as the value of K _I increases, the position of the zero shifts to higher frequencies; thus a 40dB/dec-PN reduction is effective at higher offsets, but if K _I becomes too large (320 in Fig. 3), severe jitter peaking occurs due to loop stability deterioration, which increases overall jitter Finally, when K _I is set optimally (330 in Fig. 3), the PLL has minimum output jitter and a sufficiently wide phase. margin can be achieved.

FIG. 4 is a diagram illustrating two loop gain optimization principles used in PICO in which K _I and K _P are optimally set according to an embodiment of the present invention.

과 다음 주기

에서 감지된 타이밍 에러가 상관 관계가 없도록 K_P를 최적화하는 것이다(즉, 자기 상관

= 0, 여기서 T_REF 기준 주기이다). 원칙 ①을 준수하면 "백색" 열 노이즈를 억제할 수 있지만 플리커 노이즈의 영향을 완전히 제거할 수는 없다. 현재 주기의 f_D 인 f_D[n]이

에 영향을 미치는 것을 방지하려면 원칙 ②도 충족되어야 한다. f_D[n-1], f_D[n-2] 등 과의 상관 관계를 확인하는 것은 이론적으로 필요하지만 전체 지터의 추가적인 감소에 대한 실제 영향은 무시할 수 있다. 원칙 ①에서 K_P를 최적화하면 원칙 ②의 마지막 방정식의 첫 번째 항이 0이므로 2T_REF마다

의 자기 상관이 0, 즉

= 0이되도록 K_I를 최적화하여 원칙 ②의 조건을 만족할 수 있다. Principle ① is the current cycle

and next cycle

to optimize K _P so that the timing errors detected in

= 0, where T is the _REF reference period). Adhering to principle ① can suppress “white” thermal noise, but cannot completely eliminate the effects of flicker noise. If f _D [n], f _D of the current period,

Principle ② must also be satisfied in order to avoid influencing Correlation with f _D [n-1], f _D [n-2], etc. is theoretically necessary, but the practical impact on further reduction of total jitter is negligible. If K _P is optimized in principle ①, since the first term of the last equation in principle ② is 0, every 2T _REF

has an autocorrelation of 0, i.e.

= 0, the condition of principle _② can be satisfied.

5 is a block diagram for explaining a PICO path in which K _I and K _P are optimally set according to an embodiment of the present invention.

정보를 가지고 있는 OS TDC, D_TDC의 출력이 PICO에 제공된다. 그러면 PICO는 각각 K_P와 K_I를 결정하는 D_KP와 D_KI의 디지털 코드를 생성하여

와

가 모두 0이 되도록 한다. Figure 5 shows the implementation of the proposed PICO consisting of autocorrelation logic and accumulator.

The output of OS TDC, D _TDC with information is provided to PICO. PICO then generates digital codes for D _KP and D _KI that determine K _P and K _I respectively.

Wow

are all set to 0.

6 is a diagram showing the entire architecture of DPLL and PICO according to an embodiment of the present invention.

을 양자화하고, P-경로(P-path) 및 I-경로(I-path)로 구성되는 다음 DLF(Digital Loop Filter)에 D_TDC를 제공한다. D_P와 D_I의 두 경로에 있는 B2T(Binary-to-Digital Converter)의 출력 디지털 코드는 RDCO의 주파수를 제어하여

을 보정한다. DLF(일반적으로 재타이밍 프로세스(retiming process)를 위해 수행됨) 후, 두 경로의 디지털 합산으로 인해 발생하는 추가적인 루프 지연을 제거하기 위해 D_P와 D_I가 DCO에 별도로 공급되어, 추가적인 루프 지연으로 인한 출력 지터의 저하를 방지한다[2]. K_P 및 K_I를 정확하게 조정하기 위해 PICO는 각각 D_KP 및 D_KI를 통해 P-경로 및 I-경로의

를 제어한다. 캐스케이드(cascaded)

및 RC 필터를 통과한 후 D_KP 및 D_KI는 각각 V_KP 및 V_KI로 변환된다. 이후, V_KP 및 V_KI가 매우 정확하게 D_P 및 D_I(즉, 각각 K_P 및 K_I)의 가중치를 결정한다. ADH-SC(Analog-Digital-Hybrid Switched Capacitors)[5]는 DCO에 사용되어 DCO의 주파수가 D_x의 변화에 즉시 반응하는 동시에 K_x는 V_Kx에 따라 정확하게 제어된다(x는 P 또는 I). I-경로 이득 교정 루프의 대역폭은 P-경로 이득 교정 루프보다 훨씬 좁게 설계 되었기 때문에, 안정성 문제없이 D_KP와 D_KI의 수렴을 보장할 수 있다. I-경로의 제한된 튜닝 범위를 보완하기 위해 리미터와 함께 추가적인 주파수 획득 경로를 사용하여 안정성을 보장하기 위한 I-경로의 대역폭보다 훨씬 더 작게 제한한다. 고정(locking)을 촉진하는 코어스(coarse) PD는 초기 단계에서와 같이

이 클 때만 활성화된다. DCO의 잡음을 억제하는 DPLL의 성능을 높이기 위해, FPEC-DLF 로직에서 제공되는 SFPEC의 짧은 기간 동안 P-경로 이득을 부스팅함으로써 FPEC(Fast Phase-Error Correction) 기술[5]이 DLF에서 구현된다. OS TDC is the difference between S _REF and S _DIV .

is quantized, and D _TDC is provided to the next Digital Loop Filter (DLF) composed of a P-path and an I-path. The output digital code of B2T (Binary-to-Digital Converter) in the two paths of D _P and D _I controls the frequency of RDCO to

correct the After the DLF (usually done for the retiming process), _DP and DI are fed separately to the _DCO to eliminate the additional loop delay caused by the digital summation of the two paths, resulting in It prevents degradation of output jitter [2]. In order to accurately tune K _P and K _I , PICO controls the P-path and I-path parameters via D _KP and D _KI , respectively.

to control cascaded

and RC filters, D _KP and D _KI are converted into V _KP and V _KI , respectively. Then, V _KP and V _KI determine the weights of D _P and D _I (ie, K _P and K _I , respectively) very accurately. ADH-SC (Analog-Digital-Hybrid Switched Capacitors) [5] are used in the DCO so that the frequency of the DCO responds immediately to changes in D _x while K _x is precisely controlled according to V _Kx (x is either P or I) . Since the bandwidth of the I-path gain calibration loop is designed to be much narrower than that of the P-path gain calibration loop, convergence of D _KP and D _KI can be guaranteed without stability problems. To compensate for the limited tuning range of the I-path, an additional frequency acquisition path with a limiter is used to limit it to a much smaller bandwidth than the I-path's bandwidth to ensure stability. Coarse PD, which promotes locking, as in the early stages

Activated only when To improve the performance of the DPLL in suppressing the noise of the DCO, the Fast Phase-Error Correction (FPEC) technique [5] is implemented in the DLF by boosting the P-path gain for a short period of SFPEC provided in the FPEC-DLF logic.

의 변화를 나타내는 도면이다. 7 shows the minimum achievable RMS jitter using N _TDCs according to an embodiment of the present invention.

It is a diagram showing the change of

값으로 정규화된다. 데이터는 Simulink를 통한 행동 시뮬레이션을 사용하여 얻었으며 K_P, K_I 및

의 값은 각 N_TDC에 대해 최적화되었다. 1/f 코너 주파수가 0MHz에서 20MHz로 증가함에 따라 정규화된

의 레벨이 전반적으로 증가하고, 그것의 N_TDC에 따른 감소는 더욱 크다. 두 경우에서

의 감쇠는 N_TDC가 증가함에 따라 느리고 N_TDC가 7보다 크거나 같을 때 거의 포화된다. 본 발명의 실시예에 따라 설계된 DCO는 20MHz 1/f 코너 주파수를 가지므로, 본 발명의 실시예에서는 N_TDC를 7로 고정한다. Referring to FIG. 7, the ideal N _TDC is infinite and exists only in thermal noise in DCO.

normalized to the value Data were obtained using behavioral simulations with Simulink, and K _P , K _I and

The value of is optimized for each N _TDC . Normalized as 1/f corner frequency increases from 0 MHz to 20 MHz

The level of β increases overall, and its decrease according to N _TDC is greater. in both cases

The decay of is slow as N _TDC increases and becomes almost saturated when N _TDC is greater than or equal to 7. Since the DCO designed according to the embodiment of the present invention has a 20 MHz 1/f corner frequency, N _TDC is fixed to 7 in the embodiment of the present invention.

8 is a flowchart illustrating an operating method of an RDCO-based DPLL circuit with proportional and integral gain joint optimization according to an embodiment of the present invention.

The operating method of the proposed RDCO-based DPLL circuit with proportional and integral gain co-optimization is

OS TDC (Optimally-Spaced Time-to-Digital Converter) obtains timing error information for flicker noise removal through a phase detector and quantizes the timing error (810), PICO (Proportional and integral gain Co-Optimization; PICO ) to receive the quantized timing error from the OS TDC and simultaneously adjust the proportional path gain (K _P ) and the integral path gain (K _I ) of the loop to reduce output jitter by removing flicker noise and thermal noise ( 820) and controlling the output frequency by the digitally controlled oscillator using the proportional path gain (K _P ) and the integral path gain (K _I ) adjusted by the PICO (830).

In step 810, the OS TDC obtains timing error information for flicker noise cancellation through the phase detector and quantizes the timing error.

The OS TDC includes multiple BBPDs (Bang-Bang Phase Detectors) to avoid the tradeoff between output jitter performance and power consumption, and output jitter is determined using binary values of timing error information obtained from the multiple BBPDs. To reduce, each of the plurality of BBPDs has a different time threshold.

In step 820, PICO receives the quantized timing error from the OS TDC and adjusts the proportional path gain (K _P ) and the integral path gain (K _I ) of the loop to reduce output jitter by removing flicker noise and thermal noise. adjust at the same time

PICO reduces output jitter by avoiding jitter peaking caused by loop stability deterioration, and the proportional path gain of the loop (K _P ) and the integral path gain of the loop (K _I to achieve phase margin to reduce phase noise). ) to control.

To suppress the effects of white thermal noise, PICO optimizes the proportional path gain (K _P ) of the loop so that the timing errors detected in the current cycle and the next cycle of the loop are not correlated, resulting in a proportional path gain. Generates a digital code (D _KP ) that determines (K _P ).

To suppress the effects of flicker noise, PICO adjusts the integral path gain (K _I ) of the loop so that flicker-induced frequency drifts in the current cycle do not correlate with timing errors detected in the next cycle. Optimize to generate a digital code (D _KI ) that determines the integral path gain (K _I ).

The OS TDC quantizes the timing error between the reference signal and the feedback signal of the loop and provides the quantized signal to a digital loop filter (DLF) composed of a proportional path of the loop and an integral path of the loop. At this time, PICO separately supplies the proportional path delay and the integral path delay to the digital control oscillator in order to eliminate the additional loop delay caused by the digital summation of the proportional path and the integral path after the DLF, and reduces the output jitter caused by the additional loop delay. A digital code (D _KP ) for determining the proportional path gain (K _P ) and a digital code (D _KI ) for determining the integral path gain (K _I ) are generated to suppress the influence.

PICO sets the bandwidth of the loop for calibrating the integral path gain to be smaller than the bandwidth of the loop for calibrating the proportional path gain to ensure convergence of the digital code for determining the proportional path gain and the digital code for determining the integral path gain. , using an additional frequency acquisition path with a limiter to limit the bandwidth of the integration path to a smaller size.

At step 830, RDCO controls the output frequency using the proportional path gain (K _P ) and the integral path gain (K _I ) adjusted by PICO.

9 is a diagram showing a die micrograph and power consumption of an RDCO DPLL according to an embodiment of the present invention.

9(a) shows a die micrograph of the proposed RDCO DPLL fabricated by 65nm CMOS technology. It occupies an active area of 0.075 mm ² . As shown in FIG. 9(b), the total power consumption is about 6.5 mW. RDCO consumed 4.1mW and other circuitry in the loop such as divider, digital logic and OS TDC consumed 2.38mW.

10 is a diagram showing measured phase noise and output spectrum according to an embodiment of the present invention.

10 (above graph) shows a 120 MHz reference clock when both K _I and K _P are optimized by PICO (1010 in FIG. 10), and only K _P is optimized and K _I is set to a small value (1020 in FIG. 10). is used to represent the measured PN of the 7.68 GHz output signal. The phase noise analyzer of the R&S FSWP was used for PN measurements. As shown in FIG. 10, since the wide loop bandwidth (about 40 MHz) due to FPEC greatly suppressed the free-running PN of RDCO, when only K _P was optimized (1020 in FIG. 10), a relatively low 100 -kHz PN and RMS jitter, -100dBc/Hz and 464fs, respectively, have already been achieved. When PICO is fully operational and both K _P and K _I are optimized (1010 in FIG. 10), these two values significantly decrease to -115.0 dBc/Hz and 373 fs, respectively. Even in the PN of the free-running DCO due to the PCB, there is a bump in the PN plot between the 7 and 10 MHz offset. Figure 10 (bottom graph) shows the measured output spectrum of a 7.68 GHz output signal captured by a spectrum analyzer on a Keysight N9030A.

11 is a diagram showing measured spectrum and phase noise of an output signal according to an embodiment of the present invention.

At 120 MHz offset, the level of the reference spur was -65 dBc. PN and spectrum were measured at different output frequencies (7.872 GHz (FIG. 11(a)) and 7.808 GHz (FIG. 11(b))) according to an embodiment of the present invention. 100 kHz PN, RMS jitter and reference spur level are respectively Limited to less than -115 dBc/Hz, 370 fs and -65 dBc Table 1 compares the performance of this embodiment of the present invention with that of a state-of-the-art ring oscillator based frequency synthesizer.

<Table 1>

Due to suppression of white heat and flicker noise by PICO, the proposed circuit achieves the lowest in-band PN (-132.7dBc/Hz for 100kHz PN normalized to 1GHz) among the designs in Table 1. The proposed DPLL has very severe flicker noise at the highest f _OUT generation (1/f corner frequency = 19 MHz). For this reason, the minimum achievable RMS jitter and hence the jitter FOM, FOM _JIT , are necessarily higher than other jitter with less flicker noise. Nevertheless, the proposed DPLL has very low RMS jitter and FOM _JIT compared to other architectures in Table 1.

12 is a diagram showing performance comparison with a state-of-the-art ring oscillator-based frequency synthesizer according to an embodiment of the present invention.

12 shows a performance comparison with a state-of-the-art frequency synthesizer in terms of FOM _JIT and FOM _JIT,N considering the effect of N. Despite the high f _OUT and N, the proposed RDCO DPLL achieves excellent performance of FOM _JIT and FOM _JIT,N . This is the first RDCO DPLL to achieve -240dB FOM _JIT at f _OUT above 7GHz.

The present invention proposes an RDCO DPLL capable of achieving ultra-low jitter performance even at a high output frequency with severe flicker noise. In order to overcome the limitations of conventional DPLLs that optimize only the P-path gain based on the erroneous assumption that RDCO jitter is white thermal noise, the present invention proposes a PICO that simultaneously optimizes the P-path and I-path gains. The proposed RDCO DPLL can effectively remove flicker and thermal noise through PICO.

The devices described above may be implemented as hardware components, software components, and/or a combination of hardware components and software components. For example, devices and components described in the embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), It may be implemented using one or more general purpose or special purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. A processing device may run an operating system (OS) and one or more software applications running on the operating system. A processing device may also access, store, manipulate, process, and generate data in response to execution of software. For convenience of understanding, there are cases in which one processing device is used, but those skilled in the art will understand that the processing device includes a plurality of processing elements and/or a plurality of types of processing elements. It can be seen that it can include. For example, a processing device may include a plurality of processors or a processor and a controller. Other processing configurations are also possible, such as parallel processors.

Software may include a computer program, code, instructions, or a combination of one or more of the foregoing, which configures a processing device to operate as desired or processes independently or collectively. You can command the device. Software and/or data may be any tangible machine, component, physical device, virtual equipment, computer storage medium or device, intended to be interpreted by or provide instructions or data to a processing device. can be embodied in Software may be distributed on networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer readable media.

The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program commands recorded on the medium may be specially designed and configured for the embodiment or may be known and usable to those skilled in computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks and magnetic tapes, optical media such as CD-ROMs and DVDs, and magnetic media such as floptical disks. - includes hardware devices specially configured to store and execute program instructions, such as magneto-optical media, and ROM, RAM, flash memory, and the like. Examples of program instructions include high-level language codes that can be executed by a computer using an interpreter, as well as machine language codes such as those produced by a compiler.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

<References>

[1] R. B. Staszewski et al., "All-Digital PLL and Transmitter for Mobile Phones," IEEE J. Solid-State Circuits, vol. 40, no. 12, p. 2469-2482, Dec. 2005.

[2] T. K. Kuan and S. I. Liu, "A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques," IEEE J. Solid-State Circuits, vol. 51, no. 4, p. 821-831, Apr. 2016.

[3] M. Zanuso, D. Tasca, S. Levantino, A. Donadel, C. Samori, and A. L. Lacaita, "Noise Analysis and Minimization in Bang-Bang Digital PLLs," IEEE Trans. Circuits Syst. II Express Briefs, vol. 56, no. 11, p. 835-839, Nov. 2009.

[4] S. Jang, S. Kim, S. H. Chu, G. S. Jeong, Y. Kim, and D. K. Jeong, "An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection," IEEE Trans. Circuits Syst. II Express Briefs, vol. 62, no. 9, p. 836-840, Sep. 2015.

[5] T. Seong, Y. Lee, S. Yoo, and J. Choi, "A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC," IEEE J. Solid-State Circuits, vol. 54, no. 9, p. 2501-2512, Sep. 2019.

[6] A. A. Abidi, "Phase Noise and Jitter in CMOS Ring Oscillators," IEEE J. Solid-State Circuits, vol. 41, no. 8, p. 1803-1816, 2006.

[7] S. Lloyd, "Least squares quantization in PCM," IEEE Trans. Inf. Theory, vol. 28, no. 2, p. 129-137, Mar. 1982.

[8] G. Marucci, S. Levantino, P. Maffezzoni, and C. Samori, "Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs," IEEE Trans. Circuits Syst. II Express Briefs, vol. 60, no. 10, p. 632-636, Oct. 2013.

Claims (16)

an OS Optimally-Spaced Time-to-Digital Converter (TDC) that obtains timing error information for flicker noise removal through a phase detector and quantizes the timing error;
PICO (Proportional and integral) that simultaneously adjusts the proportional path gain (K _P ) and integral path gain (K _I ) of the loop to reduce output jitter by receiving quantized timing errors from the OS TDC and removing flicker noise and thermal noise gain Co-Optimization; PICO); and
Digitally controlled oscillator that controls the output frequency using the proportional path gain (K _P ) and integral path gain (K _I ) adjusted by PICO
including,
The PICO,
Controls the loop's proportional path gain (K _P ) and loop's integral path gain (K _I ) to reduce output jitter by preventing jitter peaking caused by loop stability deterioration and achieve phase margin to reduce phase noise and
To suppress the effects of white thermal noise, the proportional path gain (K _P ) of the loop is optimized so that the timing errors detected in the current cycle and the next cycle of the loop are not correlated, so that the proportional path gain (K _P ) to generate a digital code (D _KP ) that determines
Digital phase locked loop circuit. According to claim 1,
The OS TDC,
In order to avoid a tradeoff between output jitter performance and power consumption, a plurality of Bang-Bang Phase Detectors (BBPDs) are included, and output jitter is reduced using binary values of timing error information obtained from the plurality of BBPDs. Each of the plurality of BBPDs has a different time threshold
Digital phase locked loop circuit. delete delete According to claim 1,
The PICO,
To suppress the effects of flicker noise, the loop's integration path gain (K _I ) is optimized so that the flicker-induced frequency drifts in the current cycle do not correlate with the timing errors detected in the next cycle. generating a digital code (D _KI ) that determines the integral path gain (K _I )
Digital phase locked loop circuit. According to claim 1,
The OS TDC,
Quantizes the timing error between the reference signal and the feedback signal of the loop and provides the quantized signal to the Digital Loop Filter (DLF) composed of the proportional path of the loop and the integral path of the loop.
Digital phase locked loop circuit. According to claim 6,
The PICO,
After the DLF, the proportional path delay and the integral path delay are separately supplied to the digitally controlled oscillator to eliminate the additional loop delay caused by the digital summation of the proportional and integral paths, and to suppress the effect of output jitter due to the additional loop delay. generating a digital code (D _KP ) that determines the proportional path gain (K _P ) and a digital code (D _KI ) that determines the integral path gain (K _I )
Digital phase locked loop circuit. According to claim 7,
To ensure convergence of the digital code for determining the proportional path gain and the digital code for determining the integral path gain, the bandwidth of the loop for calibrating the integral path gain is set smaller than the bandwidth of the loop for calibrating the proportional path gain, and the limiter to limit the bandwidth of the integration path to a smaller size by using an additional frequency acquisition path with
Digital phase locked loop circuit. obtaining timing error information for removing flicker noise through an OS TDC (Optimally-Spaced Time-to-Digital Converter) through a phase detector and quantizing the timing error;
Proportional path gain (K _P ) and integral path of loop to reduce output jitter by receiving quantized timing error from OS TDC through PICO (Proportional and integral gain Co-Optimization; PICO) and removing flicker noise and thermal noise simultaneously adjusting the gain (K _I ); and
A digitally controlled oscillator controlling an output frequency using a proportional path gain (K _P ) and an integral path gain (K _I ) adjusted by PICO.
including,
Simultaneously adjusting a proportional path gain (K _P ) and an integral path gain (K _I ) of a loop to reduce output jitter by receiving the quantized timing error from the OS TDC through the PICO and removing flicker noise and thermal noise. Is,
Controls the loop's proportional path gain (K _P ) and loop's integral path gain (K _I ) to reduce output jitter by preventing jitter peaking caused by loop stability deterioration and achieve phase margin to reduce phase noise and
To suppress the effects of white thermal noise, the proportional path gain (K _P ) of the loop is optimized so that the timing errors detected in the current cycle and the next cycle of the loop are not correlated, so that the proportional path gain (K _P ) to generate a digital code (D _KP ) that determines
How digital phase locked loop circuits work. According to claim 9,
The OS TDC obtaining timing error information for flicker noise removal through a phase detector and quantizing the timing error,
In order to avoid a tradeoff between output jitter performance and power consumption, a plurality of Bang-Bang Phase Detectors (BBPDs) are included, and output jitter is reduced using binary values of timing error information obtained from the plurality of BBPDs. Each of the plurality of BBPDs has a different time threshold
How digital phase locked loop circuits work. delete delete According to claim 9,
To suppress the effects of flicker noise, the loop's integration path gain (K _I ) is optimized so that the flicker-induced frequency drifts in the current cycle do not correlate with the timing errors detected in the next cycle. generating a digital code (D _KI ) that determines the integral path gain (K _I )
How digital phase locked loop circuits work. According to claim 9,
The OS TDC obtaining timing error information for flicker noise removal through a phase detector and quantizing the timing error,
Quantizes the timing error between the reference signal and the feedback signal of the loop and provides the quantized signal to the Digital Loop Filter (DLF) composed of the proportional path of the loop and the integral path of the loop.
How digital phase locked loop circuits work. According to claim 14,
Simultaneously adjusting a proportional path gain (K _P ) and an integral path gain (K _I ) of a loop to reduce output jitter by receiving the quantized timing error from the OS TDC through the PICO and removing flicker noise and thermal noise. Is,
After the DLF, the proportional and integral path delays are separately supplied to the digitally controlled oscillator to eliminate the additional loop delay caused by the digital summation of the proportional and integral paths, suppressing the effect of output jitter due to the additional loop delay. generating a digital code (D _KP ) that determines the proportional path gain (K _P ) and a digital code (D _KI ) that determines the integral path gain (K _I )
How digital phase locked loop circuits work. According to claim 15,
To ensure convergence of the digital code for determining the proportional path gain and the digital code for determining the integral path gain, the bandwidth of the loop for calibrating the integral path gain is set smaller than the bandwidth of the loop for calibrating the proportional path gain, and the limiter to limit the bandwidth of the integration path to a smaller size by using an additional frequency acquisition path with
How digital phase locked loop circuits work.

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